Hello,
This series adds support to the pci-j721e PCIe controller for up to 4x Lane
configuration supported by TI's J784S4 SoC. Bindings are also added for
the num-lanes property which shall be used by the driver. The compatible
for J784S4 SoC is added.
This series is based on linux-next tagged next-20231128.
Regards,
Siddharth.
---
v12:
https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
Changes since v12:
- Rebased series on linux-next tagged next-20231128.
- Reordered patches with bindings patches first followed by driver
patches.
- Collected Reviewed-by tag from
Krzysztof Kozlowski <[email protected]>
which was missed in the v12 series as pointed out at:
https://patchwork.kernel.org/project/linux-pci/patch/[email protected]/
Matt Ranostay (5):
dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes
dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add PCIe 4x lane selection support
PCI: j721e: add j784s4 PCIe configuration
.../bindings/pci/ti,j721e-pci-ep.yaml | 39 ++++++++++++++--
.../bindings/pci/ti,j721e-pci-host.yaml | 39 ++++++++++++++--
drivers/pci/controller/cadence/pci-j721e.c | 45 ++++++++++++++++---
3 files changed, 112 insertions(+), 11 deletions(-)
--
2.34.1
From: Matt Ranostay <[email protected]>
Various platforms have different maximum amount of lanes that can be
selected. Add max_lanes to struct j721e_pcie to allow for detection of this
which is needed to calculate the needed bitmask size for the possible lane
count.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 2c87e7728a65..63c758b14314 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -47,8 +47,6 @@ enum link_status {
#define GENERATION_SEL_MASK GENMASK(1, 0)
-#define MAX_LANES 2
-
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
struct clk *refclk;
@@ -71,6 +69,7 @@ struct j721e_pcie_data {
unsigned int quirk_disable_flr:1;
u32 linkdown_irq_regfield;
unsigned int byte_access_allowed:1;
+ unsigned int max_lanes;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
.mode = PCI_MODE_EP,
.quirk_detect_quiet_flag = true,
.quirk_disable_flr = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
.mode = PCI_MODE_RC,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 1,
};
static const struct j721e_pcie_data am64_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = J7200_LINK_DOWN,
+ .max_lanes = 1,
};
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -432,8 +437,10 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > MAX_LANES)
+ if (ret || num_lanes > data->max_lanes) {
+ dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
num_lanes = 1;
+ }
pcie->num_lanes = num_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
--
2.34.1
From: Matt Ranostay <[email protected]>
Add PCIe configuration for j784s4 platform which has 4x lane support.
Tested-by: Achal Verma <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 645597856a1d..85718246016b 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
.max_lanes = 1,
};
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+ .mode = PCI_MODE_RC,
+ .quirk_retrain_flag = true,
+ .byte_access_allowed = false,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+ .mode = PCI_MODE_EP,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
static const struct of_device_id of_j721e_pcie_match[] = {
{
.compatible = "ti,j721e-pcie-host",
@@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
.compatible = "ti,am64-pcie-ep",
.data = &am64_pcie_ep_data,
},
+ {
+ .compatible = "ti,j784s4-pcie-host",
+ .data = &j784s4_pcie_rc_data,
+ },
+ {
+ .compatible = "ti,j784s4-pcie-ep",
+ .data = &j784s4_pcie_ep_data,
+ },
{},
};
--
2.34.1
On 11/28/23 11:14 AM, Siddharth Vadapalli wrote:
> From: Matt Ranostay <[email protected]>
>
> Various platforms have different maximum amount of lanes that can be
> selected. Add max_lanes to struct j721e_pcie to allow for detection of this
> which is needed to calculate the needed bitmask size for the possible lane
> count.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Achal Verma <[email protected]>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 2c87e7728a65..63c758b14314 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -47,8 +47,6 @@ enum link_status {
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
>
> -#define MAX_LANES 2
> -
> struct j721e_pcie {
> struct cdns_pcie *cdns_pcie;
> struct clk *refclk;
> @@ -71,6 +69,7 @@ struct j721e_pcie_data {
> unsigned int quirk_disable_flr:1;
> u32 linkdown_irq_regfield;
> unsigned int byte_access_allowed:1;
> + unsigned int max_lanes;
> };
>
> static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
> @@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
> .quirk_retrain_flag = true,
> .byte_access_allowed = false,
> .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j721e_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j7200_pcie_rc_data = {
> @@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
> .quirk_detect_quiet_flag = true,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j7200_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .quirk_detect_quiet_flag = true,
> .quirk_disable_flr = true,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data am64_pcie_rc_data = {
> .mode = PCI_MODE_RC,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> + .max_lanes = 1,
> };
>
> static const struct j721e_pcie_data am64_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> + .max_lanes = 1,
> };
>
> static const struct of_device_id of_j721e_pcie_match[] = {
> @@ -432,8 +437,10 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> pcie->user_cfg_base = base;
>
> ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> - if (ret || num_lanes > MAX_LANES)
> + if (ret || num_lanes > data->max_lanes) {
> + dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
> num_lanes = 1;
> + }
> pcie->num_lanes = num_lanes;
>
> if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
Reviewed-by: Ravi Gunasekaran <[email protected]>
--
Regards,
Ravi
Hi Bjorn, Krzysztof, Lorenzo, Rob,
On Tue, Nov 28, 2023 at 11:13:57AM +0530, Siddharth Vadapalli wrote:
> This series adds support to the pci-j721e PCIe controller for up to 4x Lane
> configuration supported by TI's J784S4 SoC. Bindings are also added for
> the num-lanes property which shall be used by the driver. The compatible
> for J784S4 SoC is added.
>
> This series is based on linux-next tagged next-20231128.
These patches have been floating around for a long time (v12 was almost
identical and was submitted back in April, without any review back then
already [1]), and it looks like reviewers are happy with it.
Could you merge them to get them in 6.8?
Thanks!
Maxime
1: https://lore.kernel.org/lkml/[email protected]/
Hello,
> This series adds support to the pci-j721e PCIe controller for up to 4x Lane
> configuration supported by TI's J784S4 SoC. Bindings are also added for
> the num-lanes property which shall be used by the driver. The compatible
> for J784S4 SoC is added.
>
> This series is based on linux-next tagged next-20231128.
Applied to controller/cadence, thank you!
[01/05] dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes
https://git.kernel.org/pci/pci/c/b3ba0f6e82cb
[02/05] dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings
https://git.kernel.org/pci/pci/c/adc14d44d7cb
[03/05] PCI: j721e: Add per platform maximum lane settings
https://git.kernel.org/pci/pci/c/3ac7f14084f5
[04/05] PCI: j721e: Add PCIe 4x lane selection support
https://git.kernel.org/pci/pci/c/4490f559f755
[05/05] PCI: j721e: Add j784s4 PCIe configuration
https://git.kernel.org/pci/pci/c/9ca59b45ecf3
Krzysztof
Hi Maxime,
> > This series adds support to the pci-j721e PCIe controller for up to 4x Lane
> > configuration supported by TI's J784S4 SoC. Bindings are also added for
> > the num-lanes property which shall be used by the driver. The compatible
> > for J784S4 SoC is added.
> >
> > This series is based on linux-next tagged next-20231128.
>
> These patches have been floating around for a long time (v12 was almost
> identical and was submitted back in April, without any review back then
> already [1]), and it looks like reviewers are happy with it.
Having a glance, it looks good to me, too.
> Could you merge them to get them in 6.8?
Applied, so it should make it to 6.8. Apologies for the delay.
Krzysztof