This series hooks up MPM (which can finally be done after winning the
lengthy bindings fight) on 6375, 8996 and 2290 as a good start.
The hardware in question is present on all RPM SMD SoCs (so, roughly
msm8974 and up), which means many more platforms are there to come.
MPM is one of the key pieces for allowing full system power collapse
(and perhaps as importantly, resume) and serves roughly the same role
as PDC on RPMh SoCs for this purpose.
Signed-off-by: Konrad Dybcio <[email protected]>
---
Konrad Dybcio (3):
arm64: dts: qcom: sm6375: Hook up MPM
arm64: dts: qcom: msm8996: Hook up MPM
arm64: dts: qcom: qcm2290: Hook up MPM
arch/arm64/boot/dts/qcom/msm8996.dtsi | 39 +++++++++++++++++++++++++++-----
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 42 +++++++++++++++++++++++++++++------
arch/arm64/boot/dts/qcom/sm6375.dtsi | 41 ++++++++++++++++++++++++++++------
3 files changed, 102 insertions(+), 20 deletions(-)
---
base-commit: 11651f8cb2e88372d4ed523d909514dc9a613ea3
change-id: 20231215-topic-mpm_dt-3811720cf884
Best regards,
--
Konrad Dybcio <[email protected]>
Add a node for MPM and wire it up on consumers that use it. This also
fixes a very bad and sad assumption I made when initially porting this
SoC that the downstream MPM-TLMM mappings were 1-1. That apparently
changed some time ago, so with this patch the MPM consumers will actually
be hooked up to the correct interrupt lines.
Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375")
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6375.dtsi | 41 ++++++++++++++++++++++++++++++------
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 331bd98dbfde..7ac8bf26dda3 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -311,6 +311,25 @@ scm {
};
};
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */
+ <12 422>, /* DWC3 ss_phy_irq */
+ <86 183>, /* MPM wake, SPMI */
+ <89 314>, /* TSENS0 0C */
+ <90 315>, /* TSENS1 0C */
+ <93 164>, /* DWC3 dm_hs_phy_irq */
+ <94 165>; /* DWC3 dp_hs_phy_irq */
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -486,6 +505,7 @@ CPU_PD7: power-domain-cpu7 {
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
+ power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
};
@@ -808,7 +828,7 @@ tlmm: pinctrl@500000 {
reg = <0 0x00500000 0 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 157>;
- /* TODO: Hook up MPM as wakeup-parent when it's there */
+ wakeup-parent = <&mpm>;
interrupt-controller;
gpio-controller;
#interrupt-cells = <2>;
@@ -960,7 +980,7 @@ spmi_bus: spmi@1c40000 {
<0 0x01c0a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@@ -992,8 +1012,15 @@ tsens1: thermal-sensor@4413000 {
};
rpm_msg_ram: sram@45f0000 {
- compatible = "qcom,rpm-msg-ram";
+ compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0 0x045f0000 0 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x045f0000 0x7000>;
+
+ apss_mpm: sram@1b8 {
+ reg = <0x1b8 0x48>;
+ };
};
sram@4690000 {
@@ -1403,10 +1430,10 @@ usb_1: usb@4ef8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <133333333>;
- interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 94 IRQ_TYPE_EDGE_BOTH>;
+ interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 93 IRQ_TYPE_EDGE_BOTH>,
+ <&mpm 94 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",
--
2.40.1
Wire up MPM and the interrupts it provides.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 39 +++++++++++++++++++++++++++++------
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 35a0d2a69711..11e3fe4f342f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -444,6 +444,25 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <2 184>, /* TSENS1 upper_lower_int */
+ <52 243>, /* DWC3_PRI ss_phy_irq */
+ <79 347>, /* DWC3_PRI hs_phy_irq */
+ <80 352>, /* DWC3_SEC hs_phy_irq */
+ <81 347>, /* QUSB2_PHY_PRI DP+DM */
+ <82 352>, /* QUSB2_PHY_SEC DP+DM */
+ <87 326>; /* SPMI */
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -733,8 +752,15 @@ pciephy_2: phy@3000 {
};
rpm_msg_ram: sram@68000 {
- compatible = "qcom,rpm-msg-ram";
+ compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x00068000 0x6000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00068000 0x7000>;
+
+ apss_mpm: sram@1b8 {
+ reg = <0x1b8 0x48>;
+ };
};
qfprom@74000 {
@@ -820,8 +846,8 @@ tsens1: thermal-sensor@4ad000 {
reg = <0x004ad000 0x1000>, /* TM */
<0x004ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
@@ -1343,6 +1369,7 @@ tlmm: pinctrl@1010000 {
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 150>;
+ wakeup-parent = <&mpm>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1870,7 +1897,7 @@ spmi_bus: spmi@400f000 {
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 87 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@@ -3026,8 +3053,8 @@ usb3: usb@6af8800 {
#size-cells = <1>;
ranges;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 79 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
--
2.40.1
Wire up MPM and the interrupts it provides.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 42 +++++++++++++++++++++++++++++------
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index ce04d0acdede..0911fb08ed63 100644
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -199,6 +199,7 @@ CPU_PD3: power-domain-cpu3 {
CLUSTER_PD: power-domain-cpu-cluster {
#power-domain-cells = <0>;
+ power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP>;
};
};
@@ -266,6 +267,24 @@ rpmpd_opp_turbo_plus: opp8 {
};
};
};
+
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
+ <5 296>, /* Soundwire master_irq */
+ <12 422>, /* DWC3 ss_phy_irq */
+ <24 79>, /* Soundwire wake_irq */
+ <86 183>, /* MPM wake, SPMI */
+ <90 260>; /* QUSB2_PHY DP+DM */
+ };
};
reserved_memory: reserved-memory {
@@ -429,6 +448,7 @@ tlmm: pinctrl@500000 {
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 127>;
+ wakeup-parent = <&mpm>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -778,7 +798,7 @@ spmi_bus: spmi@1c40000 {
"obsrvr",
"intr",
"cnfg";
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
qcom,ee = <0>;
qcom,channel = <0>;
@@ -793,8 +813,8 @@ tsens0: thermal-sensor@4411000 {
reg = <0x0 0x04411000 0x0 0x1ff>,
<0x0 0x04410000 0x0 0x8>;
#qcom,sensors = <10>;
- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
@@ -813,8 +833,15 @@ bimc: interconnect@4480000 {
};
rpm_msg_ram: sram@45f0000 {
- compatible = "qcom,rpm-msg-ram";
+ compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x045f0000 0x7000>;
+
+ apss_mpm: sram@1b8 {
+ reg = <0x1b8 0x48>;
+ };
};
sram@4690000 {
@@ -1293,9 +1320,10 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
usb: usb@4ef8800 {
compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
reg = <0x0 0x04ef8800 0x0 0x400>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq";
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
--
2.40.1
On Fri, 15 Dec 2023 01:01:07 +0100, Konrad Dybcio wrote:
> This series hooks up MPM (which can finally be done after winning the
> lengthy bindings fight) on 6375, 8996 and 2290 as a good start.
>
> The hardware in question is present on all RPM SMD SoCs (so, roughly
> msm8974 and up), which means many more platforms are there to come.
>
> MPM is one of the key pieces for allowing full system power collapse
> (and perhaps as importantly, resume) and serves roughly the same role
> as PDC on RPMh SoCs for this purpose.
>
> [...]
Applied, thanks!
[1/3] arm64: dts: qcom: sm6375: Hook up MPM
commit: d3246a0cf43fd24a1986163284edd2389143809d
[2/3] arm64: dts: qcom: msm8996: Hook up MPM
commit: 09896da07315cce07b019ab00750c8a57e1b53a3
[3/3] arm64: dts: qcom: qcm2290: Hook up MPM
commit: e3f6a699404154e7e103f8055f21c3556721603f
Best regards,
--
Bjorn Andersson <[email protected]>