From: Moudy Ho <[email protected]>
Changes since v8:
- Rebase on linux-next.
- Dependent dtsi files:
Message ID = [email protected]
- Dependent bindings:
Message ID = [email protected]
Changes since v7:
- Rebase on linux-next.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=797543
- Dependent bindings:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=797555
- Patch [9/12] has made corresponding adjustments in response to the changes in
the compatible name of the PAD component in DTSI and binding.
- Adding WROT compatible name in the MDP driver's of_match_table in [9/12] to
avoid deactivating 'pm_runtime_*' functions.
Changes since v6:
- Rebase on v6.6-rc5.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=792079
- Dependent bindings:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=792477
- Move the patch that fixes compile warnings from this series and
create a separate standalone patch.
Changes since v5:
- Rebase on v6.6-rc2.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=786511
- Dependent bindings:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=786520
- Integrate MMSY/MUTEX structure in "mdp_probe".
- Fix the build warnings that were detected by the linux-media
build scripts tool.
Changes since v4:
- Rebase on v6.6-rc1
- Remove any unnecessary DTS settings.
- Adjust the usage of MOD and clock in blending components.
Changes since v3:
- Depend on :
[1] https://patchwork.kernel.org/project/linux-media/list/?series=719841
- Suggested by Krzysztof, integrating all newly added bindings for
the mt8195 MDP3 into the file "mediatek,mt8195-mdp3.yaml".
- Revise MDP3 nodes with generic names.
Changes since v2:
- Depend on :
[1] MMSYS/MUTEX: https://patchwork.kernel.org/project/linux-mediatek/list/?series=711592
[2] MDP3: https://patchwork.kernel.org/project/linux-mediatek/list/?series=711618
- Suggested by Rob to revise MDP3 bindings to pass dtbs check
- Add parallel paths feature.
- Add blended components settings.
Changes since v1:
- Depend on :
[1] MDP3 : https://patchwork.kernel.org/project/linux-mediatek/list/?series=698872
[2] MMSYS/MUTEX: https://patchwork.kernel.org/project/linux-mediatek/list/?series=684959
- Fix compilation failure due to use of undeclared identifier in file "mtk-mdp3-cmdq.c"
Hello,
This patch is used to add support for MDP3 on the MT8195 platform that
contains more picture quality components, and can arrange more pipelines
through two sets of MMSYS and MUTEX respectively.
Moudy Ho (12):
media: platform: mtk-mdp3: add support second sets of MMSYS
media: platform: mtk-mdp3: add support second sets of MUTEX
media: platform: mtk-mdp3: introduce more pipelines from MT8195
media: platform: mtk-mdp3: introduce more MDP3 components
media: platform: mtk-mdp3: add checks for dummy components
media: platform: mtk-mdp3: avoid multiple driver registrations
media: platform: mtk-mdp3: extend GCE event waiting in RDMA and WROT
media: platform: mtk-mdp3: add support for blending multiple
components
media: platform: mtk-mdp3: add mt8195 platform configuration
media: platform: mtk-mdp3: add mt8195 shared memory configurations
media: platform: mtk-mdp3: add mt8195 MDP3 component settings
media: platform: mtk-mdp3: add support for parallel pipe to improve
FPS
.../platform/mediatek/mdp3/mdp_cfg_data.c | 729 +++++++++++++-
.../platform/mediatek/mdp3/mdp_reg_aal.h | 25 +
.../platform/mediatek/mdp3/mdp_reg_color.h | 31 +
.../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 +
.../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 +
.../platform/mediatek/mdp3/mdp_reg_merge.h | 25 +
.../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 +
.../platform/mediatek/mdp3/mdp_reg_pad.h | 21 +
.../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 +
.../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 +
.../platform/mediatek/mdp3/mdp_reg_tdshp.h | 34 +
.../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 +
.../platform/mediatek/mdp3/mdp_sm_mt8195.h | 283 ++++++
.../platform/mediatek/mdp3/mtk-img-ipi.h | 4 +
.../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 2 +
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 440 +++++++--
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.h | 1 +
.../platform/mediatek/mdp3/mtk-mdp3-comp.c | 895 +++++++++++++++++-
.../platform/mediatek/mdp3/mtk-mdp3-comp.h | 93 +-
.../platform/mediatek/mdp3/mtk-mdp3-core.c | 142 ++-
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 50 +-
.../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 15 +
.../platform/mediatek/mdp3/mtk-mdp3-regs.c | 18 +
.../platform/mediatek/mdp3/mtk-mdp3-regs.h | 1 +
.../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 3 +-
25 files changed, 2747 insertions(+), 178 deletions(-)
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_sm_mt8195.h
--
2.18.0
Increasing the number of sets built by MMSYS and MUTEX in MT8195
will enable the creation of more pipelines in MDP3.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 80 ++++++++++++-------
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 7 ++
2 files changed, 60 insertions(+), 27 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index 67c8fcc3eda9..31930ddbc828 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -50,6 +50,43 @@ static struct mtk_mutex *__get_mutex(const struct mdp_dev *mdp_dev,
return mdp_dev->mm_subsys[p->sub_id].mdp_mutex[p->mutex_id];
}
+static enum mdp_pipe_id __get_pipe(const struct mdp_dev *mdp_dev,
+ enum mtk_mdp_comp_id id)
+{
+ enum mdp_pipe_id pipe_id;
+
+ switch (id) {
+ case MDP_COMP_RDMA0:
+ pipe_id = MDP_PIPE_RDMA0;
+ break;
+ case MDP_COMP_ISP_IMGI:
+ pipe_id = MDP_PIPE_IMGI;
+ break;
+ case MDP_COMP_WPEI:
+ pipe_id = MDP_PIPE_WPEI;
+ break;
+ case MDP_COMP_WPEI2:
+ pipe_id = MDP_PIPE_WPEI2;
+ break;
+ case MDP_COMP_RDMA1:
+ pipe_id = MDP_PIPE_RDMA1;
+ break;
+ case MDP_COMP_RDMA2:
+ pipe_id = MDP_PIPE_RDMA2;
+ break;
+ case MDP_COMP_RDMA3:
+ pipe_id = MDP_PIPE_RDMA3;
+ break;
+ default:
+ /* Avoid exceptions when operating MUTEX */
+ pipe_id = MDP_PIPE_RDMA0;
+ dev_err(&mdp_dev->pdev->dev, "Unknown pipeline id %d", id);
+ break;
+ }
+
+ return pipe_id;
+}
+
static int mdp_path_subfrm_require(const struct mdp_path *path,
struct mdp_cmdq_cmd *cmd,
struct mdp_pipe_info *p, u32 count)
@@ -57,7 +94,6 @@ static int mdp_path_subfrm_require(const struct mdp_path *path,
const int p_id = path->mdp_dev->mdp_data->mdp_plat_id;
const struct mdp_comp_ctx *ctx;
const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
- struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex *mutex;
int id, index;
u32 num_comp = 0;
@@ -66,23 +102,7 @@ static int mdp_path_subfrm_require(const struct mdp_path *path,
num_comp = CFG_GET(MT8183, path->config, num_components);
/* Decide which mutex to use based on the current pipeline */
- switch (path->comps[0].comp->public_id) {
- case MDP_COMP_RDMA0:
- index = MDP_PIPE_RDMA0;
- break;
- case MDP_COMP_ISP_IMGI:
- index = MDP_PIPE_IMGI;
- break;
- case MDP_COMP_WPEI:
- index = MDP_PIPE_WPEI;
- break;
- case MDP_COMP_WPEI2:
- index = MDP_PIPE_WPEI2;
- break;
- default:
- dev_err(dev, "Unknown pipeline and no mutex is assigned");
- return -EINVAL;
- }
+ index = __get_pipe(path->mdp_dev, path->comps[0].comp->public_id);
memcpy(p, &data->pipe_info[index], sizeof(struct mdp_pipe_info));
mutex = __get_mutex(path->mdp_dev, p);
@@ -336,11 +356,13 @@ static void mdp_auto_release_work(struct work_struct *work)
struct mdp_cmdq_cmd *cmd;
struct mdp_dev *mdp;
struct mtk_mutex *mutex;
+ enum mdp_pipe_id pipe_id;
cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work);
mdp = cmd->mdp;
- mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]);
+ pipe_id = __get_pipe(mdp, cmd->comps[0].public_id);
+ mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[pipe_id]);
mtk_mutex_unprepare(mutex);
mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps,
cmd->num_comps);
@@ -361,6 +383,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg)
struct cmdq_cb_data *data;
struct mdp_dev *mdp;
struct device *dev;
+ enum mdp_pipe_id pipe_id;
if (!mssg) {
pr_info("%s:no callback data\n", __func__);
@@ -388,7 +411,8 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg)
struct mtk_mutex *mutex;
dev_err(dev, "%s:queue_work fail!\n", __func__);
- mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]);
+ pipe_id = __get_pipe(mdp, cmd->comps[0].public_id);
+ mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[pipe_id]);
mtk_mutex_unprepare(mutex);
mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps,
cmd->num_comps);
@@ -412,6 +436,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
struct device *dev = &mdp->pdev->dev;
const int p_id = mdp->mdp_data->mdp_plat_id;
struct mtk_mutex *mutex = NULL;
+ enum mdp_pipe_id pipe_id;
int i, ret;
u32 num_comp = 0;
@@ -449,13 +474,6 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_free_comps;
}
- mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]);
- ret = mtk_mutex_prepare(mutex);
- if (ret) {
- dev_err(dev, "Fail to enable mutex clk\n");
- goto err_free_path;
- }
-
path->mdp_dev = mdp;
path->config = param->config;
path->param = param->param;
@@ -475,6 +493,14 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_free_path;
}
+ pipe_id = __get_pipe(mdp, path->comps[0].comp->public_id);
+ mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[pipe_id]);
+ ret = mtk_mutex_prepare(mutex);
+ if (ret) {
+ dev_err(dev, "Fail to enable mutex clk\n");
+ goto err_free_path;
+ }
+
ret = mdp_path_config(mdp, cmd, path);
if (ret) {
dev_err(dev, "mdp_path_config error\n");
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
index fde2c0b95def..ece6509666fd 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
@@ -59,6 +59,13 @@ enum mdp_pipe_id {
MDP_PIPE_WPEI2,
MDP_PIPE_IMGI,
MDP_PIPE_RDMA0,
+ MDP_PIPE_RDMA1,
+ MDP_PIPE_RDMA2,
+ MDP_PIPE_RDMA3,
+ MDP_PIPE_SPLIT,
+ MDP_PIPE_SPLIT2,
+ MDP_PIPE_VPP0_SOUT,
+ MDP_PIPE_VPP1_SOUT,
MDP_PIPE_MAX
};
--
2.18.0
The MT8195 chipset features two MMSYS subsets: VPPSYS0 and VPPSYS1.
These subsets coordinate and control the clock, power, and
register settings required for the components of MDP3.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 44 ++++++-------
.../platform/mediatek/mdp3/mtk-mdp3-comp.h | 1 +
.../platform/mediatek/mdp3/mtk-mdp3-core.c | 61 ++++++++++++++++---
.../platform/mediatek/mdp3/mtk-mdp3-core.h | 18 +++++-
4 files changed, 92 insertions(+), 32 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index 502eeae0bfdc..fcc582292b77 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -73,75 +73,75 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = {
static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
[MDP_COMP_WPEI] = {
- {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI},
+ {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_WPEO] = {
- {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO},
+ {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_WPEI2] = {
- {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2},
+ {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_WPEO2] = {
- {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2},
+ {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_ISP_IMGI] = {
- {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI},
+ {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, MDP_MM_SUBSYS_0},
{0, 0, 4}
},
[MDP_COMP_ISP_IMGO] = {
- {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO},
+ {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO, MDP_MM_SUBSYS_0},
{0, 0, 4}
},
[MDP_COMP_ISP_IMG2O] = {
- {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O},
+ {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_CAMIN] = {
- {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN},
+ {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0},
{2, 2, 1}
},
[MDP_COMP_CAMIN2] = {
- {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2},
+ {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0},
{2, 4, 1}
},
[MDP_COMP_RDMA0] = {
- {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0},
+ {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0},
{2, 0, 0}
},
[MDP_COMP_CCORR0] = {
- {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0},
+ {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0, MDP_MM_SUBSYS_0},
{1, 0, 0}
},
[MDP_COMP_RSZ0] = {
- {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0},
+ {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0},
{1, 0, 0}
},
[MDP_COMP_RSZ1] = {
- {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1},
+ {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1, MDP_MM_SUBSYS_0},
{1, 0, 0}
},
[MDP_COMP_TDSHP0] = {
- {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0},
+ {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_PATH0_SOUT] = {
- {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT},
+ {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_PATH1_SOUT] = {
- {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT},
+ {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT, MDP_MM_SUBSYS_0},
{0, 0, 0}
},
[MDP_COMP_WROT0] = {
- {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0},
+ {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0, MDP_MM_SUBSYS_0},
{1, 0, 0}
},
[MDP_COMP_WDMA] = {
- {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA},
+ {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA, MDP_MM_SUBSYS_0},
{1, 0, 0}
},
};
@@ -402,10 +402,10 @@ static const struct mdp_limit mt8183_mdp_def_limit = {
};
static const struct mdp_pipe_info mt8183_pipe_info[] = {
- [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0},
- [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 1},
- [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 2},
- [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 3}
+ [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0},
+ [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1},
+ [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2},
+ [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3}
};
const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
index 20d2bcb77ef9..e89c51e1edb7 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
@@ -138,6 +138,7 @@ struct mdp_comp_match {
enum mdp_comp_type type;
u32 alias_id;
s32 inner_id;
+ s32 subsys_id;
};
/* Used to describe the item order in MDP property */
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
index 94f4ed78523b..8cd0f11fc290 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
@@ -26,9 +26,10 @@ static const struct of_device_id mdp_of_ids[] = {
MODULE_DEVICE_TABLE(of, mdp_of_ids);
static struct platform_device *__get_pdev_by_id(struct platform_device *pdev,
+ struct platform_device *from,
enum mdp_infra_id id)
{
- struct device_node *node;
+ struct device_node *node, *f = NULL;
struct platform_device *mdp_pdev = NULL;
const struct mtk_mdp_driver_data *mdp_data;
const char *compat;
@@ -46,9 +47,14 @@ static struct platform_device *__get_pdev_by_id(struct platform_device *pdev,
dev_err(&pdev->dev, "have no driver data to find node\n");
return NULL;
}
+
compat = mdp_data->mdp_probe_infra[id].compatible;
+ if (strlen(compat) == 0)
+ return NULL;
- node = of_find_compatible_node(NULL, NULL, compat);
+ if (from)
+ f = from->dev.of_node;
+ node = of_find_compatible_node(f, NULL, compat);
if (WARN_ON(!node)) {
dev_err(&pdev->dev, "find node from id %d failed\n", id);
return NULL;
@@ -148,6 +154,46 @@ void mdp_video_device_release(struct video_device *vdev)
kfree(mdp);
}
+static int mdp_mm_subsys_deploy(struct mdp_dev *mdp, enum mdp_infra_id id)
+{
+ struct platform_device *mm_pdev = NULL;
+ struct device **dev;
+ int i;
+
+ if (!mdp)
+ return -EINVAL;
+
+ for (i = 0; i < MDP_MM_SUBSYS_MAX; i++) {
+ const char *compat;
+ enum mdp_infra_id sub_id = id + i;
+
+ switch (id) {
+ case MDP_INFRA_MMSYS:
+ dev = &mdp->mm_subsys[i].mmsys;
+ break;
+ default:
+ dev_err(&mdp->pdev->dev, "Unknown infra id %d", id);
+ return -EINVAL;
+ }
+
+ /*
+ * Not every chip has multiple multimedia subsystems, so
+ * the config may be null.
+ */
+ compat = mdp->mdp_data->mdp_probe_infra[sub_id].compatible;
+ if (strlen(compat) == 0)
+ continue;
+
+ mm_pdev = __get_pdev_by_id(mdp->pdev, mm_pdev, sub_id);
+ if (WARN_ON(!mm_pdev))
+ return -ENODEV;
+
+ *dev = &mm_pdev->dev;
+ }
+
+ return 0;
+}
+
static int mdp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -164,14 +210,11 @@ static int mdp_probe(struct platform_device *pdev)
mdp->pdev = pdev;
mdp->mdp_data = of_device_get_match_data(&pdev->dev);
- mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_MMSYS);
- if (!mm_pdev) {
- ret = -ENODEV;
+ ret = mdp_mm_subsys_deploy(mdp, MDP_INFRA_MMSYS);
+ if (ret)
goto err_destroy_device;
- }
- mdp->mdp_mmsys = &mm_pdev->dev;
- mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_MUTEX);
+ mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_MUTEX);
if (WARN_ON(!mm_pdev)) {
ret = -ENODEV;
goto err_destroy_device;
@@ -210,7 +253,7 @@ static int mdp_probe(struct platform_device *pdev)
mdp->scp = scp_get(pdev);
if (!mdp->scp) {
- mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_SCP);
+ mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_SCP);
if (WARN_ON(!mm_pdev)) {
dev_err(&pdev->dev, "Could not get scp device\n");
ret = -ENODEV;
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
index 7e21d226ceb8..7a7cdd0ce968 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
@@ -19,12 +19,23 @@
#define MDP_PHANDLE_NAME "mediatek,mdp3"
enum mdp_infra_id {
+ /*
+ * Due to the sequential nature of function "mdp_mm_subsys_deploy",
+ * adding new enum. necessitates careful consideration.
+ */
MDP_INFRA_MMSYS,
+ MDP_INFRA_MMSYS2,
MDP_INFRA_MUTEX,
MDP_INFRA_SCP,
MDP_INFRA_MAX
};
+enum mdp_mm_subsys_id {
+ MDP_MM_SUBSYS_0,
+ MDP_MM_SUBSYS_1,
+ MDP_MM_SUBSYS_MAX,
+};
+
enum mdp_buffer_usage {
MDP_BUFFER_USAGE_HW_READ,
MDP_BUFFER_USAGE_MDP,
@@ -65,9 +76,13 @@ struct mtk_mdp_driver_data {
unsigned int pipe_info_len;
};
+struct mdp_mm_subsys {
+ struct device *mmsys;
+};
+
struct mdp_dev {
struct platform_device *pdev;
- struct device *mdp_mmsys;
+ struct mdp_mm_subsys mm_subsys[MDP_MM_SUBSYS_MAX];
struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX];
struct mdp_comp *comp[MDP_MAX_COMP_COUNT];
const struct mtk_mdp_driver_data *mdp_data;
@@ -96,6 +111,7 @@ struct mdp_dev {
struct mdp_pipe_info {
enum mdp_pipe_id pipe_id;
+ enum mdp_mm_subsys_id sub_id;
u32 mutex_id;
};
--
2.18.0
Add configuration of more components in MT8195 MDP3.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../platform/mediatek/mdp3/mdp_reg_aal.h | 25 ++++++
.../platform/mediatek/mdp3/mdp_reg_color.h | 31 +++++++
.../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 +++++
.../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 +++++++
.../platform/mediatek/mdp3/mdp_reg_merge.h | 25 ++++++
.../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 ++++++
.../platform/mediatek/mdp3/mdp_reg_pad.h | 21 +++++
.../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 ++++++
.../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 +
.../platform/mediatek/mdp3/mdp_reg_tdshp.h | 34 ++++++++
.../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 ++
.../platform/mediatek/mdp3/mtk-mdp3-comp.h | 85 +++++++++++++++----
12 files changed, 318 insertions(+), 16 deletions(-)
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h
create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h
new file mode 100644
index 000000000000..4b9513e54543
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_AAL_H__
+#define __MDP_REG_AAL_H__
+
+#define MDP_AAL_EN (0x000)
+#define MDP_AAL_CFG (0x020)
+#define MDP_AAL_SIZE (0x030)
+#define MDP_AAL_OUTPUT_SIZE (0x034)
+#define MDP_AAL_OUTPUT_OFFSET (0x038)
+#define MDP_AAL_CFG_MAIN (0x200)
+
+/* MASK */
+#define MDP_AAL_EN_MASK (0x01)
+#define MDP_AAL_CFG_MASK (0x70FF00B3)
+#define MDP_AAL_SIZE_MASK (0x1FFF1FFF)
+#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF)
+#define MDP_AAL_CFG_MAIN_MASK (0x0FE)
+
+#endif // __MDP_REG_AAL_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h
new file mode 100644
index 000000000000..f72503975b24
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_COLOR_H__
+#define __MDP_REG_COLOR_H__
+
+#define MDP_COLOR_WIN_X_MAIN (0x40C)
+#define MDP_COLOR_WIN_Y_MAIN (0x410)
+#define MDP_COLOR_START (0xC00)
+#define MDP_COLOR_INTEN (0xC04)
+#define MDP_COLOR_OUT_SEL (0xC0C)
+#define MDP_COLOR_INTERNAL_IP_WIDTH (0xC50)
+#define MDP_COLOR_INTERNAL_IP_HEIGHT (0xC54)
+#define MDP_COLOR_CM1_EN (0xC60)
+#define MDP_COLOR_CM2_EN (0xCA0)
+
+/* MASK */
+#define MDP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF)
+#define MDP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF)
+#define MDP_COLOR_START_MASK (0x0FF013F)
+#define MDP_COLOR_INTEN_MASK (0x07)
+#define MDP_COLOR_OUT_SEL_MASK (0x0777)
+#define MDP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF)
+#define MDP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF)
+#define MDP_COLOR_CM1_EN_MASK (0x03)
+#define MDP_COLOR_CM2_EN_MASK (0x017)
+
+#endif // __MDP_REG_COLOR_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h
new file mode 100644
index 000000000000..d90bcad33a59
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_FG_H__
+#define __MDP_REG_FG_H__
+
+#define MDP_FG_TRIGGER (0x0)
+#define MDP_FG_FG_CTRL_0 (0x20)
+#define MDP_FG_FG_CK_EN (0x24)
+#define MDP_FG_TILE_INFO_0 (0x418)
+#define MDP_FG_TILE_INFO_1 (0x41c)
+
+/* MASK */
+#define MDP_FG_TRIGGER_MASK (0x00000007)
+#define MDP_FG_FG_CTRL_0_MASK (0x00000033)
+#define MDP_FG_FG_CK_EN_MASK (0x0000000F)
+#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF)
+#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF)
+
+#endif //__MDP_REG_FG_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h
new file mode 100644
index 000000000000..c19fbba39fc0
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_HDR_H__
+#define __MDP_REG_HDR_H__
+
+#define MDP_HDR_TOP (0x000)
+#define MDP_HDR_RELAY (0x004)
+#define MDP_HDR_SIZE_0 (0x014)
+#define MDP_HDR_SIZE_1 (0x018)
+#define MDP_HDR_SIZE_2 (0x01C)
+#define MDP_HDR_HIST_CTRL_0 (0x020)
+#define MDP_HDR_HIST_CTRL_1 (0x024)
+#define MDP_HDR_HIST_ADDR (0x0DC)
+#define MDP_HDR_TILE_POS (0x118)
+
+/* MASK */
+#define MDP_HDR_RELAY_MASK (0x01)
+#define MDP_HDR_TOP_MASK (0xFF0FEB6D)
+#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF)
+#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF)
+#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F)
+#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF)
+
+#endif // __MDP_REG_HDR_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h
new file mode 100644
index 000000000000..46be27e2a656
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_MERGE_H__
+#define __MDP_REG_MERGE_H__
+
+#define MDP_MERGE_ENABLE (0x000)
+#define MDP_MERGE_CFG_0 (0x010)
+#define MDP_MERGE_CFG_4 (0x020)
+#define MDP_MERGE_CFG_12 (0x040)
+#define MDP_MERGE_CFG_24 (0x070)
+#define MDP_MERGE_CFG_25 (0x074)
+
+/* MASK */
+#define MDP_MERGE_ENABLE_MASK (0xFFFFFFFF)
+#define MDP_MERGE_CFG_0_MASK (0xFFFFFFFF)
+#define MDP_MERGE_CFG_4_MASK (0xFFFFFFFF)
+#define MDP_MERGE_CFG_12_MASK (0xFFFFFFFF)
+#define MDP_MERGE_CFG_24_MASK (0xFFFFFFFF)
+#define MDP_MERGE_CFG_25_MASK (0xFFFFFFFF)
+
+#endif //__MDP_REG_MERGE_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h
new file mode 100644
index 000000000000..21d2d0323293
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_OVL_H__
+#define __MDP_REG_OVL_H__
+
+#define MDP_OVL_EN (0x00c)
+#define MDP_OVL_ROI_SIZE (0x020)
+#define MDP_OVL_DP_CON (0x024)
+#define MDP_OVL_SRC_CON (0x02c)
+#define MDP_OVL_L0_CON (0x030)
+#define MDP_OVL_L0_SRC_SIZE (0x038)
+
+/* MASK */
+#define MDP_OVL_DP_CON_MASK (0x0FFFFFFF)
+#define MDP_OVL_EN_MASK (0xB07D07B1)
+#define MDP_OVL_L0_CON_MASK (0xFFFFFFFF)
+#define MDP_OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF)
+#define MDP_OVL_ROI_SIZE_MASK (0x1FFF1FFF)
+#define MDP_OVL_SRC_CON_MASK (0x0000031F)
+
+#endif //__MDP_REG_OVL_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h
new file mode 100644
index 000000000000..0e89f1db19ed
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_PAD_H__
+#define __MDP_REG_PAD_H__
+
+#define MDP_PAD_CON (0x000)
+#define MDP_PAD_PIC_SIZE (0x004)
+#define MDP_PAD_W_SIZE (0x008)
+#define MDP_PAD_H_SIZE (0x00c)
+
+/* MASK */
+#define MDP_PAD_CON_MASK (0x00000007)
+#define MDP_PAD_PIC_SIZE_MASK (0xFFFFFFFF)
+#define MDP_PAD_W_SIZE_MASK (0x1FFF1FFF)
+#define MDP_PAD_H_SIZE_MASK (0x1FFF1FFF)
+
+#endif // __MDP_REG_PAD_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
index be4065e252d3..0affb2a3b958 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
@@ -26,6 +26,18 @@
#define MDP_RDMA_SRC_OFFSET_2 0x128
#define MDP_RDMA_SRC_OFFSET_0_P 0x148
#define MDP_RDMA_TRANSFORM_0 0x200
+#define MDP_RDMA_DMABUF_CON_0 0x240
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248
+#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
#define MDP_RDMA_RESV_DUMMY_0 0x2a0
#define MDP_RDMA_MON_STA_1 0x408
#define MDP_RDMA_SRC_BASE_0 0xf00
@@ -54,6 +66,18 @@
#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff
#define MDP_RDMA_TRANSFORM_0_MASK 0xff110777
+#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff
#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff
#define MDP_RDMA_MON_STA_1_MASK 0xffffffff
#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
index 484f6d60641f..187531db8e3b 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
@@ -20,6 +20,7 @@
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034
+#define RSZ_ETC_CONTROL 0x22c
/* MASK */
#define PRZ_ENABLE_MASK 0x00010001
@@ -35,5 +36,6 @@
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
+#define RSZ_ETC_CONTROL_MASK 0xff770000
#endif // __MDP_REG_RSZ_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h
new file mode 100644
index 000000000000..83b5f9b432d8
--- /dev/null
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Ping-Hsun Wu <[email protected]>
+ */
+
+#ifndef __MDP_REG_TDSHP_H__
+#define __MDP_REG_TDSHP_H__
+
+#define MDP_HIST_CFG_00 (0x064)
+#define MDP_HIST_CFG_01 (0x068)
+#define MDP_TDSHP_CTRL (0x100)
+#define MDP_TDSHP_CFG (0x110)
+#define MDP_TDSHP_INPUT_SIZE (0x120)
+#define MDP_TDSHP_OUTPUT_OFFSET (0x124)
+#define MDP_TDSHP_OUTPUT_SIZE (0x128)
+#define MDP_LUMA_HIST_INIT (0x200)
+#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)
+#define MDP_CONTOUR_HIST_INIT (0x398)
+
+/* MASK */
+#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF)
+#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF)
+#define MDP_LUMA_HIST_MASK (0xFFFFFFFF)
+#define MDP_TDSHP_CTRL_MASK (0x07)
+#define MDP_TDSHP_CFG_MASK (0x03F7)
+#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF)
+#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_LUMA_HIST_INIT_MASK (0xFFFFFFFF)
+#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF)
+#define MDP_CONTOUR_HIST_INIT_MASK (0xFFFFFFFF)
+
+#endif // __MDP_REG_TDSHP_H__
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
index 6d3ff0e2b672..b6f016d2c29d 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
+++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
@@ -17,14 +17,18 @@
#define VIDO_STRIDE 0x030
#define VIDO_OFST_ADDR_C 0x038
#define VIDO_STRIDE_C 0x03c
+#define VIDO_CTRL_2 0x048
#define VIDO_DITHER 0x054
#define VIDO_STRIDE_V 0x06c
#define VIDO_OFST_ADDR_V 0x068
#define VIDO_RSV_1 0x070
+#define VIDO_DMA_PREULTRA 0x074
#define VIDO_IN_SIZE 0x078
#define VIDO_ROT_EN 0x07c
#define VIDO_FIFO_TEST 0x080
#define VIDO_MAT_CTRL 0x084
+#define VIDO_SCAN_10BIT 0x0dc
+#define VIDO_PENDING_ZERO 0x0e0
#define VIDO_BASE_ADDR 0xf00
#define VIDO_BASE_ADDR_C 0xf04
#define VIDO_BASE_ADDR_V 0xf08
@@ -40,14 +44,18 @@
#define VIDO_STRIDE_MASK 0x0000ffff
#define VIDO_OFST_ADDR_C_MASK 0x0fffffff
#define VIDO_STRIDE_C_MASK 0x0000ffff
+#define VIDO_CTRL_2_MASK 0x0000000f
#define VIDO_DITHER_MASK 0xff000001
#define VIDO_STRIDE_V_MASK 0x0000ffff
#define VIDO_OFST_ADDR_V_MASK 0x0fffffff
#define VIDO_RSV_1_MASK 0xffffffff
+#define VIDO_DMA_PREULTRA_MASK 0x00ffffff
#define VIDO_IN_SIZE_MASK 0x1fff1fff
#define VIDO_ROT_EN_MASK 0x00000001
#define VIDO_FIFO_TEST_MASK 0x00000fff
#define VIDO_MAT_CTRL_MASK 0x000000f3
+#define VIDO_SCAN_10BIT_MASK 0x0000000f
+#define VIDO_PENDING_ZERO_MASK 0x07ffffff
#define VIDO_BASE_ADDR_MASK 0xffffffff
#define VIDO_BASE_ADDR_C_MASK 0xffffffff
#define VIDO_BASE_ADDR_V_MASK 0xffffffff
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
index e89c51e1edb7..e6cbc6ab6bae 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
@@ -84,22 +84,66 @@ enum mtk_mdp_comp_id {
MDP_COMP_CAMIN, /* 9 */
MDP_COMP_CAMIN2, /* 10 */
MDP_COMP_RDMA0, /* 11 */
- MDP_COMP_AAL0, /* 12 */
- MDP_COMP_CCORR0, /* 13 */
- MDP_COMP_RSZ0, /* 14 */
- MDP_COMP_RSZ1, /* 15 */
- MDP_COMP_TDSHP0, /* 16 */
- MDP_COMP_COLOR0, /* 17 */
- MDP_COMP_PATH0_SOUT, /* 18 */
- MDP_COMP_PATH1_SOUT, /* 19 */
- MDP_COMP_WROT0, /* 20 */
- MDP_COMP_WDMA, /* 21 */
-
- /* Dummy Engine */
- MDP_COMP_RDMA1, /* 22 */
- MDP_COMP_RSZ2, /* 23 */
- MDP_COMP_TDSHP1, /* 24 */
- MDP_COMP_WROT1, /* 25 */
+ MDP_COMP_RDMA1, /* 12 */
+ MDP_COMP_RDMA2, /* 13 */
+ MDP_COMP_RDMA3, /* 14 */
+ MDP_COMP_AAL0, /* 15 */
+ MDP_COMP_AAL1, /* 16 */
+ MDP_COMP_AAL2, /* 17 */
+ MDP_COMP_AAL3, /* 18 */
+ MDP_COMP_CCORR0, /* 19 */
+ MDP_COMP_RSZ0, /* 20 */
+ MDP_COMP_RSZ1, /* 21 */
+ MDP_COMP_RSZ2, /* 22 */
+ MDP_COMP_RSZ3, /* 23 */
+ MDP_COMP_TDSHP0, /* 24 */
+ MDP_COMP_TDSHP1, /* 25 */
+ MDP_COMP_TDSHP2, /* 26 */
+ MDP_COMP_TDSHP3, /* 27 */
+ MDP_COMP_COLOR0, /* 28 */
+ MDP_COMP_COLOR1, /* 29 */
+ MDP_COMP_COLOR2, /* 30 */
+ MDP_COMP_COLOR3, /* 31 */
+ MDP_COMP_PATH0_SOUT, /* 32 */
+ MDP_COMP_PATH1_SOUT, /* 33 */
+ MDP_COMP_WROT0, /* 34 */
+ MDP_COMP_WROT1, /* 35 */
+ MDP_COMP_WROT2, /* 36 */
+ MDP_COMP_WROT3, /* 37 */
+ MDP_COMP_WDMA, /* 38 */
+ MDP_COMP_SPLIT, /* 39 */
+ MDP_COMP_SPLIT2, /* 40 */
+ MDP_COMP_STITCH, /* 41 */
+ MDP_COMP_FG0, /* 42 */
+ MDP_COMP_FG1, /* 43 */
+ MDP_COMP_FG2, /* 44 */
+ MDP_COMP_FG3, /* 45 */
+ MDP_COMP_TO_SVPP2MOUT, /* 46 */
+ MDP_COMP_TO_SVPP3MOUT, /* 47 */
+ MDP_COMP_TO_WARP0MOUT, /* 48 */
+ MDP_COMP_TO_WARP1MOUT, /* 49 */
+ MDP_COMP_VPP0_SOUT, /* 50 */
+ MDP_COMP_VPP1_SOUT, /* 51 */
+ MDP_COMP_PQ0_SOUT, /* 52 */
+ MDP_COMP_PQ1_SOUT, /* 53 */
+ MDP_COMP_HDR0, /* 54 */
+ MDP_COMP_HDR1, /* 55 */
+ MDP_COMP_HDR2, /* 56 */
+ MDP_COMP_HDR3, /* 57 */
+ MDP_COMP_OVL0, /* 58 */
+ MDP_COMP_OVL1, /* 59 */
+ MDP_COMP_PAD0, /* 60 */
+ MDP_COMP_PAD1, /* 61 */
+ MDP_COMP_PAD2, /* 62 */
+ MDP_COMP_PAD3, /* 63 */
+ MDP_COMP_TCC0, /* 64 */
+ MDP_COMP_TCC1, /* 65 */
+ MDP_COMP_MERGE2, /* 66 */
+ MDP_COMP_MERGE3, /* 67 */
+ MDP_COMP_VDO0DL0, /* 68 */
+ MDP_COMP_VDO1DL0, /* 69 */
+ MDP_COMP_VDO0DL1, /* 70 */
+ MDP_COMP_VDO1DL1, /* 71 */
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
@@ -117,12 +161,21 @@ enum mdp_comp_type {
MDP_COMP_TYPE_COLOR,
MDP_COMP_TYPE_DRE,
MDP_COMP_TYPE_CCORR,
+ MDP_COMP_TYPE_AAL,
+ MDP_COMP_TYPE_TCC,
MDP_COMP_TYPE_HDR,
+ MDP_COMP_TYPE_SPLIT,
+ MDP_COMP_TYPE_STITCH,
+ MDP_COMP_TYPE_FG,
+ MDP_COMP_TYPE_OVL,
+ MDP_COMP_TYPE_PAD,
+ MDP_COMP_TYPE_MERGE,
MDP_COMP_TYPE_IMGI,
MDP_COMP_TYPE_WPEI,
MDP_COMP_TYPE_EXTO, /* External path */
MDP_COMP_TYPE_DL_PATH, /* Direct-link path */
+ MDP_COMP_TYPE_DUMMY,
MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */
};
--
2.18.0