2023-12-20 16:00:58

by Clément Léger

[permalink] [raw]
Subject: [PATCH v2 0/6] riscv: hwprobe: add Zicond, Zacas and Ztso support

This series add support for a few more extensions that are present in
the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful
for userspace:
- Zicond
- Zacas
- Ztso

Series currently based on riscv/for-next.

---

Changes in V2:
- Removed Zam which is not yet ratified
- Link to v1: https://lore.kernel.org/linux-riscv/[email protected]/

Clément Léger (6):
riscv: add ISA extension parsing for Ztso
riscv: hwprobe: export Ztso ISA extension
dt-bindings: riscv: add Zacas ISA extension description
riscv: add ISA extension parsing for Zacas
riscv: hwprobe: export Zacas ISA extension
riscv: hwprobe: export Zicond extension

Documentation/arch/riscv/hwprobe.rst | 13 +++++++++++++
.../devicetree/bindings/riscv/extensions.yaml | 6 ++++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
arch/riscv/kernel/cpufeature.c | 2 ++
arch/riscv/kernel/sys_riscv.c | 3 +++
6 files changed, 29 insertions(+)

--
2.43.0



2023-12-20 16:02:34

by Clément Léger

[permalink] [raw]
Subject: [PATCH v2 4/6] riscv: add ISA extension parsing for Zacas

Add parsing for Zacas ISA extension which was ratified recently in the
riscv-zacas manual.

Signed-off-by: Clément Léger <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 3b31efe2f716..34f86424d743 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -85,6 +85,7 @@
#define RISCV_ISA_EXT_ZVFHMIN 70
#define RISCV_ISA_EXT_ZFA 71
#define RISCV_ISA_EXT_ZTSO 72
+#define RISCV_ISA_EXT_ZACAS 73

#define RISCV_ISA_EXT_MAX 128
#define RISCV_ISA_EXT_INVALID U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3eb48a0eecb3..9a9d915b5bb2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+ __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
--
2.43.0


2023-12-20 16:03:22

by Clément Léger

[permalink] [raw]
Subject: [PATCH v2 6/6] riscv: hwprobe: export Zicond extension

Export the zicond extension to userspace using hwprobe.

Signed-off-by: Clément Léger <[email protected]>
---
Documentation/arch/riscv/hwprobe.rst | 5 +++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_riscv.c | 1 +
3 files changed, 7 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index bff68004ad43..ee320fe7581b 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -169,6 +169,11 @@ The following keys are defined:
defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
from commit 5059e0ca641c ("update to ratified").

+ * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
+ defined in the RISC-V Integer Conditional (Zicond) operations extension
+ manual starting from commit 95cf1f9 ("Add changes requested by Ved
+ during signoff")
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index ac65bb43c8e7..fd7af0dddb12 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -58,6 +58,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
+#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 6c680c75ac0d..cca9b1e35647 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -176,6 +176,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZIHINTNTL);
EXT_KEY(ZTSO);
EXT_KEY(ZACAS);
+ EXT_KEY(ZICOND);

if (has_vector()) {
EXT_KEY(ZVBB);
--
2.43.0


2024-01-10 11:38:36

by Conor Dooley

[permalink] [raw]
Subject: Re: [PATCH v2 4/6] riscv: add ISA extension parsing for Zacas

On Wed, Dec 20, 2023 at 04:57:20PM +0100, Cl?ment L?ger wrote:
> Add parsing for Zacas ISA extension which was ratified recently in the
> riscv-zacas manual.
>
> Signed-off-by: Cl?ment L?ger <[email protected]>

Reviewed-by: Conor Dooley <[email protected]>

Cheers,
Conor.

> ---
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 3b31efe2f716..34f86424d743 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -85,6 +85,7 @@
> #define RISCV_ISA_EXT_ZVFHMIN 70
> #define RISCV_ISA_EXT_ZFA 71
> #define RISCV_ISA_EXT_ZTSO 72
> +#define RISCV_ISA_EXT_ZACAS 73
>
> #define RISCV_ISA_EXT_MAX 128
> #define RISCV_ISA_EXT_INVALID U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3eb48a0eecb3..9a9d915b5bb2 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
> + __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
> __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
> --
> 2.43.0
>

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Subject: Re: [PATCH v2 0/6] riscv: hwprobe: add Zicond, Zacas and Ztso support

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:

On Wed, 20 Dec 2023 16:57:16 +0100 you wrote:
> This series add support for a few more extensions that are present in
> the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful
> for userspace:
> - Zicond
> - Zacas
> - Ztso
>
> [...]

Here is the summary with links:
- [v2,1/6] riscv: add ISA extension parsing for Ztso
https://git.kernel.org/riscv/c/1ec9f381e848
- [v2,2/6] riscv: hwprobe: export Ztso ISA extension
https://git.kernel.org/riscv/c/5b4d64a819c0
- [v2,3/6] dt-bindings: riscv: add Zacas ISA extension description
https://git.kernel.org/riscv/c/cd7be4d02f41
- [v2,4/6] riscv: add ISA extension parsing for Zacas
https://git.kernel.org/riscv/c/188a2122c827
- [v2,5/6] riscv: hwprobe: export Zacas ISA extension
https://git.kernel.org/riscv/c/154a37061229
- [v2,6/6] riscv: hwprobe: export Zicond extension
https://git.kernel.org/riscv/c/3359866b40a9

You are awesome, thank you!
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