Changes since v4:
- Patch(1/2) expresses JH8100 compatibility to JH7110 in dt-binding,
and adds minItems to constrain reset property.
- Patch(2/2) adds watchdog node in jh8100.dtsi. This patch depends on
patch series [1] and [2].
[1]: Initial device tree support for StarFive JH8100 SoC
https://lore.kernel.org/all/[email protected]/
[2]: Basic clock and reset support for StarFive JH8100 RISC-V SoC
https://lore.kernel.org/all/[email protected]/
Changes since v3:
- Drop items in compatible field.
- Replace items with maxItems in reset field.
- Replace maxItems with items: -description in if else reset field
Changes since v2:
- Express JH8100 compatibility to JH7110 in dt-bindings.
- Rework min/maxItems constraint for JH8100 resets property.
Changes since v1:
- Drop "starfive,jh8100-wdt" compatible field in starfive-wdt.c,
and express them in dt-bindings.
- Use minItems in resets field to cater for single reset signal
in JH8100.
- Reword Watchdog reset to Core reset for JH8100.
StarFive's JH8100 watchdog reuses JH7100 register mapping.
DT-binding of JH7100 watchdog is extended to support JH8100.
Since JH8100 only uses 1 reset signal, update the binding to
support one reset for "starfive,jh8100-wdt" compatible.
Ji Sheng Teoh (2):
dt-bindings: watchdog: starfive,jh7100-wdt: Add compatible for JH8100
riscv: dts: starfive: jh8100: Add watchdog node
.../watchdog/starfive,jh7100-wdt.yaml | 40 ++++++++++++++-----
arch/riscv/boot/dts/starfive/jh8100.dtsi | 9 +++++
2 files changed, 40 insertions(+), 9 deletions(-)
--
2.25.1
StarFive's JH8100 watchdog is based on JH7110, with JH8100 watchdog only
requiring one reset signal.
Signed-off-by: Ji Sheng Teoh <[email protected]>
---
arch/riscv/boot/dts/starfive/jh8100.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
index 9863c61324a0..657d8b79e708 100644
--- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
@@ -360,6 +360,15 @@ uart4: serial@121a0000 {
status = "disabled";
};
+ watchdog@12270000 {
+ compatible = "starfive,jh8100-wdt", "starfive,jh7110-wdt";
+ reg = <0x0 0x12270000 0x0 0x10000>;
+ clocks = <&syscrg_ne SYSCRG_NE_CLK_WDT_APB>,
+ <&syscrg_ne SYSCRG_NE_CLK_WDT>;
+ clock-names = "apb", "core";
+ resets = <&syscrg_ne SYSCRG_NE_RSTN_WDT0>;
+ };
+
syscrg_ne: syscrg_ne@12320000 {
compatible = "starfive,jh8100-syscrg-ne";
reg = <0x0 0x12320000 0x0 0x10000>;
--
2.25.1