Hi everyone,
This series is an attempt to get feedback on decoding D1 efuse speed bins
in the Sun50i H6 cpufreq driver, and turning the result into a meaningful
value that selects voltage ranges in an OPP table.
I want to make sure I get this right before sending in a v3 of the D1
cpufreq support series here
https://lore.kernel.org/linux-sunxi/[email protected]/T/#t
which is currently stuck at
https://lore.kernel.org/linux-sunxi/[email protected]/
Changes in v3:
- Drop 'len' parameter and pointer in sunxi_cpufreq_data::efuse_xlate()
prototype
Changes in v2:
- Make speed bin decoding generic in one patch and add D1 support in a
separate patch
- Fix OPP voltage ranges to avoid stability issues
Brandon Cheo Fusi (3):
cpufreq: sun50i: Refactor speed bin decoding
cpufreq: sun50i: Add support for D1's speed bin decoding
riscv: dts: allwinner: Fill in OPPs
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 19 +++-
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 89 +++++++++++++++----
2 files changed, 87 insertions(+), 21 deletions(-)
--
2.30.2
Adds support for decoding the efuse value read from D1 efuse speed
bins, and factors out equivalent code for sun50i.
The algorithm is gotten from
https://github.com/Tina-Linux/linux-5.4/blob/master/drivers/cpufreq/sun50i-cpufreq-nvmem.c#L293-L338
and maps an efuse value to either 0 or 1, with 1 meaning stable at
a lower supply voltage for the same clock frequency.
Signed-off-by: Brandon Cheo Fusi <[email protected]>
---
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index e8c2a1dc3..26bb5217b 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -29,6 +29,29 @@ struct sunxi_cpufreq_data {
u32 (*efuse_xlate)(u32 speedbin);
};
+static u32 sun20i_efuse_xlate(u32 speedbin)
+{
+ u32 ret;
+
+ switch (speedbin & 0xffff) {
+ case 0x5e00:
+ /* QFN package */
+ ret = 0;
+ break;
+ case 0x5c00:
+ case 0x7400:
+ /* QFN package */
+ ret = 1;
+ break;
+ case 0x5000:
+ default:
+ /* BGA package */
+ ret = 0;
+ }
+
+ return ret;
+}
+
static u32 sun50i_efuse_xlate(u32 speedbin)
{
u32 efuse_value;
@@ -46,6 +69,10 @@ static u32 sun50i_efuse_xlate(u32 speedbin)
return 0;
}
+struct sunxi_cpufreq_data sun20i_cpufreq_data = {
+ .efuse_xlate = sun20i_efuse_xlate,
+};
+
static struct sunxi_cpufreq_data sun50i_cpufreq_data = {
.efuse_xlate = sun50i_efuse_xlate,
};
@@ -54,6 +81,9 @@ static const struct of_device_id cpu_opp_match_list[] = {
{ .compatible = "allwinner,sun50i-h6-operating-points",
.data = &sun50i_cpufreq_data,
},
+ { .compatible = "allwinner,sun20i-d1-operating-points",
+ .data = &sun20i_cpufreq_data,
+ },
{}
};
@@ -182,6 +212,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
static const struct of_device_id sun50i_cpufreq_match_list[] = {
{ .compatible = "allwinner,sun50i-h6" },
+ { .compatible = "allwinner,sun20i-d1" },
{}
};
MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
--
2.30.2