Hi folks,
This series enables Multi Core Timer (MCT) for gs101. As part of enabling
MCT we also need to register cmu_misc bank of clocks early so exynos_mct can
obtain it's clock.
MCT timer is required longer term as the Arm arch timer can't wake the CPU from
suspend. This series is based off todays linux-next.
Note the dtsi change without the corresponding clock driver changes will result
in a system that doesn't boot. So ideally this would both be merged together
through Krzysztofs Samsung exynos tree. If that is OK with everyone?
regards,
Peter
Peter Griffin (3):
dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible
clk: samsung: gs101: register cmu_misc clocks early
arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
.../timer/samsung,exynos4210-mct.yaml | 2 ++
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 +++++++++++++++++++
drivers/clk/samsung/clk-gs101.c | 12 ++++++++---
3 files changed, 31 insertions(+), 3 deletions(-)
--
2.43.0.472.g3155946c3a-goog
Update cmu_misc so it is registered early, as it contains
the gate which clocks the Multi Core Timer (MCT). This clock
is required early in boot, otherwise exynos_mct will fail
obtaining the clock.
Note this wasn't previously an issue as exynos_mct wasn't
enabled.
Signed-off-by: Peter Griffin <[email protected]>
---
drivers/clk/samsung/clk-gs101.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 0964bb11657f..590119a25c18 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -2478,6 +2478,15 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = {
.clk_name = "dout_cmu_misc_bus",
};
+static void __init gs101_cmu_misc_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &misc_cmu_info);
+}
+
+/* Register CMU_MISC early, as it's needed for MCT timer */
+CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc",
+ gs101_cmu_misc_init);
+
/* ---- platform_driver ----------------------------------------------------- */
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -2495,9 +2504,6 @@ static const struct of_device_id gs101_cmu_of_match[] = {
{
.compatible = "google,gs101-cmu-apm",
.data = &apm_cmu_info,
- }, {
- .compatible = "google,gs101-cmu-misc",
- .data = &misc_cmu_info,
}, {
},
};
--
2.43.0.472.g3155946c3a-goog
MCT has one global timer and 8 CPU local timers. The global timer
can generate 4 interrupts, and each local timer can generate an
interrupt making 12 interrupts in total.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 9747cb3fa03a..4b09e740b58a 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -292,6 +292,26 @@ cmu_misc: clock-controller@10010000 {
clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
};
+ timer@10050000 {
+ compatible = "google,gs101-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
+ clock-names = "fin_pll", "mct";
+ };
+
watchdog_cl0: watchdog@10060000 {
compatible = "google,gs101-wdt";
reg = <0x10060000 0x100>;
--
2.43.0.472.g3155946c3a-goog
On Fri, Dec 22, 2023 at 10:54 AM Peter Griffin <[email protected]> wrote:
>
> Update cmu_misc so it is registered early, as it contains
> the gate which clocks the Multi Core Timer (MCT). This clock
> is required early in boot, otherwise exynos_mct will fail
> obtaining the clock.
>
> Note this wasn't previously an issue as exynos_mct wasn't
> enabled.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> drivers/clk/samsung/clk-gs101.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 0964bb11657f..590119a25c18 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -2478,6 +2478,15 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = {
> .clk_name = "dout_cmu_misc_bus",
> };
>
> +static void __init gs101_cmu_misc_init(struct device_node *np)
> +{
> + exynos_arm64_register_cmu(NULL, np, &misc_cmu_info);
> +}
> +
> +/* Register CMU_MISC early, as it's needed for MCT timer */
> +CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc",
> + gs101_cmu_misc_init);
> +
> /* ---- platform_driver ----------------------------------------------------- */
>
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -2495,9 +2504,6 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> {
> .compatible = "google,gs101-cmu-apm",
> .data = &apm_cmu_info,
> - }, {
> - .compatible = "google,gs101-cmu-misc",
> - .data = &misc_cmu_info,
> }, {
> },
> };
> --
> 2.43.0.472.g3155946c3a-goog
>
On Fri, Dec 22, 2023 at 10:54 AM Peter Griffin <[email protected]> wrote:
>
> MCT has one global timer and 8 CPU local timers. The global timer
> can generate 4 interrupts, and each local timer can generate an
> interrupt making 12 interrupts in total.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 9747cb3fa03a..4b09e740b58a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -292,6 +292,26 @@ cmu_misc: clock-controller@10010000 {
> clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
> };
>
> + timer@10050000 {
> + compatible = "google,gs101-mct",
> + "samsung,exynos4210-mct";
> + reg = <0x10050000 0x800>;
> + interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
> + clock-names = "fin_pll", "mct";
> + };
> +
> watchdog_cl0: watchdog@10060000 {
> compatible = "google,gs101-wdt";
> reg = <0x10060000 0x100>;
> --
> 2.43.0.472.g3155946c3a-goog
>
On Fri, 22 Dec 2023 16:53:55 +0000, Peter Griffin wrote:
> MCT has one global timer and 8 CPU local timers. The global timer
> can generate 4 interrupts, and each local timer can generate an
> interrupt making 12 interrupts in total.
>
>
Applied, thanks!
[3/3] arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
https://git.kernel.org/krzk/linux/c/2b1b22054a8240e8e806d872b6fc361611f9c7a2
Best regards,
--
Krzysztof Kozlowski <[email protected]>
On Fri, 22 Dec 2023 16:53:54 +0000, Peter Griffin wrote:
> Update cmu_misc so it is registered early, as it contains
> the gate which clocks the Multi Core Timer (MCT). This clock
> is required early in boot, otherwise exynos_mct will fail
> obtaining the clock.
>
> Note this wasn't previously an issue as exynos_mct wasn't
> enabled.
>
> [...]
Applied, thanks!
[2/3] clk: samsung: gs101: register cmu_misc clocks early
https://git.kernel.org/krzk/linux/c/163cd42fc49081964e0fc6f0b1e94b6b50eb85f5
Best regards,
--
Krzysztof Kozlowski <[email protected]>