Add the compatible and nodes for the QCE found on SM6350 SoC.
Not completely sure how to fully test it but "kcapi-speed --all" shows
no issues. Let me know if I can/should test this more.
Signed-off-by: Luca Weiss <[email protected]>
---
Luca Weiss (2):
dt-bindings: qcom-qce: Add compatible for SM6350
arm64: dts: qcom: sm6350: Add Crypto Engine
.../devicetree/bindings/crypto/qcom-qce.yaml | 1 +
arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++++++++++
2 files changed, 32 insertions(+)
---
base-commit: 610a9b8f49fbcf1100716370d3b5f6f884a2835a
change-id: 20240105-sm6350-qce-c6233abbf54f
Best regards,
--
Luca Weiss <[email protected]>
Add a compatible for the crypto block found on the SM6350 SoC.
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 8e665d910e6e..69d1c4929935 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -44,6 +44,7 @@ properties:
- items:
- enum:
+ - qcom,sm6350-qce
- qcom,sm8250-qce
- qcom,sm8350-qce
- qcom,sm8450-qce
--
2.43.0
Add crypto engine (CE) and CE BAM related nodes and definitions for this
SoC.
For reference:
[ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 8fd6f4d03490..516aadbb16bb 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1212,6 +1212,37 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <16>;
+ qcom,num-ees = <4>;
+ iommus = <&apps_smmu 0x432 0x0000>,
+ <&apps_smmu 0x438 0x0001>,
+ <&apps_smmu 0x43f 0x0000>,
+ <&apps_smmu 0x426 0x0011>,
+ <&apps_smmu 0x436 0x0011>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x432 0x0000>,
+ <&apps_smmu 0x438 0x0001>,
+ <&apps_smmu 0x43f 0x0000>,
+ <&apps_smmu 0x426 0x0011>,
+ <&apps_smmu 0x436 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sm6350-ipa";
--
2.43.0
On 05/01/2024 17:15, Luca Weiss wrote:
> Add a compatible for the crypto block found on the SM6350 SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 1/9/24 12:27, Luca Weiss wrote:
> On Mon Jan 8, 2024 at 1:40 PM CET, Konrad Dybcio wrote:
>> On 5.01.2024 17:15, Luca Weiss wrote:
>>> Add the compatible and nodes for the QCE found on SM6350 SoC.
>>>
>>> Not completely sure how to fully test it but "kcapi-speed --all" shows
>>> no issues. Let me know if I can/should test this more.
>>
>> I think I used `cryptsetup benchmark` with and without the ICE enabled
>> a couple years back. IIRC the CPU should be faaar faster but also chug
>> power while at it.
>
> Are you sure you mean QCE here (which this patch is about) and not ICE?
I.. think I do. It's been a while.
>
> I'm not aware of them working together somehow but I wouldn't be
> surprised if there's something since I don't know much of this area at
> all.
No idea
Konrad
On Fri, Feb 16, 2024 at 11:46:49AM +0100, Luca Weiss wrote:
> On Fri Jan 5, 2024 at 5:30 PM CET, Stephan Gerhold wrote:
> > On Fri, Jan 05, 2024 at 05:15:44PM +0100, Luca Weiss wrote:
> > > Add crypto engine (CE) and CE BAM related nodes and definitions for this
> > > SoC.
> > >
> > > For reference:
> > >
> > > [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1
> > >
> > > Signed-off-by: Luca Weiss <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 +++++++++++++++++++++++++++++++
> > > 1 file changed, 31 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > > index 8fd6f4d03490..516aadbb16bb 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > > @@ -1212,6 +1212,37 @@ ufs_mem_phy_lanes: phy@1d87400 {
> > > };
> > > };
> > >
> > > + cryptobam: dma-controller@1dc4000 {
> > > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> > > + reg = <0 0x01dc4000 0 0x24000>;
> > > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> > > + #dma-cells = <1>;
> > > + qcom,ee = <0>;
> > > + qcom,controlled-remotely;
> > > + num-channels = <16>;
> > > + qcom,num-ees = <4>;
> > > + iommus = <&apps_smmu 0x432 0x0000>,
> > > + <&apps_smmu 0x438 0x0001>,
> > > + <&apps_smmu 0x43f 0x0000>,
> > > + <&apps_smmu 0x426 0x0011>,
> > > + <&apps_smmu 0x436 0x0011>;
> >
> > The last two lines look equivalent to me: 0x436 & ~0x0011 = 0x426.
>
> I don't understand the IOMMU SID + mask really, but I think I've seen
> somewhere before like here that TZ can be a bit picky with the SIDs?
>
> https://lore.kernel.org/linux-arm-msm/opqdrmyj3y64nqqqmakjydn5rkspizufyeavm7ec7c7ufqz4wk@ey2a7bq3shfj/
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> I don't quite want to risk having some obscure use case breaking because
> we cleaned up the dts ;)
>
> But if you're more sure than me that it won't break, let me know!
>
> >
> > It's also a bit weird that the mask has one more digit than the stream
> > ID. And ordered numerically (by stream ID, first number) it would be a
> > bit easier to read. :-)
>
> Sorting them is no problem, can do that for v2.
>
Where you able to do this? I don't see a v2 in my inbox, am I just
searching poorly?
Regards,
Bjorn
> >
> > Thanks,
> > Stephan
>