2024-01-10 15:38:09

by Tomeu Vizoso

[permalink] [raw]
Subject: [PATCH 1/2] drm/etnaviv: Expose a few more chipspecs to userspace

These ones will be needed to make use fo the NN and TP units in the NPUs
based on Vivante IP.

Signed-off-by: Tomeu Vizoso <[email protected]>
Acked-by: Christian Gmeiner <[email protected]>
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 20 ++++++++++++++++++++
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 12 ++++++++++++
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 24 ++++++++++++++++++++++++
include/uapi/drm/etnaviv_drm.h | 5 +++++
4 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 9276756e1397..9055ed08cd7b 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -164,6 +164,26 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
*value = gpu->identity.eco_id;
break;

+ case ETNAVIV_PARAM_GPU_NN_CORE_COUNT:
+ *value = gpu->identity.nn_core_count;
+ break;
+
+ case ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE:
+ *value = gpu->identity.nn_mad_per_core;
+ break;
+
+ case ETNAVIV_PARAM_GPU_TP_CORE_COUNT:
+ *value = gpu->identity.tp_core_count;
+ break;
+
+ case ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE:
+ *value = gpu->identity.on_chip_sram_size;
+ break;
+
+ case ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE:
+ *value = gpu->identity.axi_sram_size;
+ break;
+
default:
DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
return -EINVAL;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 197e0037732e..7d5e9158e13c 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -54,6 +54,18 @@ struct etnaviv_chip_identity {
/* Number of Neural Network cores. */
u32 nn_core_count;

+ /* Number of MAD units per Neural Network core. */
+ u32 nn_mad_per_core;
+
+ /* Number of Tensor Processing cores. */
+ u32 tp_core_count;
+
+ /* Size in bytes of the SRAM inside the NPU. */
+ u32 on_chip_sram_size;
+
+ /* Size in bytes of the SRAM across the AXI bus. */
+ u32 axi_sram_size;
+
/* Size of the vertex cache. */
u32 vertex_cache_size;

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index 67201242438b..003e5faa1f4c 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -17,6 +17,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 128,
.shader_core_count = 1,
.nn_core_count = 0,
+ .nn_mad_per_core = 0,
+ .tp_core_count = 0,
+ .on_chip_sram_size = 0,
+ .axi_sram_size = 0,
.vertex_cache_size = 8,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -80,6 +84,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 512,
.shader_core_count = 2,
.nn_core_count = 0,
+ .nn_mad_per_core = 0,
+ .tp_core_count = 0,
+ .on_chip_sram_size = 0,
+ .axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -112,6 +120,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 512,
.shader_core_count = 2,
.nn_core_count = 0,
+ .nn_mad_per_core = 0,
+ .tp_core_count = 0,
+ .on_chip_sram_size = 0,
+ .axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -175,6 +187,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 1024,
.shader_core_count = 4,
.nn_core_count = 0,
+ .nn_mad_per_core = 0,
+ .tp_core_count = 0,
+ .on_chip_sram_size = 0,
+ .axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 2,
@@ -207,6 +223,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 256,
.shader_core_count = 1,
.nn_core_count = 8,
+ .nn_mad_per_core = 64,
+ .tp_core_count = 4,
+ .on_chip_sram_size = 524288,
+ .axi_sram_size = 1048576,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -239,6 +259,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.thread_count = 256,
.shader_core_count = 1,
.nn_core_count = 6,
+ .nn_mad_per_core = 64,
+ .tp_core_count = 3,
+ .on_chip_sram_size = 262144,
+ .axi_sram_size = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h
index af024d90453d..d87410a8443a 100644
--- a/include/uapi/drm/etnaviv_drm.h
+++ b/include/uapi/drm/etnaviv_drm.h
@@ -77,6 +77,11 @@ struct drm_etnaviv_timespec {
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
+#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f
+#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20
+#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21
+#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22
+#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23

#define ETNA_MAX_PIPES 4

--
2.43.0



2024-01-10 15:38:18

by Tomeu Vizoso

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Subject: [PATCH 2/2] arm64: dts: amlogic: meson-g12-common: Set the rates of the clocks for the NPU

Otherwise they are left at 24MHz and the NPU runs very slowly.

Signed-off-by: Tomeu Vizoso <[email protected]>
Suggested-by: Lucas Stach <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index ff68b911b729..9d5eab6595d0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2502,6 +2502,9 @@ npu: npu@ff100000 {
clocks = <&clkc CLKID_NNA_CORE_CLK>,
<&clkc CLKID_NNA_AXI_CLK>;
clock-names = "core", "bus";
+ assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>,
+ <&clkc CLKID_NNA_AXI_CLK>;
+ assigned-clock-rates = <800000000>, <800000000>;
resets = <&reset RESET_NNA>;
status = "disabled";
};
--
2.43.0


2024-01-10 16:25:01

by Neil Armstrong

[permalink] [raw]
Subject: Re: [PATCH 1/2] drm/etnaviv: Expose a few more chipspecs to userspace

Hi,

On Wed, 10 Jan 2024 16:37:00 +0100, Tomeu Vizoso wrote:
> These ones will be needed to make use fo the NN and TP units in the NPUs
> based on Vivante IP.
>
>

Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.9/arm64-dt)

[1/2] drm/etnaviv: Expose a few more chipspecs to userspace
(no commit info)
[2/2] arm64: dts: amlogic: meson-g12-common: Set the rates of the clocks for the NPU
https://git.kernel.org/amlogic/c/507b3e756ffcb174d383dd05df5084aed9bb6d14

These changes has been applied on the intermediate git tree [1].

The v6.9/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.

In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].

The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.

If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

--
Neil


2024-01-10 16:25:40

by Neil Armstrong

[permalink] [raw]
Subject: Re: [PATCH 1/2] drm/etnaviv: Expose a few more chipspecs to userspace

On 10/01/2024 17:24, Neil Armstrong wrote:
> Hi,
>
> On Wed, 10 Jan 2024 16:37:00 +0100, Tomeu Vizoso wrote:
>> These ones will be needed to make use fo the NN and TP units in the NPUs
>> based on Vivante IP.
>>
>>
>
> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.9/arm64-dt)
>
> [1/2] drm/etnaviv: Expose a few more chipspecs to userspace
> (no commit info)
> [2/2] arm64: dts: amlogic: meson-g12-common: Set the rates of the clocks for the NPU
> https://git.kernel.org/amlogic/c/507b3e756ffcb174d383dd05df5084aed9bb6d14

To be clear, I only applied patch 2.

Neil

>
> These changes has been applied on the intermediate git tree [1].
>
> The v6.9/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
> for inclusion in their intermediate git branches in order to be sent to Linus during
> the next merge window, or sooner if it's a set of fixes.
>
> In the cases of fixes, those will be merged in the current release candidate
> kernel and as soon they appear on the Linux master branch they will be
> backported to the previous Stable and Long-Stable kernels [2].
>
> The intermediate git branches are merged daily in the linux-next tree [3],
> people are encouraged testing these pre-release kernels and report issues on the
> relevant mailing-lists.
>
> If problems are discovered on those changes, please submit a signed-off-by revert
> patch followed by a corrective changeset.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
>