Add bindings, driver and devicetree node for networking sub system clock
controller on IPQ5332. Some of the nssnoc clocks present in GCC driver is
enabled by default and its RCG is configured by bootloaders, so enable
those clocks in driver probe.
The NSS clock controller driver depends on the below patchset which adds
support for multiple configurations for same frequency.
https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
---
Changes in v4:
- Rebased on next-20240122
- Fixed the missing space on the nsscc node
- Link to v3: https://lore.kernel.org/linux-arm-msm/[email protected]/
Changes in v3:
- Collected the tags
- Dropped the dt-binding patch 3/9
- Cleaned up the header file inclusion and updated the module
description in the driver
- Used the decimal number instead of hex in the NSSCC node
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Change logs are in respective patches
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Kathiravan Thirumoorthy (8):
clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock
clk: qcom: ipq5332: add gpll0_out_aux clock
dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions
clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
arm64: dts: qcom: ipq5332: add support for the NSSCC
arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
.../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 ++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5332.c | 122 +--
drivers/clk/qcom/nsscc-ipq5332.c | 1031 ++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++
9 files changed, 1260 insertions(+), 77 deletions(-)
---
base-commit: 319fbd8fc6d339e0a1c7b067eed870c518a13a02
change-id: 20231030-ipq5332-nsscc-aeac9e153045
Best regards,
--
Kathiravan Thirumoorthy <[email protected]>
Describe the NSS clock controller node and it's relevant external
clocks.
Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 42e2e48b2bc3..1e280e045b00 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -15,6 +15,18 @@ / {
#size-cells = <2>;
clocks {
+ cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ #clock-cells = <0>;
+ };
+
+ cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -473,6 +485,22 @@ frame@b128000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@39b00000 {
+ compatible = "qcom,ipq5332-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&cmn_pll_nss_200m_clk>,
+ <&cmn_pll_nss_300m_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&xo_board>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
};
timer {
--
2.34.1