This patch series is an update from the previous version [1] after
exex_op support and fixes (patch 1 to 4 from the previous version.)
It updates all the BCMBCA SoC to support the nand controller and add
functions to handle BCMBCA specific needs on ECC and Write Protection
usage. The device tree document is also updated accordingly with the new
properties needed by the driver.
In addition there is a bug fix for exec_op helper functions and on-die ECC.
[1] https://lore.kernel.org/lkml/[email protected]/
Changes in v3:
- Update brcm,nand-use-wp description
- Revert the description change to BCM63168 SoC-specific NAND controller
- Updated bcmbca_read_data_bus comment
Changes in v2:
- Revert the new compatible string nand-bcmbca
- Drop the BCM63168 compatible fix to avoid any potential ABI
Incompatibility issue
- Simplify the explanation for brcm,nand-use-wp
- Keep the interrupt name requirement when interrupt number is specified
- Add nand controller node label for 4908 so it is consistent with other
SoC's and can be referenced by board dts file
- Drop the is_param argument to the read data bus function now that we
have the exec_op API to read the parameter page and ONFI data
- Minor cosmetic fixes
- Added patches 8, 9, 10 to patch series
William Zhang (7):
dt-bindings: mtd: brcmnand: Updates for bcmbca SoCs
ARM: dts: broadcom: bcmbca: Add NAND controller node
arm64: dts: broadcom: bcmbca: Add NAND controller node
mtd: rawnand: brcmnand: Rename bcm63138 nand driver
mtd: rawnand: brcmnand: Add BCMBCA read data bus interface
mtd: rawnand: brcmnand: Add support for getting ecc setting from strap
mtd: rawnand: brcmnand: Support write protection setting from dts
David Regan (3):
mtd: rawnand: brcmnand: exec_op helper functions return type fixes
mtd: rawnand: brcmnand: update log level messages
mtd: rawnand: brcmnand: allow for on-die ecc
.../bindings/mtd/brcm,brcmnand.yaml | 37 ++++-
arch/arm/boot/dts/broadcom/bcm47622.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm63138.dtsi | 10 +-
arch/arm/boot/dts/broadcom/bcm63148.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm63178.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm6756.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm6846.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm6855.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm6878.dtsi | 17 ++
arch/arm/boot/dts/broadcom/bcm947622.dts | 4 +
arch/arm/boot/dts/broadcom/bcm963138.dts | 4 +
arch/arm/boot/dts/broadcom/bcm963138dvt.dts | 12 +-
arch/arm/boot/dts/broadcom/bcm963148.dts | 4 +
arch/arm/boot/dts/broadcom/bcm963178.dts | 4 +
arch/arm/boot/dts/broadcom/bcm96756.dts | 4 +
arch/arm/boot/dts/broadcom/bcm96846.dts | 4 +
arch/arm/boot/dts/broadcom/bcm96855.dts | 4 +
arch/arm/boot/dts/broadcom/bcm96878.dts | 4 +
.../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +-
.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 17 ++
.../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 17 ++
.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 17 ++
.../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 17 ++
.../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 17 ++
.../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 17 ++
.../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 +
.../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 +
.../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 +
.../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 +
.../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 +
.../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 +
drivers/mtd/nand/raw/brcmnand/Makefile | 2 +-
drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c | 99 ------------
drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c | 126 +++++++++++++++
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 146 +++++++++++++++---
drivers/mtd/nand/raw/brcmnand/brcmnand.h | 2 +
36 files changed, 578 insertions(+), 138 deletions(-)
delete mode 100644 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c
create mode 100644 drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
--
2.37.3
From: William Zhang <[email protected]>
The BCMBCA broadband SoC integrates the NAND controller differently than
STB, iProc and other SoCs. It has different endianness for NAND cache
data.
Add a SoC read data bus shim for BCMBCA to meet the specific SoC need
and performance improvement using the optimized memcpy function on NAND
cache memory.
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: David Regan <[email protected]>
---
Changes in v3:
- Updated bcmbca_read_data_bus comment
---
Changes in v2:
- Drop the is_param argument to the read data bus function now that we
have the exec_op API to read the parameter page and ONFI data
- Remove be32_to_cpu from brcmnand_read_data_bus
---
drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c | 27 +++++++++++++++++++++
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 ++++++++++++---
drivers/mtd/nand/raw/brcmnand/brcmnand.h | 2 ++
3 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
index 3e2f3b79788d..7ad3e7a98f97 100644
--- a/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
+++ b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
@@ -26,6 +26,18 @@ enum {
BCMBCA_CTLRDY = BIT(4),
};
+#if defined(CONFIG_ARM64)
+#define ALIGN_REQ 8
+#else
+#define ALIGN_REQ 4
+#endif
+
+static inline bool bcmbca_nand_is_buf_aligned(void *flash_cache, void *buffer)
+{
+ return IS_ALIGNED((uintptr_t)buffer, ALIGN_REQ) &&
+ IS_ALIGNED((uintptr_t)flash_cache, ALIGN_REQ);
+}
+
static bool bcmbca_nand_intc_ack(struct brcmnand_soc *soc)
{
struct bcmbca_nand_soc *priv =
@@ -56,6 +68,20 @@ static void bcmbca_nand_intc_set(struct brcmnand_soc *soc, bool en)
brcmnand_writel(val, mmio);
}
+static void bcmbca_read_data_bus(struct brcmnand_soc *soc,
+ void __iomem *flash_cache, u32 *buffer, int fc_words)
+{
+ /*
+ * memcpy can do unaligned aligned access depending on source
+ * and dest address, which is incompatible with nand cache. Fallback
+ * to the memcpy_fromio in such case
+ */
+ if (bcmbca_nand_is_buf_aligned((void *)flash_cache, buffer))
+ memcpy((void *)buffer, (void *)flash_cache, fc_words * 4);
+ else
+ memcpy_fromio((void *)buffer, flash_cache, fc_words * 4);
+}
+
static int bcmbca_nand_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -73,6 +99,7 @@ static int bcmbca_nand_probe(struct platform_device *pdev)
soc->ctlrdy_ack = bcmbca_nand_intc_ack;
soc->ctlrdy_set_enabled = bcmbca_nand_intc_set;
+ soc->read_data_bus = bcmbca_read_data_bus;
return brcmnand_probe(pdev, soc);
}
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 8faca43ae1ff..73fdf7ce21aa 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -851,6 +851,20 @@ static inline u32 edu_readl(struct brcmnand_controller *ctrl,
return brcmnand_readl(ctrl->edu_base + offs);
}
+static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl,
+ void __iomem *flash_cache, u32 *buffer, int fc_words)
+{
+ struct brcmnand_soc *soc = ctrl->soc;
+ int i;
+
+ if (soc->read_data_bus) {
+ soc->read_data_bus(soc, flash_cache, buffer, fc_words);
+ } else {
+ for (i = 0; i < fc_words; i++)
+ buffer[i] = brcmnand_read_fc(ctrl, i);
+ }
+}
+
static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
{
@@ -1975,7 +1989,7 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
{
struct brcmnand_host *host = nand_get_controller_data(chip);
struct brcmnand_controller *ctrl = host->ctrl;
- int i, j, ret = 0;
+ int i, ret = 0;
brcmnand_clear_ecc_addr(ctrl);
@@ -1988,8 +2002,8 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
if (likely(buf)) {
brcmnand_soc_data_bus_prepare(ctrl->soc, false);
- for (j = 0; j < FC_WORDS; j++, buf++)
- *buf = brcmnand_read_fc(ctrl, j);
+ brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS);
+ buf += FC_WORDS;
brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
}
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.h b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
index 928114c0be5e..7261a69989fe 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.h
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.h
@@ -24,6 +24,8 @@ struct brcmnand_soc {
void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
bool is_param);
+ void (*read_data_bus)(struct brcmnand_soc *soc, void __iomem *flash_cache,
+ u32 *buffer, int fc_words);
const struct brcmnand_io_ops *ops;
};
--
2.37.3
From: William Zhang <[email protected]>
BCMBCA broadband SoC based board design does not specify ecc setting in
dts but rather use the SoC NAND strap info to obtain the ecc strength
and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for
this purpose and update driver to support this option.
The generic nand ecc settings still take precedence over this flag. For
example, if nand-ecc-strength is set in the dts, the driver ignores the
strap setting and falls back to original behavior. This makes sure that
the existing BCMBCA board dts still works the old way even the strap
flag is set in the BCMBCA chip dtsi.
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: David Regan <[email protected]>
---
Changes in v3: None
---
Changes in v2:
- Minor cosmetic fixes
---
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 83 ++++++++++++++++++++++--
1 file changed, 76 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 73fdf7ce21aa..869ea64e9189 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -1038,6 +1038,19 @@ static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
return -1;
}
+static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ int shift = brcmnand_sector_1k_shift(ctrl);
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+
+ if (shift < 0)
+ return 0;
+
+ return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
+}
+
static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
{
struct brcmnand_controller *ctrl = host->ctrl;
@@ -1055,6 +1068,38 @@ static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
nand_writereg(ctrl, acc_control_offs, tmp);
}
+static int brcmnand_get_spare_size(struct brcmnand_host *host)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+ u32 acc = nand_readreg(ctrl, acc_control_offs);
+
+ return (acc & brcmnand_spare_area_mask(ctrl));
+}
+
+static int brcmnand_get_ecc_strength(struct brcmnand_host *host)
+{
+ struct brcmnand_controller *ctrl = host->ctrl;
+ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+ BRCMNAND_CS_ACC_CONTROL);
+ int sector_size_1k = brcmnand_get_sector_size_1k(host);
+ int spare_area_size, ecc_level, ecc_strength;
+ u32 acc;
+
+ spare_area_size = brcmnand_get_spare_size(host);
+ acc = nand_readreg(ctrl, acc_control_offs);
+ ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift;
+ if (sector_size_1k)
+ ecc_strength = ecc_level * 2;
+ else if (spare_area_size == 16 && ecc_level == 15)
+ ecc_strength = 1; /* hamming */
+ else
+ ecc_strength = ecc_level;
+
+ return ecc_strength;
+}
+
/***********************************************************************
* CS_NAND_SELECT
***********************************************************************/
@@ -2622,19 +2667,43 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
nanddev_get_memorg(&chip->base);
struct brcmnand_controller *ctrl = host->ctrl;
struct brcmnand_cfg *cfg = &host->hwcfg;
- char msg[128];
+ struct device_node *np = nand_get_flash_node(chip);
u32 offs, tmp, oob_sector;
- int ret;
+ int ret, sector_size_1k = 0;
+ bool use_strap = false;
+ char msg[128];
memset(cfg, 0, sizeof(*cfg));
+ use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap");
- ret = of_property_read_u32(nand_get_flash_node(chip),
- "brcm,nand-oob-sector-size",
+ /*
+ * Set ECC size and strength based on hw configuration from strap
+ * if device tree does not specify them and use strap property is set
+ * If ecc strength is set in dts, don't use strap setting.
+ */
+ if (chip->ecc.strength)
+ use_strap = 0;
+
+ if (use_strap) {
+ chip->ecc.strength = brcmnand_get_ecc_strength(host);
+ sector_size_1k = brcmnand_get_sector_size_1k(host);
+ if (chip->ecc.size == 0) {
+ if (sector_size_1k < 0)
+ chip->ecc.size = 512;
+ else
+ chip->ecc.size = 512 << sector_size_1k;
+ }
+ }
+
+ ret = of_property_read_u32(np, "brcm,nand-oob-sector-size",
&oob_sector);
if (ret) {
- /* Use detected size */
- cfg->spare_area_size = mtd->oobsize /
- (mtd->writesize >> FC_SHIFT);
+ if (use_strap)
+ cfg->spare_area_size = brcmnand_get_spare_size(host);
+ else
+ /* Use detected size */
+ cfg->spare_area_size = mtd->oobsize /
+ (mtd->writesize >> FC_SHIFT);
} else {
cfg->spare_area_size = oob_sector;
}
--
2.37.3
From: William Zhang <[email protected]>
Add support for Broadcom STB NAND controller in BCMBCA ARMv8 chip dts
files.
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: David Regan <[email protected]>
---
Changes in v3: None
---
Changes in v2:
- Add nand controller node label for 4908 so it is consistent with other
SoCs and can be referenced by board dts file
---
.../arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 ++++-
.../arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 17 +++++++++++++++++
.../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 17 +++++++++++++++++
.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 17 +++++++++++++++++
.../arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 17 +++++++++++++++++
.../arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 17 +++++++++++++++++
.../arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 17 +++++++++++++++++
.../arm64/boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++
.../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++
.../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++
.../arm64/boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++
.../arm64/boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++
.../arm64/boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++
13 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
index 2f124b027bbf..03a516d02501 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
@@ -589,7 +589,7 @@ hsspi: spi@1000 {
status = "disabled";
};
- nand-controller@1800 {
+ nand_controller: nand-controller@1800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
@@ -597,11 +597,14 @@ nand-controller@1800 {
reg-names = "nand", "nand-int-base";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nand_ctlrdy";
+ brcm,nand-use-wp = <0>;
status = "okay";
nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
index d658c81f7285..92a829542467 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
@@ -138,6 +138,23 @@ hsspi: spi@1000 {
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ brcm,nand-use-wp = <0>;
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
index 4f474d47022e..2283fd81ece6 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -119,6 +119,23 @@ hsspi: spi@1000 {
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ brcm,nand-use-wp = <0>;
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
index 909f254dc47d..c70177066a15 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -137,6 +137,23 @@ hsspi: spi@1000 {
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ brcm,nand-use-wp = <0>;
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
index 685ae32951c9..09115e3af694 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
@@ -138,6 +138,23 @@ hsspi: spi@1000 {
status = "disabled";
};
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ brcm,nand-use-wp = <0>;
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+ };
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
index 820553ce541b..03ed65b35dbc 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -119,5 +119,22 @@ hsspi: spi@1000 {
num-cs = <8>;
status = "disabled";
};
+
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ brcm,nand-use-wp = <0>;
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
index 0eb93c298297..36f1fc06fcec 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -156,5 +156,22 @@ hsspi: spi@1000 {
num-cs = <8>;
status = "disabled";
};
+
+ nand_controller: nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ brcm,nand-use-wp = <0>;
+ status = "disabled";
+
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ brcm,nand-ecc-use-strap;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
index e69cd683211a..4d1ea501e384 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
@@ -32,3 +32,7 @@ &uart0 {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
index db2c82d6dfd8..810b5a23da7b 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
@@ -32,3 +32,7 @@ &uart0 {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
index 25c12bc63545..3aaae5dbb568 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
@@ -32,3 +32,7 @@ &uart0 {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
index faba21f03120..6b167cc2af76 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
@@ -32,3 +32,7 @@ &uart0 {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
index 9808331eede2..d598cd618b57 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
@@ -32,3 +32,7 @@ &uart0 {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
index 1f561c8e13b0..e50ddbf6f58c 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
@@ -32,3 +32,7 @@ &uart0 {
&hsspi {
status = "okay";
};
+
+&nand_controller {
+ status = "okay";
+};
--
2.37.3
Hi David,
> @@ -2622,19 +2667,43 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
> nanddev_get_memorg(&chip->base);
> struct brcmnand_controller *ctrl = host->ctrl;
> struct brcmnand_cfg *cfg = &host->hwcfg;
> - char msg[128];
> + struct device_node *np = nand_get_flash_node(chip);
> u32 offs, tmp, oob_sector;
> - int ret;
> + int ret, sector_size_1k = 0;
> + bool use_strap = false;
> + char msg[128];
>
> memset(cfg, 0, sizeof(*cfg));
> + use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap");
>
> - ret = of_property_read_u32(nand_get_flash_node(chip),
> - "brcm,nand-oob-sector-size",
> + /*
> + * Set ECC size and strength based on hw configuration from strap
> + * if device tree does not specify them and use strap property is set
> + * If ecc strength is set in dts, don't use strap setting.
> + */
You would have to use the strap settings only if the property is set.
If not property is set, the default from the core should apply I guess.
> + if (chip->ecc.strength)
> + use_strap = 0;
> +
> + if (use_strap) {
> + chip->ecc.strength = brcmnand_get_ecc_strength(host);
> + sector_size_1k = brcmnand_get_sector_size_1k(host);
> + if (chip->ecc.size == 0) {
> + if (sector_size_1k < 0)
> + chip->ecc.size = 512;
> + else
> + chip->ecc.size = 512 << sector_size_1k;
> + }
> + }
> +
> + ret = of_property_read_u32(np, "brcm,nand-oob-sector-size",
> &oob_sector);
> if (ret) {
> - /* Use detected size */
> - cfg->spare_area_size = mtd->oobsize /
> - (mtd->writesize >> FC_SHIFT);
> + if (use_strap)
> + cfg->spare_area_size = brcmnand_get_spare_size(host);
> + else
> + /* Use detected size */
> + cfg->spare_area_size = mtd->oobsize /
> + (mtd->writesize >> FC_SHIFT);
> } else {
> cfg->spare_area_size = oob_sector;
> }
Thanks,
Miquèl
Hi Miquel,
On 1/24/24 09:32, Miquel Raynal wrote:
> Hi David,
>
>> @@ -2622,19 +2667,43 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
>> nanddev_get_memorg(&chip->base);
>> struct brcmnand_controller *ctrl = host->ctrl;
>> struct brcmnand_cfg *cfg = &host->hwcfg;
>> - char msg[128];
>> + struct device_node *np = nand_get_flash_node(chip);
>> u32 offs, tmp, oob_sector;
>> - int ret;
>> + int ret, sector_size_1k = 0;
>> + bool use_strap = false;
>> + char msg[128];
>>
>> memset(cfg, 0, sizeof(*cfg));
>> + use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap");
>>
>> - ret = of_property_read_u32(nand_get_flash_node(chip),
>> - "brcm,nand-oob-sector-size",
>> + /*
>> + * Set ECC size and strength based on hw configuration from strap
>> + * if device tree does not specify them and use strap property is set
>> + * If ecc strength is set in dts, don't use strap setting.
>> + */
>
> You would have to use the strap settings only if the property is set.
> If not property is set, the default from the core should apply I guess.
>
Maybe the comment confuse you... I will make it more clear. But the
logic here is exactly what you said. If no properties are set, the core
value is already set in chip->ecc.strength and chip->ecc.size and it
clear the use_strap flag too.
>> + if (chip->ecc.strength)
>> + use_strap = 0;
>> +
>> + if (use_strap) {
>> + chip->ecc.strength = brcmnand_get_ecc_strength(host);
>> + sector_size_1k = brcmnand_get_sector_size_1k(host);
>> + if (chip->ecc.size == 0) {
>> + if (sector_size_1k < 0)
>> + chip->ecc.size = 512;
>> + else
>> + chip->ecc.size = 512 << sector_size_1k;
>> + }
>> + }
>> +
>> + ret = of_property_read_u32(np, "brcm,nand-oob-sector-size",
>> &oob_sector);
>> if (ret) {
>> - /* Use detected size */
>> - cfg->spare_area_size = mtd->oobsize /
>> - (mtd->writesize >> FC_SHIFT);
>> + if (use_strap)
>> + cfg->spare_area_size = brcmnand_get_spare_size(host);
>> + else
>> + /* Use detected size */
>> + cfg->spare_area_size = mtd->oobsize /
>> + (mtd->writesize >> FC_SHIFT);
>> } else {
>> cfg->spare_area_size = oob_sector;
>> }
>
>
> Thanks,
> Miquèl