The previous patch put the phylink_suspend after the pm_runtime_force_suspend
to fix an issue. But in phylink_suspend, it will call mdio read/write. If the
iomux of the pins of MDIO bus have been changed to others, the MDIO bus will
not functional.
So put pinctrl_pm_select_sleep_state to the right place to fix this issue.
Fixes: 90702dcd19c0 ("net: stmmac: fix MAC not working when system resume back with WoL active")
Signed-off-by: Clark Wang <[email protected]>
Reviewed-by: Wei Fang <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index b334eb16da23..9104ebf49c5d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -7851,7 +7851,6 @@ int stmmac_suspend(struct device *dev)
priv->irq_wake = 1;
} else {
stmmac_mac_set(priv, priv->ioaddr, false);
- pinctrl_pm_select_sleep_state(priv->device);
}
mutex_unlock(&priv->lock);
@@ -7863,6 +7862,7 @@ int stmmac_suspend(struct device *dev)
if (device_may_wakeup(priv->device))
phylink_speed_down(priv->phylink, false);
phylink_suspend(priv->phylink, false);
+ pinctrl_pm_select_sleep_state(priv->device);
}
rtnl_unlock();
--
2.34.1
In RMII mode, the default setting is using the 50MHz reference clock
from SoC. The ref_clk pin is output.
If users want to use external or PHY to provide the 50MHz ref clock,
it needs to config the GPR register.
So, add the code to config GPR register to support the clock input.
Signed-off-by: Clark Wang <[email protected]>
Reviewed-by: Wei Fang <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
index 8f730ada71f9..64c5277895e6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
@@ -36,6 +36,8 @@
#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
#define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
+#define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0)
+#define MX93_GPR_CLK_SEL_OFFSET (4)
#define DMA_BUS_MODE 0x00001000
#define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
@@ -108,13 +110,22 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
{
struct imx_priv_data *dwmac = plat_dat->bsp_priv;
- int val;
+ int val, ret;
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
break;
case PHY_INTERFACE_MODE_RMII:
+ if (dwmac->rmii_refclk_ext) {
+ ret = regmap_update_bits(dwmac->intf_regmap,
+ dwmac->intf_reg_off +
+ MX93_GPR_CLK_SEL_OFFSET,
+ MX93_GPR_ENET_QOS_CLK_SEL_MASK,
+ 0);
+ if (ret)
+ return ret;
+ }
val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
break;
case PHY_INTERFACE_MODE_RGMII:
--
2.34.1
On Fri, Jan 26, 2024 at 10:44:33AM +0800, Clark Wang wrote:
> In RMII mode, the default setting is using the 50MHz reference clock
> from SoC. The ref_clk pin is output.
> If users want to use external or PHY to provide the 50MHz ref clock,
> it needs to config the GPR register.
> So, add the code to config GPR register to support the clock input.
Hi Clark
You have this threaded to the previous email. That previous email is a
fix, where are this is development of a new feature. So please don't
thread them. Please take a read of:
https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html
You need different Subject lines to indicate which tree these patches
should be applied to.
>
> Signed-off-by: Clark Wang <[email protected]>
> Reviewed-by: Wei Fang <[email protected]>
Signed-of-by comes last.
Andrew
---
pw-bot: cr