Hello all,
I know this has been tried before[0], but given the recent upstreaming of
the Series6+ GPU bindings I figured it might be time to give the Series5
bindings another try.
While there is currently no mainline driver for these binding, there is an
open source out-of-tree kernel-side driver available[1]. Having a stable
and upstream binding for these devices allows us to describe this hardware
in device tree.
This is my vision for how these bindings should look, along with some
example uses in several SoC DT files. The compatible names have been
updated to match what was decided on for Series6+, but otherwise most
is the same as we have been using in our vendor tree for many years.
Thanks,
Andrew
Based on next-20240109.
[0]: https://lkml.org/lkml/2020/4/24/1222
[1]: https://github.com/openpvrsgx-devgroup
Changes for v1:
- Added commit message to patch #1
- Reworked Rogue binding title
- Add TI copyright to new binding doc
- Added default min/maxItems to clocks property
- Moved "additionalProperties" to end
- Flattened out allOf block logic
- Added extra SGX binding example
- Added Suggested/Reviewed tags
Changes for RFC v2:
- Added patch to rename Rogue+ binding to img,powervr-rogue.yaml
- Locked all property item counts
- Removed nodename pattern check
Andrew Davis (11):
dt-bindings: gpu: Rename img,powervr to img,powervr-rogue
dt-bindings: gpu: Add PowerVR Series5 SGX GPUs
ARM: dts: omap3: Add device tree entry for SGX GPU
ARM: dts: omap4: Add device tree entry for SGX GPU
ARM: dts: omap5: Add device tree entry for SGX GPU
ARM: dts: AM33xx: Add device tree entry for SGX GPU
ARM: dts: AM437x: Add device tree entry for SGX GPU
ARM: dts: DRA7xx: Add device tree entry for SGX GPU
arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU
ARM: dts: sun6i: Add device tree entry for SGX GPU
MIPS: DTS: jz4780: Add device tree entry for SGX GPU
...mg,powervr.yaml => img,powervr-rogue.yaml} | 4 +-
.../bindings/gpu/img,powervr-sgx.yaml | 138 ++++++++++++++++++
MAINTAINERS | 3 +-
arch/arm/boot/dts/allwinner/sun6i-a31.dtsi | 9 ++
arch/arm/boot/dts/ti/omap/am33xx.dtsi | 9 +-
arch/arm/boot/dts/ti/omap/am3517.dtsi | 11 +-
arch/arm/boot/dts/ti/omap/am4372.dtsi | 6 +
arch/arm/boot/dts/ti/omap/dra7.dtsi | 9 +-
arch/arm/boot/dts/ti/omap/omap34xx.dtsi | 11 +-
arch/arm/boot/dts/ti/omap/omap36xx.dtsi | 9 +-
arch/arm/boot/dts/ti/omap/omap4.dtsi | 9 +-
arch/arm/boot/dts/ti/omap/omap5.dtsi | 9 +-
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 7 +
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 ++
14 files changed, 215 insertions(+), 30 deletions(-)
rename Documentation/devicetree/bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} (91%)
create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
--
2.39.2
Add SGX GPU device entry to base OMAP5 dtsi file.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Javier Martinez Canillas <[email protected]>
---
arch/arm/boot/dts/ti/omap/omap5.dtsi | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi
index bac6fa8387936..6a66214ad0e2f 100644
--- a/arch/arm/boot/dts/ti/omap/omap5.dtsi
+++ b/arch/arm/boot/dts/ti/omap/omap5.dtsi
@@ -453,10 +453,11 @@ target-module@56000000 {
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
+ gpu@0 {
+ compatible = "ti,omap5432-gpu", "img,powervr-sgx544";
+ reg = <0x0 0x2000000>; /* 32MB */
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
target-module@58000000 {
--
2.39.2
The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
multiple vendors. Describe how the SGX GPU is integrated in these SoC,
including register space and interrupts. Clocks, reset, and power domain
information is SoC specific.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Javier Martinez Canillas <[email protected]>
---
.../bindings/gpu/img,powervr-sgx.yaml | 138 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 139 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
new file mode 100644
index 0000000000000..f5898b04381cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Imagination Technologies Ltd.
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR SGX GPUs
+
+maintainers:
+ - Frank Binns <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ti,omap3430-gpu # Rev 121
+ - ti,omap3630-gpu # Rev 125
+ - const: img,powervr-sgx530
+ - items:
+ - enum:
+ - ingenic,jz4780-gpu # Rev 130
+ - ti,omap4430-gpu # Rev 120
+ - const: img,powervr-sgx540
+ - items:
+ - enum:
+ - allwinner,sun6i-a31-gpu # MP2 Rev 115
+ - ti,omap4470-gpu # MP1 Rev 112
+ - ti,omap5432-gpu # MP2 Rev 105
+ - ti,am5728-gpu # MP2 Rev 116
+ - ti,am6548-gpu # MP1 Rev 117
+ - const: img,powervr-sgx544
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: mem
+ - const: sys
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,am6548-gpu
+ then:
+ required:
+ - power-domains
+ else:
+ properties:
+ power-domains: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun6i-a31-gpu
+ - ingenic,jz4780-gpu
+ then:
+ required:
+ - clocks
+ - clock-names
+ else:
+ properties:
+ clocks: false
+ clock-names: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun6i-a31-gpu
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ingenic,jz4780-gpu
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ gpu@7000000 {
+ compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+ reg = <0x7000000 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpu: gpu@1c40000 {
+ compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 1>, <&ccu 2>;
+ clock-names = "core", "mem";
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2a4e8d2c69c40..b8b3aab5dd490 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10469,6 +10469,7 @@ M: Matt Coster <[email protected]>
S: Supported
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+F: Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
F: Documentation/gpu/imagination/
F: drivers/gpu/drm/imagination/
F: include/uapi/drm/pvr_drm.h
--
2.39.2
Add SGX GPU device entry to base jz4780 dtsi file.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Javier Martinez Canillas <[email protected]>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 18affff85ce38..5ea6833f5e872 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -460,6 +460,17 @@ hdmi: hdmi@10180000 {
status = "disabled";
};
+ gpu: gpu@13040000 {
+ compatible = "ingenic,jz4780-gpu", "img,powervr-sgx540";
+ reg = <0x13040000 0x4000>;
+
+ clocks = <&cgu JZ4780_CLK_GPU>;
+ clock-names = "core";
+
+ interrupt-parent = <&intc>;
+ interrupts = <63>;
+ };
+
lcdc0: lcdc0@13050000 {
compatible = "ingenic,jz4780-lcd";
reg = <0x13050000 0x1800>;
--
2.39.2
Add SGX GPU device entry to base AM654 dtsi file.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Javier Martinez Canillas <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index fcea544656360..64b52c8dafc6c 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -1050,6 +1050,13 @@ dss_ports: ports {
};
};
+ gpu: gpu@7000000 {
+ compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+ reg = <0x0 0x7000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+ };
+
ehrpwm0: pwm@3000000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
--
2.39.2
On 09/01/2024 18:19, Andrew Davis wrote:
> The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
> multiple vendors. Describe how the SGX GPU is integrated in these SoC,
> including register space and interrupts. Clocks, reset, and power domain
> information is SoC specific.
>
> Signed-off-by: Andrew Davis <[email protected]>
> Reviewed-by: Javier Martinez Canillas <[email protected]>
> + clock-names:
> + minItems: 1
> + items:
> + - const: core
> + - const: mem
> + - const: sys
There are no devices currently using third clock, but I assume it is
expected or possible.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
* Krzysztof Kozlowski <[email protected]> [240109 19:53]:
> On 09/01/2024 18:19, Andrew Davis wrote:
> > The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
> > multiple vendors. Describe how the SGX GPU is integrated in these SoC,
> > including register space and interrupts. Clocks, reset, and power domain
> > information is SoC specific.
> >
> > Signed-off-by: Andrew Davis <[email protected]>
> > Reviewed-by: Javier Martinez Canillas <[email protected]>
>
>
> > + clock-names:
> > + minItems: 1
> > + items:
> > + - const: core
> > + - const: mem
> > + - const: sys
>
> There are no devices currently using third clock, but I assume it is
> expected or possible.
I think the third clock is typically merged with one of the two clocks but
yeah possibly it's a separate clocke in some cases.
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
Looks good to me too.
So for merging these, as many of the changes touch the omap variants, I
could set up an immutable branch with all the changes after -rc1. Or I can
ack the patches too if somebody has better ideas.
Regards,
Tony
On Wed, Jan 10, 2024 at 10:38:57AM +0200, Tony Lindgren wrote:
> * Krzysztof Kozlowski <[email protected]> [240109 19:53]:
> > On 09/01/2024 18:19, Andrew Davis wrote:
> > > The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
> > > multiple vendors. Describe how the SGX GPU is integrated in these SoC,
> > > including register space and interrupts. Clocks, reset, and power domain
> > > information is SoC specific.
> > >
> > > Signed-off-by: Andrew Davis <[email protected]>
> > > Reviewed-by: Javier Martinez Canillas <[email protected]>
> >
> >
> > > + clock-names:
> > > + minItems: 1
> > > + items:
> > > + - const: core
> > > + - const: mem
> > > + - const: sys
> >
> > There are no devices currently using third clock, but I assume it is
> > expected or possible.
>
> I think the third clock is typically merged with one of the two clocks but
> yeah possibly it's a separate clocke in some cases.
>
> > Reviewed-by: Krzysztof Kozlowski <[email protected]>
>
> Looks good to me too.
>
> So for merging these, as many of the changes touch the omap variants, I
> could set up an immutable branch with all the changes after -rc1. Or I can
> ack the patches too if somebody has better ideas.
Just take all but patches 10 and 11. I don't think it matters if the
binding is there for them as long as it is all there in next. No one is
paying that close attention to the warnings I think.
Rob
* Rob Herring <[email protected]> [240119 17:48]:
> On Wed, Jan 10, 2024 at 10:38:57AM +0200, Tony Lindgren wrote:
> > So for merging these, as many of the changes touch the omap variants, I
> > could set up an immutable branch with all the changes after -rc1. Or I can
> > ack the patches too if somebody has better ideas.
>
> Just take all but patches 10 and 11. I don't think it matters if the
> binding is there for them as long as it is all there in next. No one is
> paying that close attention to the warnings I think.
OK I've now applied these except patches 10 and 11 into a sgx-for-v6.9
branch [0].
Regards,
Tony
[0] https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git/log/?h=sgx-for-v6.9