Add device tree binding for StarFive's JH8100 StarLink PMU (Performance
Monitor Unit).
Signed-off-by: Ji Sheng Teoh <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
---
.../perf/starfive,jh8100-starlink-pmu.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml
diff --git a/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml b/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml
new file mode 100644
index 000000000000..915c6b814026
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 StarLink PMU
+
+maintainers:
+ - Ji Sheng Teoh <[email protected]>
+
+description:
+ StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
+ shared L3 memory system. The PMU support overflow interrupt, up to
+ 16 programmable 64bit event counters, and an independent 64bit cycle
+ counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
+
+properties:
+ compatible:
+ const: starfive,jh8100-starlink-pmu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmu@12900000 {
+ compatible = "starfive,jh8100-starlink-pmu";
+ reg = <0x0 0x12900000 0x0 0x10000>;
+ interrupts = <34>;
+ };
+ };
--
2.43.0