tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 41bccc98fb7931d63d03f326a746ac4d429c1dd3
commit: 360de67280641e451bc944a06bab64ddbeaa7fb9 pinctrl: mediatek: add support for MT7986 SoC
date: 2 years, 3 months ago
config: i386-buildonly-randconfig-004-20240106 (https://download.01.org/0day-ci/archive/20240129/[email protected]/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240129/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'GPIO_BASE' not described in enum '(anonymous)'
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_RT_BASE' not described in enum '(anonymous)'
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_RB_BASE' not described in enum '(anonymous)'
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_LT_BASE' not described in enum '(anonymous)'
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_LB_BASE' not described in enum '(anonymous)'
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_TR_BASE' not described in enum '(anonymous)'
>> drivers/pinctrl/mediatek/pinctrl-mt7986.c:68: warning: Enum value 'IOCFG_TL_BASE' not described in enum '(anonymous)'
vim +68 drivers/pinctrl/mediatek/pinctrl-mt7986.c
13
14 #define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
15 _x_bits) \
16 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
17 _x_bits, 32, 0)
18
19 /**
20 * enum - Locking variants of the iocfg bases
21 *
22 * MT7986 have multiple bases to program pin configuration listed as the below:
23 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
24 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
25 * _i_based could be used to indicate what base the pin should be mapped into.
26 *
27 * Each iocfg register base control different group of pads on the SoC
28 *
29 *
30 * chip carrier
31 *
32 * A B C D E F G H
33 * +------------------------+
34 * 8 | o o o o o o o o |
35 * 7 | o o o o o o o o |
36 * 6 | o o o o o o o o |
37 * 5 | o o o o o o o o |
38 * 4 | o o o o o o o o |
39 * 3 | o o o o o o o o |
40 * 2 | o o o o o o o o |
41 * 1 | o o o o o o o o |
42 * +------------------------+
43 *
44 * inside Chip carrier
45 *
46 * A B C D E F G H
47 * +------------------------+
48 * 8 | |
49 * 7 | TL TR |
50 * 6 | +---------+ |
51 * 5 | LT | | RT |
52 * 4 | | | |
53 * 3 | LB | | RB |
54 * 2 | +---------+ |
55 * 1 | |
56 * +------------------------+
57 *
58 */
59
60 enum {
61 GPIO_BASE,
62 IOCFG_RT_BASE,
63 IOCFG_RB_BASE,
64 IOCFG_LT_BASE,
65 IOCFG_LB_BASE,
66 IOCFG_TR_BASE,
67 IOCFG_TL_BASE,
> 68 };
69
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