Currently, PCI core will enable D3 support for PCI bridges only when the
following conditions are met:
1. Platform is ACPI based
2. Thunderbolt controller is used
3. pcie_port_pm=force passed in cmdline
While options 1 and 2 do not apply to Qcom SoCs, option 3 will make the
life harder for distro maintainers. Due to this, runtime PM is also not
getting enabled for the bridges.
Ideally, D3 support should be enabled by default for the recent PCI
bridges, but we do not have a sane way to detect them. So let's adds a new
flag, "bridge_d3_capable" to "struct pci_dev" which could be set by the
bridge drivers for capable devices. This will allow the PCI core to enable
D3 support for the bridges during enumeration.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/pci.c | 3 +++
include/linux/pci.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d8f11a078924..8226a65d8ca1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3127,6 +3127,9 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
*/
if (dmi_get_bios_year() >= 2015)
return true;
+
+ if (bridge->bridge_d3_capable)
+ return true;
break;
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index add9368e6314..161c0acf2b3e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -376,6 +376,7 @@ struct pci_dev {
unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
unsigned int no_d3cold:1; /* D3cold is forbidden */
unsigned int bridge_d3:1; /* Allow D3 for bridge */
+ unsigned int bridge_d3_capable:1; /* D3 capability for bridge */
unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
unsigned int mmio_always_on:1; /* Disallow turning off io/mem
decoding during BAR sizing */
--
2.25.1