From: Shravan Chippa <[email protected]>
Changes from V4 -> V5:
Modified commit msg
Replaced the sf_pdma_of_xlate() function with
of_dma_xlate_by_chan_id()
Changes from V3 -> V4:
Removed unnecessary parentheses and extra space Added review tags
Changes from V2 -> V3:
Removed whitespace
Change naming convention of the macros (modified code as per new macros)
updated with new API device_get_match_data()
modified dt-bindings as per the commmets from v2
modified compatible name string for mpfs platform
Changes from V1 -> V2:
Removed internal review tags
Commit massages modified.
Added devicetree patch with new compatible name for mpfs platform
Added of_dma_controller_free() clenup call in sf_pdma_remove() function
V1:
This series does the following
1. Adds a PolarFire SoC specific compatible and code to support for
out-of-order dma transfers
2. Adds generic device tree bindings support by using
of_dma_controller_register()
Shravan Chippa (4):
dmaengine: sf-pdma: Support of_dma_controller_register()
dt-bindings: dma: sf-pdma: add new compatible name
dmaengine: sf-pdma: add mpfs-pdma compatible name
riscv: dts: microchip: add specific compatible for mpfs pdma
.../bindings/dma/sifive,fu540-c000-pdma.yaml | 1 +
arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +-
drivers/dma/sf-pdma/sf-pdma.c | 44 +++++++++++++++++--
drivers/dma/sf-pdma/sf-pdma.h | 8 +++-
4 files changed, 50 insertions(+), 5 deletions(-)
--
2.34.1
From: Shravan Chippa <[email protected]>
Add new compatible name microchip,mpfs-pdma to support
out of order dma transfers
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Shravan Chippa <[email protected]>
---
.../devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
index a1af0b906365..3b22183a1a37 100644
--- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
+++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
@@ -29,6 +29,7 @@ properties:
compatible:
items:
- enum:
+ - microchip,mpfs-pdma
- sifive,fu540-c000-pdma
- const: sifive,pdma0
description:
--
2.34.1
From: Shravan Chippa <[email protected]>
Sifive platform dma (sf-pdma) has both in-order and out-of-order
configurations but sf-pdam driver configured to do in-order DMA
transfers, with out-of-order configuration got better throughput
in the PolarFire SoC platform.
Add a PolarFire SoC specific compatible and code to support
for out-of-order dma transfers
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Shravan Chippa <[email protected]>
---
drivers/dma/sf-pdma/sf-pdma.c | 27 ++++++++++++++++++++++++---
drivers/dma/sf-pdma/sf-pdma.h | 8 +++++++-
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c
index 6109e1c5a09e..428473611115 100644
--- a/drivers/dma/sf-pdma/sf-pdma.c
+++ b/drivers/dma/sf-pdma/sf-pdma.c
@@ -25,6 +25,8 @@
#include "sf-pdma.h"
+#define PDMA_QUIRK_NO_STRICT_ORDERING BIT(0)
+
#ifndef readq
static inline unsigned long long readq(void __iomem *addr)
{
@@ -66,7 +68,7 @@ static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan)
static void sf_pdma_fill_desc(struct sf_pdma_desc *desc,
u64 dst, u64 src, u64 size)
{
- desc->xfer_type = PDMA_FULL_SPEED;
+ desc->xfer_type = desc->chan->pdma->transfer_type;
desc->xfer_size = size;
desc->dst_addr = dst;
desc->src_addr = src;
@@ -493,6 +495,7 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma)
static int sf_pdma_probe(struct platform_device *pdev)
{
+ const struct sf_pdma_driver_platdata *ddata;
struct sf_pdma *pdma;
int ret, n_chans;
const enum dma_slave_buswidth widths =
@@ -518,6 +521,14 @@ static int sf_pdma_probe(struct platform_device *pdev)
pdma->n_chans = n_chans;
+ pdma->transfer_type = PDMA_FULL_SPEED | PDMA_STRICT_ORDERING;
+
+ ddata = device_get_match_data(&pdev->dev);
+ if (ddata) {
+ if (ddata->quirks & PDMA_QUIRK_NO_STRICT_ORDERING)
+ pdma->transfer_type &= ~PDMA_STRICT_ORDERING;
+ }
+
pdma->membase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdma->membase))
return PTR_ERR(pdma->membase);
@@ -603,9 +614,19 @@ static void sf_pdma_remove(struct platform_device *pdev)
dma_async_device_unregister(&pdma->dma_dev);
}
+static const struct sf_pdma_driver_platdata mpfs_pdma = {
+ .quirks = PDMA_QUIRK_NO_STRICT_ORDERING,
+};
+
static const struct of_device_id sf_pdma_dt_ids[] = {
- { .compatible = "sifive,fu540-c000-pdma" },
- { .compatible = "sifive,pdma0" },
+ {
+ .compatible = "sifive,fu540-c000-pdma",
+ }, {
+ .compatible = "sifive,pdma0",
+ }, {
+ .compatible = "microchip,mpfs-pdma",
+ .data = &mpfs_pdma,
+ },
{},
};
MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids);
diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h
index d05772b5d8d3..215e07183d7e 100644
--- a/drivers/dma/sf-pdma/sf-pdma.h
+++ b/drivers/dma/sf-pdma/sf-pdma.h
@@ -48,7 +48,8 @@
#define PDMA_ERR_STATUS_MASK GENMASK(31, 31)
/* Transfer Type */
-#define PDMA_FULL_SPEED 0xFF000008
+#define PDMA_FULL_SPEED 0xFF000000
+#define PDMA_STRICT_ORDERING BIT(3)
/* Error Recovery */
#define MAX_RETRY 1
@@ -112,8 +113,13 @@ struct sf_pdma {
struct dma_device dma_dev;
void __iomem *membase;
void __iomem *mappedbase;
+ u32 transfer_type;
u32 n_chans;
struct sf_pdma_chan chans[] __counted_by(n_chans);
};
+struct sf_pdma_driver_platdata {
+ u32 quirks;
+};
+
#endif /* _SF_PDMA_H */
--
2.34.1
From: Shravan Chippa <[email protected]>
Add specific compatible for PolarFire SoC for The SiFive PDMA driver
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Shravan Chippa <[email protected]>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index a6faf24f1dba..e3e9c5b2b33c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -236,7 +236,7 @@ plic: interrupt-controller@c000000 {
};
pdma: dma-controller@3000000 {
- compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
+ compatible = "microchip,mpfs-pdma", "sifive,pdma0";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
--
2.34.1
On Fri, 08 Dec 2023 16:08:52 +0530, shravan chippa wrote:
> Changes from V4 -> V5:
>
> Modified commit msg
> Replaced the sf_pdma_of_xlate() function with
> of_dma_xlate_by_chan_id()
>
> Changes from V3 -> V4:
>
> [...]
Applied, thanks!
[1/4] dmaengine: sf-pdma: Support of_dma_controller_register()
commit: 8e578b47e6d92d5e43982ddc54045973dd4a7de5
[2/4] dt-bindings: dma: sf-pdma: add new compatible name
commit: 72b22006ba78c2e3bf39b486a7b8155dc9020133
[3/4] dmaengine: sf-pdma: add mpfs-pdma compatible name
commit: 58eea79a1cf285a62af886851b1a91ed5aceb401
Best regards,
--
~Vinod
From: Conor Dooley <[email protected]>
On Fri, 08 Dec 2023 16:08:52 +0530, shravan chippa wrote:
> From: Shravan Chippa <[email protected]>
>
> Changes from V4 -> V5:
>
> Modified commit msg
> Replaced the sf_pdma_of_xlate() function with
> of_dma_xlate_by_chan_id()
>
> [...]
Applied to riscv-dt-for-next, thanks!
[4/4] riscv: dts: microchip: add specific compatible for mpfs pdma
https://git.kernel.org/conor/c/5669bb5a16a0
Thanks,
Conor.