2024-02-07 04:22:56

by Hojin Nam

Subject: [PATCH v2] perf: CXL: fix mismatched cpmu event opcode

S2M NDR BI-ConflictAck opcode is described as 4 in the CXL
r3.1 3.3.9 Table 3.50. However, it is defined as 3 in macro definition. Also
adds s2m_ndr_cmpm for bit 3 that was added in CXL r3.1.

Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
Signed-off-by: Hojin Nam <[email protected]>
---

Hi Jonathan,
I've modified the commit messsge and code to reflect you mentioned. Thank you!

Changes since v1:
- Add s2m_ndr_cmpm event attribute (Jonathan)


drivers/perf/cxl_pmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
index 365d964b0f6a..d85d53d907a6 100644
--- a/drivers/perf/cxl_pmu.c
+++ b/drivers/perf/cxl_pmu.c
@@ -415,11 +415,12 @@ static struct attribute *cxl_pmu_event_attrs[] = {
CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblk, CXL_PMU_GID_S2M_BISNP, BIT(4)),
CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_datblk, CXL_PMU_GID_S2M_BISNP, BIT(5)),
CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblk, CXL_PMU_GID_S2M_BISNP, BIT(6)),
- /* CXL rev 3.0 Table 3-43 S2M NDR Opcopdes */
+ /* CXL rev 3.1 Table 3-50 S2M NDR Opcopdes */
CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CXL_PMU_GID_S2M_NDR, BIT(0)),
CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CXL_PMU_GID_S2M_NDR, BIT(1)),
CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CXL_PMU_GID_S2M_NDR, BIT(2)),
- CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(3)),
+ CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpm, CXL_PMU_GID_S2M_NDR, BIT(3)),
+ CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(4)),
/* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata, CXL_PMU_GID_S2M_DRS, BIT(0)),
CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm, CXL_PMU_GID_S2M_DRS, BIT(1)),
--
2.34.1

2024-02-07 12:28:33

by Jonathan Cameron

Subject: Re: [PATCH v2] perf: CXL: fix mismatched cpmu event opcode

On Wed, 07 Feb 2024 13:22:35 +0900
Hojin Nam <[email protected]> wrote:

> S2M NDR BI-ConflictAck opcode is described as 4 in the CXL
> r3.1 3.3.9 Table 3.50. However, it is defined as 3 in macro definition. Also
> adds s2m_ndr_cmpm for bit 3 that was added in CXL r3.1.
>
> Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
> Signed-off-by: Hojin Nam <[email protected]>

Ah. Sorry I've mislead you. I lazily assumed this was in the 3.0 spec as well
without checking.

As a fix, we should not add the cmpm or update the reference comment.

So should be the v1 patch with a reference to table 3-43 in r3.0
and the fixes tag.

A follow up patch to add the 3.1 definitions would be excellent but we shouldn't
be looking to backport that so it doesn't belong in the fix :(


Jonathan


> ---
>
> Hi Jonathan,
> I've modified the commit messsge and code to reflect you mentioned. Thank you!
>
> Changes since v1:
> - Add s2m_ndr_cmpm event attribute (Jonathan)
>
>
> drivers/perf/cxl_pmu.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> index 365d964b0f6a..d85d53d907a6 100644
> --- a/drivers/perf/cxl_pmu.c
> +++ b/drivers/perf/cxl_pmu.c
> @@ -415,11 +415,12 @@ static struct attribute *cxl_pmu_event_attrs[] = {
> CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblk, CXL_PMU_GID_S2M_BISNP, BIT(4)),
> CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_datblk, CXL_PMU_GID_S2M_BISNP, BIT(5)),
> CXL_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblk, CXL_PMU_GID_S2M_BISNP, BIT(6)),
> - /* CXL rev 3.0 Table 3-43 S2M NDR Opcopdes */
> + /* CXL rev 3.1 Table 3-50 S2M NDR Opcopdes */
> CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CXL_PMU_GID_S2M_NDR, BIT(0)),
> CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CXL_PMU_GID_S2M_NDR, BIT(1)),
> CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CXL_PMU_GID_S2M_NDR, BIT(2)),
> - CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(3)),
> + CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpm, CXL_PMU_GID_S2M_NDR, BIT(3)),
> + CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CXL_PMU_GID_S2M_NDR, BIT(4)),
> /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
> CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata, CXL_PMU_GID_S2M_DRS, BIT(0)),
> CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm, CXL_PMU_GID_S2M_DRS, BIT(1)),
> --
> 2.34.1