Finally touch the hfpll doc and convert it to yaml, and do some related
changes along the way.
Signed-off-by: Luca Weiss <[email protected]>
---
Changes in v2:
- Drop APQ8064/IPQ8064/MSM8960 compatibles (Dmitry)
- Update example to MSM8974 since IPQ8064 is dropped
- Clean up dt binding description (Krzysztof)
- Remove second example in docs (Krzysztof)
- Try to clear up the text and content around deprecating qcom,hfpll
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Luca Weiss (3):
dt-bindings: clock: qcom,hfpll: Convert to YAML
clk: qcom: hfpll: Add QCS404-specific compatible
arm64: dts: qcom: qcs404: Use qcs404-hfpll compatible for hfpll
.../devicetree/bindings/clock/qcom,hfpll.txt | 63 --------------------
.../devicetree/bindings/clock/qcom,hfpll.yaml | 69 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
drivers/clk/qcom/hfpll.c | 6 +-
4 files changed, 74 insertions(+), 66 deletions(-)
---
base-commit: 841c35169323cd833294798e58b9bf63fa4fa1de
change-id: 20231231-hfpll-yaml-9266f012365c
Best regards,
--
Luca Weiss <[email protected]>
Follow the updated bindings and use a QCS404-specific compatible for the
HFPLL on this SoC.
Signed-off-by: Luca Weiss <[email protected]>
---
Please note that this patch should only land after the patch for the
clock driver.
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 2f2eeaf2e945..4133d5a19deb 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1308,7 +1308,7 @@ apcs_glb: mailbox@b011000 {
};
apcs_hfpll: clock-controller@b016000 {
- compatible = "qcom,hfpll";
+ compatible = "qcom,qcs404-hfpll";
reg = <0x0b016000 0x30>;
#clock-cells = <0>;
clock-output-names = "apcs_hfpll";
--
2.43.2
Convert the .txt documentation to .yaml with some adjustments.
* APQ8064/IPQ8064/MSM8960 compatibles are dropped since their HFPLLs are
a part of GCC so there is no need for a separate compat entry.
* Change the MSM8974 compatible to follow the updated naming schema.
Theis compatible is not used upstream yet.
* Add qcs404-hfpll. QCS404 currently uses qcom,hfpll. Mark that as
deprecated since every SoC appears to need different driver data so
"qcom,hfpll" makes no sense to keep
Signed-off-by: Luca Weiss <[email protected]>
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 63 --------------------
.../devicetree/bindings/clock/qcom,hfpll.yaml | 69 ++++++++++++++++++++++
2 files changed, 69 insertions(+), 63 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
deleted file mode 100644
index 5769cbbe76be..000000000000
--- a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-High-Frequency PLL (HFPLL)
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>:
- shall contain only one of the following. The generic
- compatible "qcom,hfpll" should be also included.
-
- "qcom,hfpll-ipq8064", "qcom,hfpll"
- "qcom,hfpll-apq8064", "qcom,hfpll"
- "qcom,hfpll-msm8974", "qcom,hfpll"
- "qcom,hfpll-msm8960", "qcom,hfpll"
- "qcom,msm8976-hfpll-a53", "qcom,hfpll"
- "qcom,msm8976-hfpll-a72", "qcom,hfpll"
- "qcom,msm8976-hfpll-cci", "qcom,hfpll"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: address and size of HPLL registers. An optional second
- element specifies the address and size of the alias
- register region.
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: reference to the xo clock.
-
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "xo".
-
-- clock-output-names:
- Usage: required
- Value type: <string>
- Definition: Name of the PLL. Typically hfpllX where X is a CPU number
- starting at 0. Otherwise hfpll_Y where Y is more specific
- such as "l2".
-
-Example:
-
-1) An HFPLL for the L2 cache.
-
- clock-controller@f9016000 {
- compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
- reg = <0xf9016000 0x30>;
- clocks = <&xo_board>;
- clock-names = "xo";
- clock-output-names = "hfpll_l2";
- };
-
-2) An HFPLL for CPU0. This HFPLL has the alias register region.
-
- clock-controller@f908a000 {
- compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
- reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
- clocks = <&xo_board>;
- clock-names = "xo";
- clock-output-names = "hfpll0";
- };
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.yaml b/Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
new file mode 100644
index 000000000000..8cb1c164f760
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm High-Frequency PLL
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+
+description:
+ The HFPLL is used as CPU PLL on various Qualcomm SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - qcom,msm8974-hfpll
+ - qcom,msm8976-hfpll-a53
+ - qcom,msm8976-hfpll-a72
+ - qcom,msm8976-hfpll-cci
+ - qcom,qcs404-hfpll
+ - const: qcom,hfpll
+ deprecated: true
+
+ reg:
+ items:
+ - description: HFPLL registers
+ - description: Alias register region
+ minItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: board XO clock
+
+ clock-names:
+ items:
+ - const: xo
+
+ clock-output-names:
+ description:
+ Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.
+ Otherwise hfpll_Y where Y is more specific such as "l2".
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@f908a000 {
+ compatible = "qcom,msm8974-hfpll";
+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
+ #clock-cells = <0>;
+ clock-output-names = "hfpll0";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
--
2.43.2
It doesn't appear that the configuration is for the HFPLL is generic, so
add a qcs404-specific compatible and rename the existing struct to
qcs404.
Keep qcom,hfpll in the driver for compatibility with old dtbs.
Signed-off-by: Luca Weiss <[email protected]>
---
drivers/clk/qcom/hfpll.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index dac27e31ef60..b0b0cb074b4a 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -14,7 +14,7 @@
#include "clk-regmap.h"
#include "clk-hfpll.h"
-static const struct hfpll_data hdata = {
+static const struct hfpll_data qcs404 = {
.mode_reg = 0x00,
.l_reg = 0x04,
.m_reg = 0x08,
@@ -84,10 +84,12 @@ static const struct hfpll_data msm8976_cci = {
};
static const struct of_device_id qcom_hfpll_match_table[] = {
- { .compatible = "qcom,hfpll", .data = &hdata },
{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
+ { .compatible = "qcom,qcs404-hfpll", .data = &qcs404 },
+ /* Deprecated in bindings */
+ { .compatible = "qcom,hfpll", .data = &qcs404 },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
--
2.43.2
On Sun, 18 Feb 2024 at 22:58, Luca Weiss <[email protected]> wrote:
>
> Follow the updated bindings and use a QCS404-specific compatible for the
> HFPLL on this SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Please note that this patch should only land after the patch for the
> clock driver.
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 18/02/2024 21:57, Luca Weiss wrote:
> Convert the .txt documentation to .yaml with some adjustments.
>
> * APQ8064/IPQ8064/MSM8960 compatibles are dropped since their HFPLLs are
> a part of GCC so there is no need for a separate compat entry.
> * Change the MSM8974 compatible to follow the updated naming schema.
> Theis compatible is not used upstream yet.
> * Add qcs404-hfpll. QCS404 currently uses qcom,hfpll. Mark that as
> deprecated since every SoC appears to need different driver data so
> "qcom,hfpll" makes no sense to keep
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 18/02/2024 21:57, Luca Weiss wrote:
> Follow the updated bindings and use a QCS404-specific compatible for the
> HFPLL on this SoC.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Please note that this patch should only land after the patch for the
> clock driver.
> ---
This patch should go in the next cycle, after clock driver is merged to
mainline, to preserve bisectability.
Best regards,
Krzysztof
On Sun, 18 Feb 2024 21:57:24 +0100, Luca Weiss wrote:
> Finally touch the hfpll doc and convert it to yaml, and do some related
> changes along the way.
>
>
Applied, thanks!
[1/3] dt-bindings: clock: qcom,hfpll: Convert to YAML
commit: 849ed9d414d04e369bccc2278d75becde9e40e0f
[2/3] clk: qcom: hfpll: Add QCS404-specific compatible
commit: 3db0f3b9ff5adb6a5e8564a32fadb2af1216810d
Best regards,
--
Bjorn Andersson <[email protected]>