As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt
controller.
PolarFire implements its own PCIe interrupts, additional to the regular
PCIe interrupts, due to lack of an MSI controller, so the interrupt to
event number mapping is different to the PLDA regular interrupts,
necessitating a custom get_events() implementation.
Microchip Polarfire PCIe additional intrerrupts:
EVENT_PCIE_L2_EXIT
EVENT_PCIE_HOTRST_EXIT
EVENT_PCIE_DLUP_EXIT
EVENT_SEC_TX_RAM_SEC_ERR
EVENT_SEC_RX_RAM_SEC_ERR
...
plda_get_events() adds interrupt register to PLDA event num mapping codes.
All The PLDA interrupts can be seen in new added graph.
Signed-off-by: Minda Chen <[email protected]>
Acked-by: Conor Dooley <[email protected]>
---
.../pci/controller/plda/pcie-microchip-host.c | 35 ++++++++++++++++++-
drivers/pci/controller/plda/pcie-plda.h | 32 +++++++++++++++++
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c
index 8a51d3aa7e88..b3df373a2141 100644
--- a/drivers/pci/controller/plda/pcie-microchip-host.c
+++ b/drivers/pci/controller/plda/pcie-microchip-host.c
@@ -626,6 +626,26 @@ static u32 mc_get_events(struct plda_pcie_rp *port)
return events;
}
+static u32 plda_get_events(struct plda_pcie_rp *port)
+{
+ u32 events, val, origin;
+
+ origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL);
+
+ /* MSI event and sys events */
+ val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT;
+ events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1);
+
+ /* INTx events */
+ if (origin & PM_MSI_INT_INTX_MASK)
+ events |= BIT(PM_MSI_INT_INTX_SHIFT);
+
+ /* remains are same with register */
+ events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0);
+
+ return events;
+}
+
static irqreturn_t mc_event_handler(int irq, void *dev_id)
{
struct plda_pcie_rp *port = dev_id;
@@ -656,7 +676,7 @@ static void plda_handle_event(struct irq_desc *desc)
chained_irq_enter(chip, desc);
- events = mc_get_events(port);
+ events = port->event_ops->get_events(port);
for_each_set_bit(bit, &events, port->num_events)
generic_handle_domain_irq(port->event_domain, bit);
@@ -750,6 +770,10 @@ static struct irq_chip mc_event_irq_chip = {
.irq_unmask = mc_unmask_event_irq,
};
+static const struct plda_event_ops plda_event_ops = {
+ .get_events = plda_get_events,
+};
+
static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
@@ -815,6 +839,10 @@ static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq,
0, event_cause[event].sym, plda);
}
+static const struct plda_event_ops mc_event_ops = {
+ .get_events = mc_get_events,
+};
+
static const struct plda_event mc_event = {
.request_event_irq = mc_request_event_irq,
.intx_event = EVENT_LOCAL_PM_MSI_INT_INTX,
@@ -931,6 +959,9 @@ static int plda_init_interrupts(struct platform_device *pdev,
int i, intx_irq, msi_irq, event_irq;
int ret;
+ if (!port->event_ops)
+ port->event_ops = &plda_event_ops;
+
ret = plda_pcie_init_irq_domains(port);
if (ret) {
dev_err(dev, "failed creating IRQ domains\n");
@@ -1007,6 +1038,8 @@ static int mc_platform_init(struct pci_config_window *cfg)
if (ret)
return ret;
+ port->plda.event_ops = &mc_event_ops;
+
/* Address translation is up; safe to enable interrupts */
ret = plda_init_interrupts(pdev, &port->plda, &mc_event);
if (ret)
diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h
index 89172ce18237..e0e5e7cc8434 100644
--- a/drivers/pci/controller/plda/pcie-plda.h
+++ b/drivers/pci/controller/plda/pcie-plda.h
@@ -58,6 +58,7 @@
#define PM_MSI_INT_EVENTS_SHIFT 30
#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
#define PM_MSI_INT_SYS_ERR_SHIFT 31
+#define SYS_AND_MSI_MASK GENMASK(31, 28)
#define NUM_LOCAL_EVENTS 15
#define ISTATUS_LOCAL 0x184
#define IMASK_HOST 0x188
@@ -108,6 +109,36 @@ enum plda_int_event {
#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
+/*
+ * PLDA interrupt register
+ *
+ * 31 27 23 15 7 0
+ * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+
+ * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end |
+ * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+
+ * bit 0-7 DMA interrupt end : reserved for vendor implement
+ * bit 8-15 DMA error : reserved for vendor implement
+ * 0: AXI post error (PLDA_AXI_POST_ERR)
+ * 1: AXI fetch error (PLDA_AXI_FETCH_ERR)
+ * 2: AXI discard error (PLDA_AXI_DISCARD_ERR)
+ * 3: AXI doorbell (PLDA_PCIE_DOORBELL)
+ * 4: PCIe post error (PLDA_PCIE_POST_ERR)
+ * 5: PCIe fetch error (PLDA_PCIE_FETCH_ERR)
+ * 6: PCIe discard error (PLDA_PCIE_DISCARD_ERR)
+ * 7: PCIe doorbell (PLDA_PCIE_DOORBELL)
+ * 8: 4 INTx interruts (PLDA_INTX)
+ * 9: MSI interrupt (PLDA_MSI)
+ * 10: AER event (PLDA_AER_EVENT)
+ * 11: PM/LTR/Hotplug (PLDA_MISC_EVENTS)
+ * 12: System error (PLDA_SYS_ERR)
+ */
+
+struct plda_pcie_rp;
+
+struct plda_event_ops {
+ u32 (*get_events)(struct plda_pcie_rp *pcie);
+};
+
struct plda_msi {
struct mutex lock; /* Protect used bitmap */
struct irq_domain *msi_domain;
@@ -123,6 +154,7 @@ struct plda_pcie_rp {
struct irq_domain *event_domain;
raw_spinlock_t lock;
struct plda_msi msi;
+ const struct plda_event_ops *event_ops;
void __iomem *bridge_addr;
int num_events;
};
--
2.17.1
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt
controller.
Microchip PolarFire PCIE event IRQs includes PLDA interrupts and
Polarfire their own interrupts. The interrupt irqchip ops includes
ack/mask/unmask interrupt ops, which will write correct registers.
Microchip Polarfire PCIe additional interrupts require to write Polarfire
SoC self-defined registers. So Microchip PCIe event irqchip ops can not
be re-used.
To support PLDA its own event IRQ process, implements PLDA irqchip ops and
add event irqchip field to struct pcie_plda_rp.
Signed-off-by: Minda Chen <[email protected]>
Acked-by: Conor Dooley <[email protected]>
---
.../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
drivers/pci/controller/plda/pcie-plda.h | 3 +
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c
index b3df373a2141..beaf5c27da84 100644
--- a/drivers/pci/controller/plda/pcie-microchip-host.c
+++ b/drivers/pci/controller/plda/pcie-microchip-host.c
@@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
.irq_unmask = mc_unmask_event_irq,
};
+static u32 plda_hwirq_to_mask(int hwirq)
+{
+ u32 mask;
+
+ /* hwirq 23 - 0 are the same with register */
+ if (hwirq < EVENT_PM_MSI_INT_INTX)
+ mask = BIT(hwirq);
+ else if (hwirq == EVENT_PM_MSI_INT_INTX)
+ mask = PM_MSI_INT_INTX_MASK;
+ else
+ mask = BIT(hwirq + PCI_NUM_INTX - 1);
+
+ return mask;
+}
+
+static void plda_ack_event_irq(struct irq_data *data)
+{
+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
+
+ writel_relaxed(plda_hwirq_to_mask(data->hwirq),
+ port->bridge_addr + ISTATUS_LOCAL);
+}
+
+static void plda_mask_event_irq(struct irq_data *data)
+{
+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
+ u32 mask, val;
+
+ mask = plda_hwirq_to_mask(data->hwirq);
+
+ raw_spin_lock(&port->lock);
+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
+ val &= ~mask;
+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
+ raw_spin_unlock(&port->lock);
+}
+
+static void plda_unmask_event_irq(struct irq_data *data)
+{
+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
+ u32 mask, val;
+
+ mask = plda_hwirq_to_mask(data->hwirq);
+
+ raw_spin_lock(&port->lock);
+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
+ val |= mask;
+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
+ raw_spin_unlock(&port->lock);
+}
+
+static struct irq_chip plda_event_irq_chip = {
+ .name = "PLDA PCIe EVENT",
+ .irq_ack = plda_ack_event_irq,
+ .irq_mask = plda_mask_event_irq,
+ .irq_unmask = plda_unmask_event_irq,
+};
+
static const struct plda_event_ops plda_event_ops = {
.get_events = plda_get_events,
};
@@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops = {
static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
- irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
+ struct plda_pcie_rp *port = (void *)domain->host_data;
+
+ irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq);
irq_set_chip_data(irq, domain->host_data);
return 0;
@@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device *pdev,
if (!port->event_ops)
port->event_ops = &plda_event_ops;
+ if (!port->event_irq_chip)
+ port->event_irq_chip = &plda_event_irq_chip;
+
ret = plda_pcie_init_irq_domains(port);
if (ret) {
dev_err(dev, "failed creating IRQ domains\n");
@@ -1039,6 +1102,7 @@ static int mc_platform_init(struct pci_config_window *cfg)
return ret;
port->plda.event_ops = &mc_event_ops;
+ port->plda.event_irq_chip = &mc_event_irq_chip;
/* Address translation is up; safe to enable interrupts */
ret = plda_init_interrupts(pdev, &port->plda, &mc_event);
diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h
index e0e5e7cc8434..a3ce01735bea 100644
--- a/drivers/pci/controller/plda/pcie-plda.h
+++ b/drivers/pci/controller/plda/pcie-plda.h
@@ -107,6 +107,8 @@ enum plda_int_event {
#define PLDA_NUM_DMA_EVENTS 16
+#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX)
+#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI)
#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
/*
@@ -155,6 +157,7 @@ struct plda_pcie_rp {
raw_spinlock_t lock;
struct plda_msi msi;
const struct plda_event_ops *event_ops;
+ const struct irq_chip *event_irq_chip;
void __iomem *bridge_addr;
int num_events;
};
--
2.17.1
>
> As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
> plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt
> controller.
>
> Microchip PolarFire PCIE event IRQs includes PLDA interrupts and Polarfire their
> own interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt
> ops, which will write correct registers.
> Microchip Polarfire PCIe additional interrupts require to write Polarfire SoC
> self-defined registers. So Microchip PCIe event irqchip ops can not be re-used.
>
> To support PLDA its own event IRQ process, implements PLDA irqchip ops and
> add event irqchip field to struct pcie_plda_rp.
>
> Signed-off-by: Minda Chen <[email protected]>
> Acked-by: Conor Dooley <[email protected]>
> ---
> .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
> drivers/pci/controller/plda/pcie-plda.h | 3 +
> 2 files changed, 68 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> b/drivers/pci/controller/plda/pcie-microchip-host.c
> index b3df373a2141..beaf5c27da84 100644
> --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
> .irq_unmask = mc_unmask_event_irq,
> };
>
Hi Thomas
I think this patch code it is easy to review. If you busy, Could you let other
IRQ maintainer review? Thanks.
Hi Lorenzo, Bjorn and Krzysztof
Now the code is pending several weeks. Maybe this patch is blocking.
Actually I write irqchip ops(ack/mask/unmask) like microchip irqchip ops.
They looks very simple that write PLDA mask or status register. They all call the
same function plda_hwirq_to_mask(). Now you can see this function below.
Except INTx interrupt, one irqnum mapping to one register bit. The PLDA register
graph can be seen 14th patch, which can show all the PLDA interrupts and easy to
get PLDA codes logic.
Now the 6.9-next will be closed less than 20 days. I still hope the refactoring patches
(patch 1 - 16) can be accepted to 6.9. (Starfive and PLDA patches have to be delayed
to 6.10 or later). I will try my best to achieve it because this series patches reviewed lasts
a long period and Conor have reviewed all the refactoring patches.
I have no experience in refactoring code before this series patches. I try my best to do this.
Maybe I did something wrong in this. Please forgive me.
> +static u32 plda_hwirq_to_mask(int hwirq) {
> + u32 mask;
> +
> + /* hwirq 23 - 0 are the same with register */
> + if (hwirq < EVENT_PM_MSI_INT_INTX)
> + mask = BIT(hwirq);
> + else if (hwirq == EVENT_PM_MSI_INT_INTX)
> + mask = PM_MSI_INT_INTX_MASK;
> + else
> + mask = BIT(hwirq + PCI_NUM_INTX - 1);
> +
> + return mask;
> +}
> +
> +static void plda_ack_event_irq(struct irq_data *data) {
> + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> +
> + writel_relaxed(plda_hwirq_to_mask(data->hwirq),
> + port->bridge_addr + ISTATUS_LOCAL); }
> +
> +static void plda_mask_event_irq(struct irq_data *data) {
> + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> + u32 mask, val;
> +
> + mask = plda_hwirq_to_mask(data->hwirq);
> +
> + raw_spin_lock(&port->lock);
> + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> + val &= ~mask;
> + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> + raw_spin_unlock(&port->lock);
> +}
> +
> +static void plda_unmask_event_irq(struct irq_data *data) {
> + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> + u32 mask, val;
> +
> + mask = plda_hwirq_to_mask(data->hwirq);
> +
> + raw_spin_lock(&port->lock);
> + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> + val |= mask;
> + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> + raw_spin_unlock(&port->lock);
> +}
> +
> +static struct irq_chip plda_event_irq_chip = {
> + .name = "PLDA PCIe EVENT",
> + .irq_ack = plda_ack_event_irq,
> + .irq_mask = plda_mask_event_irq,
> + .irq_unmask = plda_unmask_event_irq,
> +};
> +
> static const struct plda_event_ops plda_event_ops = {
> .get_events = plda_get_events,
> };
> @@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops =
> { static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
> irq_hw_number_t hwirq)
> {
> - irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
> + struct plda_pcie_rp *port = (void *)domain->host_data;
> +
> + irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq);
> irq_set_chip_data(irq, domain->host_data);
>
> return 0;
> @@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device
> *pdev,
> if (!port->event_ops)
> port->event_ops = &plda_event_ops;
>
> + if (!port->event_irq_chip)
> + port->event_irq_chip = &plda_event_irq_chip;
> +
> ret = plda_pcie_init_irq_domains(port);
> if (ret) {
> dev_err(dev, "failed creating IRQ domains\n"); @@ -1039,6 +1102,7
> @@ static int mc_platform_init(struct pci_config_window *cfg)
> return ret;
>
> port->plda.event_ops = &mc_event_ops;
> + port->plda.event_irq_chip = &mc_event_irq_chip;
>
> /* Address translation is up; safe to enable interrupts */
> ret = plda_init_interrupts(pdev, &port->plda, &mc_event); diff --git
> a/drivers/pci/controller/plda/pcie-plda.h
> b/drivers/pci/controller/plda/pcie-plda.h
> index e0e5e7cc8434..a3ce01735bea 100644
> --- a/drivers/pci/controller/plda/pcie-plda.h
> +++ b/drivers/pci/controller/plda/pcie-plda.h
> @@ -107,6 +107,8 @@ enum plda_int_event {
>
> #define PLDA_NUM_DMA_EVENTS 16
>
> +#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS +
> PLDA_INTX)
> +#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS +
> PLDA_MSI)
> #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS +
> PLDA_INT_EVENT_NUM)
>
> /*
> @@ -155,6 +157,7 @@ struct plda_pcie_rp {
> raw_spinlock_t lock;
> struct plda_msi msi;
> const struct plda_event_ops *event_ops;
> + const struct irq_chip *event_irq_chip;
> void __iomem *bridge_addr;
> int num_events;
> };
> --
> 2.17.1
On Tue, Feb 20, 2024 at 1:02 PM Minda Chen <minda.chen@starfivetechcom> wrote:
>
>
> >
> > As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
> > plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt
> > controller.
> >
> > Microchip PolarFire PCIE event IRQs includes PLDA interrupts and Polarfire their
> > own interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt
> > ops, which will write correct registers.
> > Microchip Polarfire PCIe additional interrupts require to write Polarfire SoC
> > self-defined registers. So Microchip PCIe event irqchip ops can not be re-used.
> >
> > To support PLDA its own event IRQ process, implements PLDA irqchip ops and
> > add event irqchip field to struct pcie_plda_rp.
> >
> > Signed-off-by: Minda Chen <[email protected]>
> > Acked-by: Conor Dooley <[email protected]>
> > ---
> > .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
> > drivers/pci/controller/plda/pcie-plda.h | 3 +
> > 2 files changed, 68 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> > b/drivers/pci/controller/plda/pcie-microchip-host.c
> > index b3df373a2141..beaf5c27da84 100644
> > --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> > +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> > @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
> > .irq_unmask = mc_unmask_event_irq,
> > };
> >
> Hi Thomas
> I think this patch code it is easy to review. If you busy, Could you let other
> IRQ maintainer review? Thanks.
>
> Hi Lorenzo, Bjorn and Krzysztof
Hi Minda,
This patchset seems to have broken threading (lore, mailman). I have
seen other folks on IRC mentioning that too.
I am not sure if that requires re-sending, but let's wait for others to comment.
Cheers,
david
> Now the code is pending several weeks. Maybe this patch is blocking.
> Actually I write irqchip ops(ack/mask/unmask) like microchip irqchip ops.
> They looks very simple that write PLDA mask or status register. They all call the
> same function plda_hwirq_to_mask(). Now you can see this function below.
> Except INTx interrupt, one irqnum mapping to one register bit. The PLDA register
> graph can be seen 14th patch, which can show all the PLDA interrupts and easy to
> get PLDA codes logic.
>
> Now the 6.9-next will be closed less than 20 days. I still hope the refactoring patches
> (patch 1 - 16) can be accepted to 6.9. (Starfive and PLDA patches have to be delayed
> to 6.10 or later). I will try my best to achieve it because this series patches reviewed lasts
> a long period and Conor have reviewed all the refactoring patches.
>
> I have no experience in refactoring code before this series patches. I try my best to do this.
> Maybe I did something wrong in this. Please forgive me.
>
> > +static u32 plda_hwirq_to_mask(int hwirq) {
> > + u32 mask;
> > +
> > + /* hwirq 23 - 0 are the same with register */
> > + if (hwirq < EVENT_PM_MSI_INT_INTX)
> > + mask = BIT(hwirq);
> > + else if (hwirq == EVENT_PM_MSI_INT_INTX)
> > + mask = PM_MSI_INT_INTX_MASK;
> > + else
> > + mask = BIT(hwirq + PCI_NUM_INTX - 1);
> > +
> > + return mask;
> > +}
> > +
> > +static void plda_ack_event_irq(struct irq_data *data) {
> > + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> > +
> > + writel_relaxed(plda_hwirq_to_mask(data->hwirq),
> > + port->bridge_addr + ISTATUS_LOCAL); }
> > +
> > +static void plda_mask_event_irq(struct irq_data *data) {
> > + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> > + u32 mask, val;
> > +
> > + mask = plda_hwirq_to_mask(data->hwirq);
> > +
> > + raw_spin_lock(&port->lock);
> > + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> > + val &= ~mask;
> > + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> > + raw_spin_unlock(&port->lock);
> > +}
> > +
> > +static void plda_unmask_event_irq(struct irq_data *data) {
> > + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> > + u32 mask, val;
> > +
> > + mask = plda_hwirq_to_mask(data->hwirq);
> > +
> > + raw_spin_lock(&port->lock);
> > + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> > + val |= mask;
> > + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> > + raw_spin_unlock(&port->lock);
> > +}
> > +
> > +static struct irq_chip plda_event_irq_chip = {
> > + .name = "PLDA PCIe EVENT",
> > + .irq_ack = plda_ack_event_irq,
> > + .irq_mask = plda_mask_event_irq,
> > + .irq_unmask = plda_unmask_event_irq,
> > +};
> > +
> > static const struct plda_event_ops plda_event_ops = {
> > .get_events = plda_get_events,
> > };
> > @@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops =
> > { static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
> > irq_hw_number_t hwirq)
> > {
> > - irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
> > + struct plda_pcie_rp *port = (void *)domain->host_data;
> > +
> > + irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq);
> > irq_set_chip_data(irq, domain->host_data);
> >
> > return 0;
> > @@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device
> > *pdev,
> > if (!port->event_ops)
> > port->event_ops = &plda_event_ops;
> >
> > + if (!port->event_irq_chip)
> > + port->event_irq_chip = &plda_event_irq_chip;
> > +
> > ret = plda_pcie_init_irq_domains(port);
> > if (ret) {
> > dev_err(dev, "failed creating IRQ domains\n"); @@ -1039,6 +1102,7
> > @@ static int mc_platform_init(struct pci_config_window *cfg)
> > return ret;
> >
> > port->plda.event_ops = &mc_event_ops;
> > + port->plda.event_irq_chip = &mc_event_irq_chip;
> >
> > /* Address translation is up; safe to enable interrupts */
> > ret = plda_init_interrupts(pdev, &port->plda, &mc_event); diff --git
> > a/drivers/pci/controller/plda/pcie-plda.h
> > b/drivers/pci/controller/plda/pcie-plda.h
> > index e0e5e7cc8434..a3ce01735bea 100644
> > --- a/drivers/pci/controller/plda/pcie-plda.h
> > +++ b/drivers/pci/controller/plda/pcie-plda.h
> > @@ -107,6 +107,8 @@ enum plda_int_event {
> >
> > #define PLDA_NUM_DMA_EVENTS 16
> >
> > +#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS +
> > PLDA_INTX)
> > +#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS +
> > PLDA_MSI)
> > #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS +
> > PLDA_INT_EVENT_NUM)
> >
> > /*
> > @@ -155,6 +157,7 @@ struct plda_pcie_rp {
> > raw_spinlock_t lock;
> > struct plda_msi msi;
> > const struct plda_event_ops *event_ops;
> > + const struct irq_chip *event_irq_chip;
> > void __iomem *bridge_addr;
> > int num_events;
> > };
> > --
> > 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> On Tue, Feb 20, 2024 at 1:02 PM Minda Chen <[email protected]>
> wrote:
> >
> >
> > >
> > > As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
> > > plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an
> > > interrupt controller.
> > >
> > > Microchip PolarFire PCIE event IRQs includes PLDA interrupts and
> > > Polarfire their own interrupts. The interrupt irqchip ops includes
> > > ack/mask/unmask interrupt ops, which will write correct registers.
> > > Microchip Polarfire PCIe additional interrupts require to write
> > > Polarfire SoC self-defined registers. So Microchip PCIe event irqchip ops can
> not be re-used.
> > >
> > > To support PLDA its own event IRQ process, implements PLDA irqchip
> > > ops and add event irqchip field to struct pcie_plda_rp.
> > >
> > > Signed-off-by: Minda Chen <[email protected]>
> > > Acked-by: Conor Dooley <[email protected]>
> > > ---
> > > .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
> > > drivers/pci/controller/plda/pcie-plda.h | 3 +
> > > 2 files changed, 68 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> > > b/drivers/pci/controller/plda/pcie-microchip-host.c
> > > index b3df373a2141..beaf5c27da84 100644
> > > --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> > > +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> > > @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
> > > .irq_unmask = mc_unmask_event_irq, };
> > >
> > Hi Thomas
> > I think this patch code it is easy to review. If you busy, Could you
> > let other IRQ maintainer review? Thanks.
> >
> > Hi Lorenzo, Bjorn and Krzysztof
>
> Hi Minda,
>
> This patchset seems to have broken threading (lore, mailman). I have seen other
> folks on IRC mentioning that too.
>
> I am not sure if that requires re-sending, but let's wait for others to comment.
>
> Cheers,
> david
>
Do you mean the auto test error in linux-riscv?
I can see that. But In v14 resend version, There is no error. Version 15 just add
a new patch. Other no change. It is very strange.
If not this error, I will waiting others comment.
> > Now the code is pending several weeks. Maybe this patch is blocking.
> > Actually I write irqchip ops(ack/mask/unmask) like microchip irqchip ops.
> > They looks very simple that write PLDA mask or status register. They
> > all call the same function plda_hwirq_to_mask(). Now you can see this
> function below.
> > Except INTx interrupt, one irqnum mapping to one register bit. The
> > PLDA register graph can be seen 14th patch, which can show all the
> > PLDA interrupts and easy to get PLDA codes logic.
> >
> > Now the 6.9-next will be closed less than 20 days. I still hope the
> > refactoring patches (patch 1 - 16) can be accepted to 6.9. (Starfive
> > and PLDA patches have to be delayed to 6.10 or later). I will try my
> > best to achieve it because this series patches reviewed lasts a long period and
> Conor have reviewed all the refactoring patches.
> >
> > I have no experience in refactoring code before this series patches. I try my
> best to do this.
> > Maybe I did something wrong in this. Please forgive me.
> >
> > > +static u32 plda_hwirq_to_mask(int hwirq) {
> > > + u32 mask;
> > > +
> > > + /* hwirq 23 - 0 are the same with register */
> > > + if (hwirq < EVENT_PM_MSI_INT_INTX)
> > > + mask = BIT(hwirq);
> > > + else if (hwirq == EVENT_PM_MSI_INT_INTX)
> > > + mask = PM_MSI_INT_INTX_MASK;
> > > + else
> > > + mask = BIT(hwirq + PCI_NUM_INTX - 1);
> > > +
> > > + return mask;
> > > +}
> > > +
> > > +static void plda_ack_event_irq(struct irq_data *data) {
> > > + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> > > +
> > > + writel_relaxed(plda_hwirq_to_mask(data->hwirq),
> > > + port->bridge_addr + ISTATUS_LOCAL); }
> > > +
> > > +static void plda_mask_event_irq(struct irq_data *data) {
> > > + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> > > + u32 mask, val;
> > > +
> > > + mask = plda_hwirq_to_mask(data->hwirq);
> > > +
> > > + raw_spin_lock(&port->lock);
> > > + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> > > + val &= ~mask;
> > > + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> > > + raw_spin_unlock(&port->lock);
> > > +}
> > > +
> > > +static void plda_unmask_event_irq(struct irq_data *data) {
> > > + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> > > + u32 mask, val;
> > > +
> > > + mask = plda_hwirq_to_mask(data->hwirq);
> > > +
> > > + raw_spin_lock(&port->lock);
> > > + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> > > + val |= mask;
> > > + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> > > + raw_spin_unlock(&port->lock);
> > > +}
> > > +
> > > +static struct irq_chip plda_event_irq_chip = {
> > > + .name = "PLDA PCIe EVENT",
> > > + .irq_ack = plda_ack_event_irq,
> > > + .irq_mask = plda_mask_event_irq,
> > > + .irq_unmask = plda_unmask_event_irq, };
> > > +
> > > static const struct plda_event_ops plda_event_ops = {
> > > .get_events = plda_get_events, }; @@ -777,7 +835,9 @@ static
> > > const struct plda_event_ops plda_event_ops = { static int
> > > plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
> > > irq_hw_number_t hwirq) {
> > > - irq_set_chip_and_handler(irq, &mc_event_irq_chip,
> handle_level_irq);
> > > + struct plda_pcie_rp *port = (void *)domain->host_data;
> > > +
> > > + irq_set_chip_and_handler(irq, port->event_irq_chip,
> handle_level_irq);
> > > irq_set_chip_data(irq, domain->host_data);
> > >
> > > return 0;
> > > @@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct
> platform_device
> > > *pdev,
> > > if (!port->event_ops)
> > > port->event_ops = &plda_event_ops;
> > >
> > > + if (!port->event_irq_chip)
> > > + port->event_irq_chip = &plda_event_irq_chip;
> > > +
> > > ret = plda_pcie_init_irq_domains(port);
> > > if (ret) {
> > > dev_err(dev, "failed creating IRQ domains\n"); @@
> -1039,6 +1102,7
> > > @@ static int mc_platform_init(struct pci_config_window *cfg)
> > > return ret;
> > >
> > > port->plda.event_ops = &mc_event_ops;
> > > + port->plda.event_irq_chip = &mc_event_irq_chip;
> > >
> > > /* Address translation is up; safe to enable interrupts */
> > > ret = plda_init_interrupts(pdev, &port->plda, &mc_event); diff --git
> > > a/drivers/pci/controller/plda/pcie-plda.h
> > > b/drivers/pci/controller/plda/pcie-plda.h
> > > index e0e5e7cc8434..a3ce01735bea 100644
> > > --- a/drivers/pci/controller/plda/pcie-plda.h
> > > +++ b/drivers/pci/controller/plda/pcie-plda.h
> > > @@ -107,6 +107,8 @@ enum plda_int_event {
> > >
> > > #define PLDA_NUM_DMA_EVENTS 16
> > >
> > > +#define EVENT_PM_MSI_INT_INTX
> (PLDA_NUM_DMA_EVENTS +
> > > PLDA_INTX)
> > > +#define EVENT_PM_MSI_INT_MSI
> (PLDA_NUM_DMA_EVENTS +
> > > PLDA_MSI)
> > > #define PLDA_MAX_EVENT_NUM
> (PLDA_NUM_DMA_EVENTS +
> > > PLDA_INT_EVENT_NUM)
> > >
> > > /*
> > > @@ -155,6 +157,7 @@ struct plda_pcie_rp {
> > > raw_spinlock_t lock;
> > > struct plda_msi msi;
> > > const struct plda_event_ops *event_ops;
> > > + const struct irq_chip *event_irq_chip;
> > > void __iomem *bridge_addr;
> > > int num_events;
> > > };
> > > --
> > > 2.17.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi,
On 2024-02-21 10:10, Minda Chen wrote:
>
>
> >
> > On Tue, Feb 20, 2024 at 1:02 PM Minda Chen <[email protected]>
> > wrote:
> > >
> > >
> > > >
> > > > As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
> > > > plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an
> > > > interrupt controller.
> > > >
> > > > Microchip PolarFire PCIE event IRQs includes PLDA interrupts and
> > > > Polarfire their own interrupts. The interrupt irqchip ops includes
> > > > ack/mask/unmask interrupt ops, which will write correct registers.
> > > > Microchip Polarfire PCIe additional interrupts require to write
> > > > Polarfire SoC self-defined registers. So Microchip PCIe event irqchip ops can
> > not be re-used.
> > > >
> > > > To support PLDA its own event IRQ process, implements PLDA irqchip
> > > > ops and add event irqchip field to struct pcie_plda_rp.
> > > >
> > > > Signed-off-by: Minda Chen <[email protected]>
> > > > Acked-by: Conor Dooley <[email protected]>
> > > > ---
> > > > .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
> > > > drivers/pci/controller/plda/pcie-plda.h | 3 +
> > > > 2 files changed, 68 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > b/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > index b3df373a2141..beaf5c27da84 100644
> > > > --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
> > > > .irq_unmask = mc_unmask_event_irq, };
> > > >
> > > Hi Thomas
> > > I think this patch code it is easy to review. If you busy, Could you
> > > let other IRQ maintainer review? Thanks.
> > >
> > > Hi Lorenzo, Bjorn and Krzysztof
> >
> > Hi Minda,
> >
> > This patchset seems to have broken threading (lore, mailman). I have seen other
> > folks on IRC mentioning that too.
> >
> > I am not sure if that requires re-sending, but let's wait for others to comment.
> >
> > Cheers,
> > david
> >
> Do you mean the auto test error in linux-riscv?
> I can see that. But In v14 resend version, There is no error. Version 15 just add
> a new patch. Other no change. It is very strange.
> If not this error, I will waiting others comment.
V15 is wrongly threaded:
- Patch 2 has no In-Reply-To / In-Reply-To headers
- Patch 3 to 13 reference patch 2 instead of the cover letter
- Patch 14 has no In-Reply-To / In-Reply-To headers
- Patch 15 references patch 14 instead of the cover letter
- Patch 16 has no In-Reply-To / In-Reply-To headers
- Patch 17 to 23 reference patch 17 instead of the cover letter
Said otherwise, the patches appears as (sorry for the long lines):
[PATCH v15 00/23] Refactoring Microchip PCIe driver and add StarFive PCIe
└─>[PATCH v15 01/23] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties
[PATCH v15 02/23] PCI: microchip: Move pcie-microchip-host.c to plda directory
├─>[PATCH v15 03/23] PCI: microchip: Move PLDA IP register macros to pcie-plda.h
├─>[PATCH v15 04/23] PCI: microchip: Add bridge_addr field to struct mc_pcie
├─>[PATCH v15 05/23] PCI: microchip: Rename two PCIe data structures
├─>[PATCH v15 06/23] PCI: microchip: Move PCIe host data structures to plda-pcie.h
├─>[PATCH v15 07/23] PCI: microchip: Rename two setup functions
├─>[PATCH v15 08/23] PCI: microchip: Change the argument of plda_pcie_setup_iomems()
├─>[PATCH v15 09/23] PCI: microchip: Move setup functions to pcie-plda-host.c
├─>[PATCH v15 10/23] PCI: microchip: Rename interrupt related functions
├─>[PATCH v15 11/23] PCI: microchip: Add num_events field to struct plda_pcie_rp
├─>[PATCH v15 12/23] PCI: microchip: Add request_event_irq() callback function
└─>[PATCH v15 13/23] PCI: microchip: Add INTx and MSI event num to struct plda_event
[PATCH v15 14/23] PCI: microchip: Add get_events() callback and add PLDA get_event()
└─>[PATCH v15 15/23] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip
[PATCH v15 16/23] PCI: microchip: Move IRQ functions to pcie-plda-host.c
├─>[PATCH v15 17/23] PCI: plda: Add event bitmap field to struct plda_pcie_rp
├─>[PATCH v15 18/23] PCI: plda: Add host init/deinit and map bus functions
├─>[PATCH v15 19/23] dt-bindings: PCI: Add StarFive JH7110 PCIe controller
├─>[PATCH v15 20/23] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value
├─>[PATCH v15 21/23] PCI: starfive: Add JH7110 PCIe controller
├─>[PATCH v15 22/23] PCI: starfive: Offload the NVMe timeout workaround to host drivers.
└─>[PATCH v15 23/23] riscv: dts: starfive: add PCIe dts configuration for JH7110
I *think* it is the reason why some tools are not able to consider all
the patches as a single patchset.
Regards
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://aurel32.net
>
> Hi,
>
> On 2024-02-21 10:10, Minda Chen wrote:
> >
> >
> > >
> > > On Tue, Feb 20, 2024 at 1:02 PM Minda Chen
> > > <[email protected]>
> > > wrote:
> > > >
> > > >
> > > > >
> > > > > As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
> > > > > plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an
> > > > > interrupt controller.
> > > > >
> > > > > Microchip PolarFire PCIE event IRQs includes PLDA interrupts and
> > > > > Polarfire their own interrupts. The interrupt irqchip ops
> > > > > includes ack/mask/unmask interrupt ops, which will write correct
> registers.
> > > > > Microchip Polarfire PCIe additional interrupts require to write
> > > > > Polarfire SoC self-defined registers. So Microchip PCIe event
> > > > > irqchip ops can
> > > not be re-used.
> > > > >
> > > > > To support PLDA its own event IRQ process, implements PLDA
> > > > > irqchip ops and add event irqchip field to struct pcie_plda_rp.
> > > > >
> > > > > Signed-off-by: Minda Chen <[email protected]>
> > > > > Acked-by: Conor Dooley <[email protected]>
> > > > > ---
> > > > > .../pci/controller/plda/pcie-microchip-host.c | 66
> ++++++++++++++++++-
> > > > > drivers/pci/controller/plda/pcie-plda.h | 3 +
> > > > > 2 files changed, 68 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > > b/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > > index b3df373a2141..beaf5c27da84 100644
> > > > > --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > > +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> > > > > @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
> > > > > .irq_unmask = mc_unmask_event_irq, };
> > > > >
> > > > Hi Thomas
> > > > I think this patch code it is easy to review. If you busy, Could
> > > > you let other IRQ maintainer review? Thanks.
> > > >
> > > > Hi Lorenzo, Bjorn and Krzysztof
> > >
> > > Hi Minda,
> > >
> > > This patchset seems to have broken threading (lore, mailman). I have
> > > seen other folks on IRC mentioning that too.
> > >
> > > I am not sure if that requires re-sending, but let's wait for others to
> comment.
> > >
> > > Cheers,
> > > david
> > >
> > Do you mean the auto test error in linux-riscv?
> > I can see that. But In v14 resend version, There is no error. Version
> > 15 just add a new patch. Other no change. It is very strange.
> > If not this error, I will waiting others comment.
>
> V15 is wrongly threaded:
> - Patch 2 has no In-Reply-To / In-Reply-To headers
> - Patch 3 to 13 reference patch 2 instead of the cover letter
> - Patch 14 has no In-Reply-To / In-Reply-To headers
> - Patch 15 references patch 14 instead of the cover letter
> - Patch 16 has no In-Reply-To / In-Reply-To headers
> - Patch 17 to 23 reference patch 17 instead of the cover letter
>
> Said otherwise, the patches appears as (sorry for the long lines):
>
> [PATCH v15 00/23] Refactoring Microchip PCIe driver and add StarFive PCIe
> └─>[PATCH v15 01/23] dt-bindings: PCI: Add PLDA XpressRICH PCIe host
> common properties [PATCH v15 02/23] PCI: microchip: Move
> pcie-microchip-host.c to plda directory ├─>[PATCH v15 03/23] PCI: microchip:
> Move PLDA IP register macros to pcie-plda.h ├─>[PATCH v15 04/23] PCI:
> microchip: Add bridge_addr field to struct mc_pcie ├─>[PATCH v15 05/23] PCI:
> microchip: Rename two PCIe data structures ├─>[PATCH v15 06/23] PCI:
> microchip: Move PCIe host data structures to plda-pcie.h ├─>[PATCH v15 07/23]
> PCI: microchip: Rename two setup functions ├─>[PATCH v15 08/23] PCI:
> microchip: Change the argument of plda_pcie_setup_iomems() ├─>[PATCH v15
> 09/23] PCI: microchip: Move setup functions to pcie-plda-host.c ├─>[PATCH v15
> 10/23] PCI: microchip: Rename interrupt related functions ├─>[PATCH v15
> 11/23] PCI: microchip: Add num_events field to struct plda_pcie_rp ├─>[PATCH
> v15 12/23] PCI: microchip: Add request_event_irq() callback function
> └─>[PATCH v15 13/23] PCI: microchip: Add INTx and MSI event num to struct
> plda_event [PATCH v15 14/23] PCI: microchip: Add get_events() callback and
> add PLDA get_event() └─>[PATCH v15 15/23] PCI: microchip: Add event irqchip
> field to host port and add PLDA irqchip [PATCH v15 16/23] PCI: microchip: Move
> IRQ functions to pcie-plda-host.c ├─>[PATCH v15 17/23] PCI: plda: Add event
> bitmap field to struct plda_pcie_rp ├─>[PATCH v15 18/23] PCI: plda: Add host
> init/deinit and map bus functions ├─>[PATCH v15 19/23] dt-bindings: PCI: Add
> StarFive JH7110 PCIe controller ├─>[PATCH v15 20/23] PCI: Add
> PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value ├─>[PATCH v15
> 21/23] PCI: starfive: Add JH7110 PCIe controller ├─>[PATCH v15 22/23] PCI:
> starfive: Offload the NVMe timeout workaround to host drivers.
> └─>[PATCH v15 23/23] riscv: dts: starfive: add PCIe dts configuration for
> JH7110
>
> I *think* it is the reason why some tools are not able to consider all the patches
> as a single patchset.
>
> Regards
> Aurelien
>
> --
> Aurelien Jarno GPG: 4096R/1DDD8C9B
> [email protected] http://aurel32.net
I know what the reason is . I have sent the patches with different e-mails receivers.
I am sorry about it . I will resend this today.