Update the existing overlay which configures PCIE0 instance of PCIe on
J721E-EVM in Endpoint mode of operation, in order to configure PCIE1
instance of PCIe as well in Endpoint mode of operation. Hence, change the
name of the overlay to reflect its updated functionality.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
Hello,
This patch is based on linux-next tagged next-20240220.
Regards,
Siddharth.
arch/arm64/boot/dts/ti/Makefile | 8 ++---
....dtso => k3-j721e-evm-pcie0-pcie1-ep.dtso} | 30 +++++++++++++++++--
2 files changed, 32 insertions(+), 6 deletions(-)
rename arch/arm64/boot/dts/ti/{k3-j721e-evm-pcie0-ep.dtso => k3-j721e-evm-pcie0-pcie1-ep.dtso} (60%)
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index d601c52ab181..c7c9508e3980 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -75,7 +75,7 @@ k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-e
dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
-dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo
@@ -126,8 +126,8 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
-k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
- k3-j721e-evm-pcie0-ep.dtbo
+k3-j721e-evm-pcie0-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
+ k3-j721e-evm-pcie0-pcie1-ep.dtbo
k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -147,7 +147,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
k3-am68-sk-base-board-csi2-dual-imx219-dtbs \
k3-am69-sk-csi2-dual-imx219-dtbs \
- k3-j721e-evm-pcie0-ep.dtb \
+ k3-j721e-evm-pcie0-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219-dtbs \
k3-j721s2-evm-pcie1-ep.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-pcie1-ep.dtso
similarity index 60%
rename from arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
rename to arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-pcie1-ep.dtso
index 4062709d6579..5eaf304e3102 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-pcie1-ep.dtso
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
- * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
- * J7 common processor board.
+ * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration
+ * with the J7 common processor board.
*
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
*
@@ -24,6 +24,10 @@ &pcie0_rc {
status = "disabled";
};
+&pcie1_rc {
+ status = "disabled";
+};
+
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
@@ -50,4 +54,26 @@ pcie0_ep: pcie-ep@2900000 {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
};
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 1>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ };
};
--
2.34.1
On 2/20/24 4:50 AM, Siddharth Vadapalli wrote:
> Update the existing overlay which configures PCIE0 instance of PCIe on
> J721E-EVM in Endpoint mode of operation, in order to configure PCIE1
> instance of PCIe as well in Endpoint mode of operation. Hence, change the
> name of the overlay to reflect its updated functionality.
>
What if I only want PCIe0 to be in EP mode? Why not make a separate
DTBO for PCIe1, that way I can have one in EP and the other in RC,
and mix and match as needed.
Andrew
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
>
> Hello,
>
> This patch is based on linux-next tagged next-20240220.
>
> Regards,
> Siddharth.
>
> arch/arm64/boot/dts/ti/Makefile | 8 ++---
> ....dtso => k3-j721e-evm-pcie0-pcie1-ep.dtso} | 30 +++++++++++++++++--
> 2 files changed, 32 insertions(+), 6 deletions(-)
> rename arch/arm64/boot/dts/ti/{k3-j721e-evm-pcie0-ep.dtso => k3-j721e-evm-pcie0-pcie1-ep.dtso} (60%)
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index d601c52ab181..c7c9508e3980 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -75,7 +75,7 @@ k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-e
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
> -dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
> +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-pcie1-ep.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo
>
> @@ -126,8 +126,8 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \
> k3-j721e-sk-csi2-dual-imx219.dtbo
> k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
> k3-j721e-sk-csi2-dual-imx219.dtbo
> -k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
> - k3-j721e-evm-pcie0-ep.dtbo
> +k3-j721e-evm-pcie0-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
> + k3-j721e-evm-pcie0-pcie1-ep.dtbo
> k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
> k3-j721e-sk-csi2-dual-imx219.dtbo
> k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
> @@ -147,7 +147,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
> k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
> k3-am68-sk-base-board-csi2-dual-imx219-dtbs \
> k3-am69-sk-csi2-dual-imx219-dtbs \
> - k3-j721e-evm-pcie0-ep.dtb \
> + k3-j721e-evm-pcie0-pcie1-ep.dtb \
> k3-j721e-sk-csi2-dual-imx219-dtbs \
> k3-j721s2-evm-pcie1-ep.dtb
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-pcie1-ep.dtso
> similarity index 60%
> rename from arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
> rename to arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-pcie1-ep.dtso
> index 4062709d6579..5eaf304e3102 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-pcie1-ep.dtso
> @@ -1,7 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only OR MIT
> /**
> - * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
> - * J7 common processor board.
> + * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration
> + * with the J7 common processor board.
> *
> * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
> *
> @@ -24,6 +24,10 @@ &pcie0_rc {
> status = "disabled";
> };
>
> +&pcie1_rc {
> + status = "disabled";
> +};
> +
> &cbass_main {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -50,4 +54,26 @@ pcie0_ep: pcie-ep@2900000 {
> phys = <&serdes0_pcie_link>;
> phy-names = "pcie-phy";
> };
> +
> + pcie1_ep: pcie-ep@2910000 {
> + compatible = "ti,j721e-pcie-ep";
> + reg = <0x00 0x02910000 0x00 0x1000>,
> + <0x00 0x02917000 0x00 0x400>,
> + <0x00 0x0d800000 0x00 0x00800000>,
> + <0x00 0x18000000 0x00 0x08000000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
> + max-link-speed = <3>;
> + num-lanes = <2>;
> + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 240 1>;
> + clock-names = "fck";
> + max-functions = /bits/ 8 <6>;
> + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
> + dma-coherent;
> + phys = <&serdes1_pcie_link>;
> + phy-names = "pcie-phy";
> + };
> };
On Wed, Feb 21, 2024 at 10:53:14AM -0600, Andrew Davis wrote:
> On 2/20/24 4:50 AM, Siddharth Vadapalli wrote:
> > Update the existing overlay which configures PCIE0 instance of PCIe on
> > J721E-EVM in Endpoint mode of operation, in order to configure PCIE1
> > instance of PCIe as well in Endpoint mode of operation. Hence, change the
> > name of the overlay to reflect its updated functionality.
> >
>
> What if I only want PCIe0 to be in EP mode? Why not make a separate
> DTBO for PCIe1, that way I can have one in EP and the other in RC,
> and mix and match as needed.
Thank you for reviewing the patch. I had planned to create a different
overlay initially but felt that I would be asked to combine it with the
existing PCIe0 overlay.. I will create a separate overlay since that
seems to be acceptable and post the v2 patch.
Regards,
Siddharth.