The Beacon board has an LVDS display that cannot get a proper clock rate
from Video_PLL if the DSI is operational due to the way the clock divides
the pixel clocks from video_pll. To make the LVDS work, the LVDS needs
to use an alternative clock.
Because the clock rated needed for the LDB driving the LVDS display
isn't divisible by the clock rate needed by SAI3, move SAI3 to use
Audio_PLL1, and reconfigure the CODEC to use a 12MHz fixed clock.
Because these clocks are no longer in sync with each other, the sound
generated as the wrong pitch, so reconfigure the SAI3 to be the master
since the CODEC can internally compensate when fed a fixed clock
reference, even if it is not an even multiple of the desired rate.
This now leaves AUDIO_PLL2 completely free for the LDB without
compromising the audio sound from the codec.
Signed-off-by: Adam Ford <[email protected]>
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
index a08057410bde..1f827ef38e36 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
@@ -211,20 +211,20 @@ sound-wm8962 {
simple-audio-card,cpu {
sound-dai = <&sai3>;
+ frame-master;
+ bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
- frame-master;
- bitclock-master;
};
};
};
&audio_blk_ctrl {
- assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>;
- assigned-clock-rates = <393216000>, <135475200>;
+ assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>;
+ assigned-clock-rates = <393216000>;
};
&ecspi2 {
@@ -370,8 +370,8 @@ wm8962: audio-codec@1a {
pinctrl-0 = <&pinctrl_wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <22576000>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ assigned-clock-rates = <12000000>;
DCVDD-supply = <®_audio>;
DBVDD-supply = <®_audio>;
AVDD-supply = <®_audio>;
@@ -499,10 +499,9 @@ &pcie_phy {
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
- <&clk IMX8MP_AUDIO_PLL2> ;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <12288000>, <361267200>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
--
2.43.0
Beacon has an LVDS display that can connect to one of the
LVDS ports on the baseboard. The display requires a 30MHz
clock to display properly, and the LDB needs to run at 7x that.
With the audio CODEC now moved to the AUDIO_PLL1, the AUDIO_PLL2
is now available to source the LDB at 210MHz and the DISP_PIX2.
Signed-off-by: Adam Ford <[email protected]>
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
index 1f827ef38e36..731ee2667060 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
@@ -19,6 +19,26 @@ aliases {
ethernet1 = &fec;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 100000 0>;
+ power-supply = <®_lcd1_reset>;
+ status = "okay";
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <80>;
+ };
+
chosen {
stdout-path = &uart2;
};
@@ -135,6 +155,38 @@ led-3 {
};
};
+ lvds-1 {
+ compatible = "panel-lvds";
+ power-supply = <®_lcd1>;
+ width-mm = <223>;
+ height-mm = <125>;
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ /* 800x480@60Hz */
+ clock-frequency = <30000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hsync-len = <48>;
+ hfront-porch = <40>;
+ hback-porch = <40>;
+ vfront-porch = <13>;
+ vback-porch = <29>;
+ vsync-len = <1>;
+ hsync-active = <1>;
+ vsync-active = <3>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+
reg_audio: regulator-wm8962 {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
@@ -144,6 +196,25 @@ reg_audio: regulator-wm8962 {
enable-active-high;
};
+ reg_lcd1_reset: regulator-lcd1-reset {
+ compatible = "regulator-fixed";
+ regulator-name = "LVDS-1 reset";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416_3 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_lcd1>;
+ };
+
+ reg_lcd1: regulator-lcd1 {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds-1 power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416_3 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@@ -457,6 +528,38 @@ &lcdif1 {
status = "okay";
};
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_AUDIO_PLL2_OUT>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
+ assigned-clock-rates = <210000000>, <210000000>;
+ status = "okay";
+
+ ports {
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&panel1_in>;
+ };
+ };
+ };
+};
+
+&media_blk_ctrl {
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+ <&clk IMX8MP_CLK_MEDIA_APB>,
+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+ <&clk IMX8MP_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_VIDEO_PLL1_OUT>,
+ <&clk IMX8MP_AUDIO_PLL2_OUT>;
+ assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <1039500000>;
+};
+
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
@@ -496,6 +599,12 @@ &pcie_phy {
status = "okay";
};
+&pwm2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -596,6 +705,13 @@ &usdhc2 {
};
&iomuxc {
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x116
+ >;
+ };
+
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
--
2.43.0
Hi Adam,
On 24-02-29, Adam Ford wrote:
> Beacon has an LVDS display that can connect to one of the
> LVDS ports on the baseboard. The display requires a 30MHz
> clock to display properly, and the LDB needs to run at 7x that.
> With the audio CODEC now moved to the AUDIO_PLL1, the AUDIO_PLL2
> is now available to source the LDB at 210MHz and the DISP_PIX2.
>
> Signed-off-by: Adam Ford <[email protected]>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
> index 1f827ef38e36..731ee2667060 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
> @@ -19,6 +19,26 @@ aliases {
> ethernet1 = &fec;
> };
>
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm2 0 100000 0>;
> + power-supply = <®_lcd1_reset>;
> + status = "okay";
status is not required here.
> +
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100>;
Are you aware of: 'num-interpolated-steps' to avoid such arrays?
> + default-brightness-level = <80>;
> + };
> +
> chosen {
> stdout-path = &uart2;
> };
> @@ -135,6 +155,38 @@ led-3 {
> };
> };
>
> + lvds-1 {
> + compatible = "panel-lvds";
> + power-supply = <®_lcd1>;
> + width-mm = <223>;
> + height-mm = <125>;
> + backlight = <&backlight>;
> + data-mapping = "vesa-24";
> +
> + panel-timing {
> + /* 800x480@60Hz */
> + clock-frequency = <30000000>;
> + hactive = <800>;
> + vactive = <480>;
> + hsync-len = <48>;
> + hfront-porch = <40>;
> + hback-porch = <40>;
> + vfront-porch = <13>;
> + vback-porch = <29>;
> + vsync-len = <1>;
> + hsync-active = <1>;
> + vsync-active = <3>;
> + de-active = <1>;
> + pixelclk-active = <0>;
> + };
I would like to have a proper panel-simple.c entry but that's just my
POV of adding panels.
> +
> + port {
> + panel1_in: endpoint {
> + remote-endpoint = <&ldb_lvds_ch1>;
> + };
> + };
> + };
> +
> reg_audio: regulator-wm8962 {
> compatible = "regulator-fixed";
> regulator-name = "3v3_aud";
> @@ -144,6 +196,25 @@ reg_audio: regulator-wm8962 {
> enable-active-high;
> };
>
> + reg_lcd1_reset: regulator-lcd1-reset {
> + compatible = "regulator-fixed";
> + regulator-name = "LVDS-1 reset";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&pca6416_3 13 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <®_lcd1>;
> + };
This reset "regulator" seems more like a workaround, why don't you use
the reset-gpios property from "panel-lvds"?
Regards,
Marco
> +
> + reg_lcd1: regulator-lcd1 {
> + compatible = "regulator-fixed";
> + regulator-name = "lvds-1 power";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&pca6416_3 14 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> reg_usdhc2_vmmc: regulator-usdhc2 {
> compatible = "regulator-fixed";
> regulator-name = "VSD_3V3";
> @@ -457,6 +528,38 @@ &lcdif1 {
> status = "okay";
> };
>
> +&lcdif2 {
> + status = "okay";
> +};
> +
> +&lvds_bridge {
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_AUDIO_PLL2_OUT>;
> + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
> + assigned-clock-rates = <210000000>, <210000000>;
> + status = "okay";
> +
> + ports {
> + port@2 {
> + ldb_lvds_ch1: endpoint {
> + remote-endpoint = <&panel1_in>;
> + };
> + };
> + };
> +};
> +
> +&media_blk_ctrl {
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
> + <&clk IMX8MP_CLK_MEDIA_APB>,
> + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> + <&clk IMX8MP_VIDEO_PLL1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> + <&clk IMX8MP_SYS_PLL1_800M>,
> + <&clk IMX8MP_VIDEO_PLL1_OUT>,
> + <&clk IMX8MP_AUDIO_PLL2_OUT>;
> + assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <1039500000>;
> +};
> +
> &micfil {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pdm>;
> @@ -496,6 +599,12 @@ &pcie_phy {
> status = "okay";
> };
>
> +&pwm2 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> +};
> +
> &sai3 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_sai3>;
> @@ -596,6 +705,13 @@ &usdhc2 {
> };
>
> &iomuxc {
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x116
> + >;
> + };
> +
> pinctrl_ecspi2: ecspi2grp {
> fsl,pins = <
> MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
> --
> 2.43.0
>
>
>
On Thu, 29 Feb 2024 17:35:54 -0600, Adam Ford wrote:
> The Beacon board has an LVDS display that cannot get a proper clock rate
> from Video_PLL if the DSI is operational due to the way the clock divides
> the pixel clocks from video_pll. To make the LVDS work, the LVDS needs
> to use an alternative clock.
>
> Because the clock rated needed for the LDB driving the LVDS display
> isn't divisible by the clock rate needed by SAI3, move SAI3 to use
> Audio_PLL1, and reconfigure the CODEC to use a 12MHz fixed clock.
>
> Because these clocks are no longer in sync with each other, the sound
> generated as the wrong pitch, so reconfigure the SAI3 to be the master
> since the CODEC can internally compensate when fed a fixed clock
> reference, even if it is not an even multiple of the desired rate.
>
> This now leaves AUDIO_PLL2 completely free for the LDB without
> compromising the audio sound from the codec.
>
> Signed-off-by: Adam Ford <[email protected]>
>
My bot found new DT warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y freescale/imx8mp-beacon-kit.dtb' for [email protected]:
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: panel-timing:vsync-active:0:0: 3 is not one of [0, 1]
from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: compatible:0: 'panel-lvds' is not one of ['admatec,9904379', 'auo,b101ew05', 'chunghwa,claa070wp03xg', 'edt,etml0700z9ndha', 'hannstar,hsd101pww2', 'hydis,hv070wx2-1e0', 'tbs,a711-panel']
from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: compatible: ['panel-lvds'] is too short
from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: Unevaluated properties are not allowed ('backlight', 'compatible', 'height-mm', 'panel-timing', 'port', 'power-supply', 'width-mm' were unexpected)
from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#