This is the second attempt to sunset sun4m and sun4d.
See [1] for the inital attempt.
The sun4m and sun4d parts of the kernel have seen no real interest
for several years now. Last time a few people surfaced, but it was
either due to a personal project or for nostalgic reasons.
It is time to let go and drop the parts of sparc32 that in reality
are not in use.
LEON from Frontgrade Gaisler is the only real user of sparc32,
and this patchset reduces sparc32 to what is required by LEON.
The defconfig is first adapted to the one used by Gaisler.
Then the patches removes sun4m and sun4d specific
implementations such as small drivers, SMP support, IRQ suppor etc.
Removing sun4m and sun4d support allowed removal of the run time
patching of the code as well as a lot of assembler code.
The result is a much cleaner assembler code that is easier to
understand and thus maintain and extend.
Changes in v2:
- Rebased on top of Andreas' for-next branch
- Collected ack's
- Added patch to remove cpuid patching (Andreas)
- Run-time testing using qemu (Andreas, Mark Cave-Ayland)
Sam
[1]: https://lore.kernel.org/all/[email protected]/
---
Sam Ravnborg (28):
sparc32: Update defconfig to LEON SMP
sparc32: Drop sun4m/sun4d support from head_32.S
sparc32: Drop floppy support
sparc32: Drop sun4m specific led driver
sparc32: Drop sun specific power management drivers
sparc32: Drop auxio support
sparc32: Drop run-time patching of ipi trap
sparc32: Drop patching of interrupt vector
sparc32: Drop sun4m/sun4d specific irq handling
sparc32: Drop sun4d/sun4m smp support
sparc32: Drop pcic support
sparc32: Drop mbus support
sparc32: Drop unused function __get_{phys,iospace}
sparc32: Drop unused mmu models
sparc32: Drop check for sparc_model
sparc32: Drop use of sparc_config
sparc32: Drop run-time cpuid patching
sparc32: Drop run-time patching of ASI instructions
sparc32: Drop support for 7 register windows
sparc32: Drop additional sun4d bits
sparc32: Drop unused prom ranges support
sparc32: Drop unused sbus iommu support
sparc32: Drop sun4m irq support
sparc32: Drop unused trampoline code
sparc32: Drop config SPARC_LEON
sparc32: Drop sbus support
sbus: char: Drop now unused uctrl driver
fbdev/p9100: Drop now unused driver p9100
arch/sparc/Kconfig | 54 +--
arch/sparc/configs/sparc32_defconfig | 170 +++----
arch/sparc/include/asm/asmmacro.h | 22 -
arch/sparc/include/asm/auxio_32.h | 73 +--
arch/sparc/include/asm/cpu_type.h | 18 -
arch/sparc/include/asm/elf_32.h | 2 -
arch/sparc/include/asm/fb.h | 8 +-
arch/sparc/include/asm/floppy.h | 2 -
arch/sparc/include/asm/floppy_32.h | 393 ----------------
arch/sparc/include/asm/io-unit.h | 59 ---
arch/sparc/include/asm/io_32.h | 83 ----
arch/sparc/include/asm/iommu.h | 2 -
arch/sparc/include/asm/iommu_32.h | 122 -----
arch/sparc/include/asm/irq_32.h | 2 -
arch/sparc/include/asm/mbus.h | 97 ----
arch/sparc/include/asm/mxcc.h | 138 ------
arch/sparc/include/asm/obio.h | 226 ---------
arch/sparc/include/asm/oplib_32.h | 11 -
arch/sparc/include/asm/pcic.h | 130 ------
arch/sparc/include/asm/pgtable_32.h | 24 -
arch/sparc/include/asm/pgtsrmmu.h | 33 +-
arch/sparc/include/asm/ross.h | 192 --------
arch/sparc/include/asm/sbi.h | 116 -----
arch/sparc/include/asm/sections.h | 3 -
arch/sparc/include/asm/setup.h | 12 -
arch/sparc/include/asm/swift.h | 107 -----
arch/sparc/include/asm/switch_to_32.h | 1 -
arch/sparc/include/asm/timer_32.h | 1 +
arch/sparc/include/asm/tsunami.h | 65 ---
arch/sparc/include/asm/turbosparc.h | 126 -----
arch/sparc/include/asm/viking.h | 255 -----------
arch/sparc/include/asm/winmacro.h | 12 -
arch/sparc/kernel/Makefile | 8 +-
arch/sparc/kernel/apc.c | 196 --------
arch/sparc/kernel/auxio_32.c | 139 ------
arch/sparc/kernel/cpu.c | 1 -
arch/sparc/kernel/devices.c | 10 +-
arch/sparc/kernel/entry.S | 426 +----------------
arch/sparc/kernel/etrap_32.S | 50 +-
arch/sparc/kernel/head_32.S | 255 +----------
arch/sparc/kernel/ioport.c | 55 +--
arch/sparc/kernel/irq.h | 84 +---
arch/sparc/kernel/irq_32.c | 133 +-----
arch/sparc/kernel/kernel.h | 53 +--
arch/sparc/kernel/led.c | 146 ------
arch/sparc/kernel/leon_kernel.c | 53 +--
arch/sparc/kernel/leon_pmc.c | 16 +-
arch/sparc/kernel/leon_smp.c | 3 -
arch/sparc/kernel/of_device_32.c | 18 +-
arch/sparc/kernel/pcic.c | 840 ----------------------------------
arch/sparc/kernel/pmc.c | 100 ----
arch/sparc/kernel/process_32.c | 10 -
arch/sparc/kernel/rtrap_32.S | 73 ++-
arch/sparc/kernel/setup_32.c | 109 -----
arch/sparc/kernel/smp_32.c | 102 +----
arch/sparc/kernel/sun4d_irq.c | 519 ---------------------
arch/sparc/kernel/sun4d_smp.c | 415 -----------------
arch/sparc/kernel/sun4m_irq.c | 478 -------------------
arch/sparc/kernel/sun4m_smp.c | 275 -----------
arch/sparc/kernel/time_32.c | 68 +--
arch/sparc/kernel/trampoline_32.S | 127 +----
arch/sparc/kernel/ttable_32.S | 9 +-
arch/sparc/kernel/vmlinux.lds.S | 5 -
arch/sparc/kernel/wof.S | 61 +--
arch/sparc/kernel/wuf.S | 41 +-
arch/sparc/mm/Makefile | 4 +-
arch/sparc/mm/hypersparc.S | 414 -----------------
arch/sparc/mm/io-unit.c | 286 ------------
arch/sparc/mm/iommu.c | 455 ------------------
arch/sparc/mm/mm_32.h | 4 -
arch/sparc/mm/srmmu.c | 836 +--------------------------------
arch/sparc/mm/srmmu_access.S | 83 ----
arch/sparc/mm/swift.S | 256 -----------
arch/sparc/mm/tsunami.S | 132 ------
arch/sparc/mm/viking.S | 284 ------------
arch/sparc/prom/Makefile | 1 -
arch/sparc/prom/init_32.c | 2 -
arch/sparc/prom/misc_32.c | 2 -
arch/sparc/prom/ranges.c | 114 -----
drivers/sbus/char/Kconfig | 8 -
drivers/sbus/char/Makefile | 1 -
drivers/sbus/char/uctrl.c | 434 ------------------
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-hcd.c | 4 +-
drivers/usb/host/uhci-hcd.c | 2 +-
drivers/video/fbdev/Kconfig | 10 +-
drivers/video/fbdev/Makefile | 1 -
drivers/video/fbdev/p9100.c | 372 ---------------
sound/sparc/Kconfig | 1 +
89 files changed, 316 insertions(+), 10829 deletions(-)
---
base-commit: 84b76d05828a1909e20d0f66553b876b801f98c8
change-id: 20240309-sunset-3437be64cd5f
Best regards,
--
Sam Ravnborg <[email protected]>
From: Sam Ravnborg <[email protected]>
Remove the most obvious parts of sun4* support from head_32.S.
Use a single print if a sun4* machine is detected thus restricting
boots to LEON machines.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/kernel/head_32.S | 190 +++-----------------------------------------
1 file changed, 9 insertions(+), 181 deletions(-)
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S
index 964c61b5cd03..03dc232dd235 100644
--- a/arch/sparc/kernel/head_32.S
+++ b/arch/sparc/kernel/head_32.S
@@ -45,11 +45,7 @@ cputypvar:
.align 4
notsup:
- .asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
- .align 4
-
-sun4e_notsup:
- .asciz "Sparc-Linux sun4e support does not exist\n\n"
+ .asciz "This kernel only supports LEON SPARC V8\n\n"
.align 4
/* The trap-table - located in the __HEAD section */
@@ -215,114 +211,10 @@ not_a_sun4:
be leon_remap /* It is a LEON - jump */
nop
- /* Sanity-check, is MMU enabled */
- lda [%g0] ASI_M_MMUREGS, %g1
- andcc %g1, 1, %g0
- be halt_notsup
- nop
-
- /* Check for a viking (TI) module. */
- cmp %g3, PSR_IMPL_TI
- bne srmmu_not_viking
- nop
-
- /* Figure out what kind of viking we are on.
- * We need to know if we have to play with the
- * AC bit and disable traps or not.
- */
-
- /* I've only seen MicroSparc's on SparcClassics with this
- * bit set.
- */
- set 0x800, %g2
- lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg
- and %g2, %g3, %g3
- subcc %g3, 0x0, %g0
- bnz srmmu_not_viking ! is in mbus mode
- nop
-
- rd %psr, %g3 ! DO NOT TOUCH %g3
- andn %g3, PSR_ET, %g2
- wr %g2, 0x0, %psr
- WRITE_PAUSE
-
- /* Get context table pointer, then convert to
- * a physical address, which is 36 bits.
- */
- set AC_M_CTPR, %g4
- lda [%g4] ASI_M_MMUREGS, %g4
- sll %g4, 0x4, %g4 ! We use this below
- ! DO NOT TOUCH %g4
-
- /* Set the AC bit in the Viking's MMU control reg. */
- lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
- set 0x8000, %g6 ! AC bit mask
- or %g5, %g6, %g6 ! Or it in...
- sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes...
-
- /* Grrr, why does it seem like every other load/store
- * on the sun4m is in some ASI space...
- * Fine with me, let's get the pointer to the level 1
- * page table directory and fetch its entry.
- */
- lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
- srl %o1, 0x4, %o1 ! Clear low 4 bits
- sll %o1, 0x8, %o1 ! Make physical
-
- /* Ok, pull in the PTD. */
- lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd
-
- /* Calculate to KERNBASE entry. */
- add %o1, KERNBASE >> (PGDIR_SHIFT - 2), %o3
-
- /* Poke the entry into the calculated address. */
- sta %o2, [%o3] ASI_M_BYPASS
-
- /* I don't get it Sun, if you engineered all these
- * boot loaders and the PROM (thank you for the debugging
- * features btw) why did you not have them load kernel
- * images up in high address space, since this is necessary
- * for ABI compliance anyways? Does this low-mapping provide
- * enhanced interoperability?
- *
- * "The PROM is the computer."
- */
-
- /* Ok, restore the MMU control register we saved in %g5 */
- sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
-
- /* Turn traps back on. We saved it in %g3 earlier. */
- wr %g3, 0x0, %psr ! tick tock, tick tock
-
- /* Now we burn precious CPU cycles due to bad engineering. */
- WRITE_PAUSE
-
- /* Wow, all that just to move a 32-bit value from one
- * place to another... Jump to high memory.
- */
- b go_to_highmem
+ /* Not LEON - halt */
+ ba halt_notsup
nop
-srmmu_not_viking:
- /* This works on viking's in Mbus mode and all
- * other MBUS modules. It is virtually the same as
- * the above madness sans turning traps off and flipping
- * the AC bit.
- */
- set AC_M_CTPR, %g1
- lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr
- sll %g1, 0x4, %g1 ! make physical addr
- lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
- srl %g1, 0x4, %g1
- sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
-
- lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
- add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3
- sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
- b go_to_highmem
- nop ! wheee....
-
-
leon_remap:
/* Sanity-check, is MMU enabled */
lda [%g0] ASI_LEON_MMUREGS, %g1
@@ -343,8 +235,6 @@ leon_remap:
lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3
sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
- b go_to_highmem
- nop ! wheee....
/* Now do a non-relative jump so that PC is in high-memory */
go_to_highmem:
@@ -413,13 +303,13 @@ execute_in_high_mem:
ldub [%o2 + 0x4], %l1
cmp %l1, 'm'
- be sun4m_init
+ be no_sun4_here ! sun4m
cmp %l1, 's'
- be sun4m_init
+ be no_sun4_here ! sun4m
cmp %l1, 'd'
- be sun4d_init
+ be no_sun4_here ! sun4d
cmp %l1, 'e'
- be no_sun4e_here ! Could be a sun4e.
+ be no_sun4_here ! Could be a sun4e.
nop
b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
nop
@@ -441,68 +331,6 @@ leon_init:
/* Update boot_cpu_id only on boot cpu */
stub %g1, [%g2 + %lo(boot_cpu_id)]
- ba continue_boot
- nop
-
-/* CPUID in bootbus can be found at PA 0xff0140000 */
-#define SUN4D_BOOTBUS_CPUID 0xf0140000
-
-sun4d_init:
- /* Need to patch call to handler_irq */
- set patch_handler_irq, %g4
- set sun4d_handler_irq, %g5
- sethi %hi(0x40000000), %g3 ! call
- sub %g5, %g4, %g5
- srl %g5, 2, %g5
- or %g5, %g3, %g5
- st %g5, [%g4]
-
-#ifdef CONFIG_SMP
- /* Get our CPU id out of bootbus */
- set SUN4D_BOOTBUS_CPUID, %g3
- lduba [%g3] ASI_M_CTL, %g3
- and %g3, 0xf8, %g3
- srl %g3, 3, %g4
- sta %g4, [%g0] ASI_M_VIKING_TMP1
- sethi %hi(boot_cpu_id), %g5
- stb %g4, [%g5 + %lo(boot_cpu_id)]
-#endif
-
- /* Fall through to sun4m_init */
-
-sun4m_init:
-/* Ok, the PROM could have done funny things and apple cider could still
- * be sitting in the fault status/address registers. Read them all to
- * clear them so we don't get magic faults later on.
- */
-/* This sucks, apparently this makes Vikings call prom panic, will fix later */
-2:
- rd %psr, %o1
- srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU
-
- subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC
- be continue_boot
- nop
-
- set AC_M_SFSR, %o0
- lda [%o0] ASI_M_MMUREGS, %g0
- set AC_M_SFAR, %o0
- lda [%o0] ASI_M_MMUREGS, %g0
-
- /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
- subcc %o1, 0, %g0
- be continue_boot
- nop
-
- set AC_M_AFSR, %o0
- lda [%o0] ASI_M_MMUREGS, %g0
- set AC_M_AFAR, %o0
- lda [%o0] ASI_M_MMUREGS, %g0
- nop
-
-
-continue_boot:
-
/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
* show-time!
*/
@@ -670,9 +498,9 @@ continue_boot:
call halt_me
nop
-no_sun4e_here:
+no_sun4_here:
ld [%g7 + 0x68], %o1
- set sun4e_notsup, %o0
+ set notsup, %o0
call %o1
nop
b halt_me
--
2.34.1
From: Sam Ravnborg <[email protected]>
LEON do not have floppy support so we can drop it
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/Kconfig | 2 +-
arch/sparc/include/asm/floppy.h | 2 -
arch/sparc/include/asm/floppy_32.h | 393 -------------------------------------
arch/sparc/include/asm/setup.h | 12 --
arch/sparc/kernel/entry.S | 137 -------------
arch/sparc/kernel/irq.h | 3 -
arch/sparc/kernel/irq_32.c | 93 ---------
arch/sparc/kernel/kernel.h | 2 -
8 files changed, 1 insertion(+), 643 deletions(-)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index d08a5662ea60..278452f22f75 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -189,7 +189,7 @@ config GENERIC_CALIBRATE_DELAY
config ARCH_MAY_HAVE_PC_FDC
bool
- default y
+ default y if SPARC64
config EMULATED_CMPXCHG
bool
diff --git a/arch/sparc/include/asm/floppy.h b/arch/sparc/include/asm/floppy.h
index 4b315802e635..c89f719a18e9 100644
--- a/arch/sparc/include/asm/floppy.h
+++ b/arch/sparc/include/asm/floppy.h
@@ -3,7 +3,5 @@
#define ___ASM_SPARC_FLOPPY_H
#if defined(__sparc__) && defined(__arch64__)
#include <asm/floppy_64.h>
-#else
-#include <asm/floppy_32.h>
#endif
#endif
diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h
deleted file mode 100644
index 836f6575aa1d..000000000000
--- a/arch/sparc/include/asm/floppy_32.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* asm/floppy.h: Sparc specific parts of the Floppy driver.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef __ASM_SPARC_FLOPPY_H
-#define __ASM_SPARC_FLOPPY_H
-
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/pgtable.h>
-
-#include <asm/idprom.h>
-#include <asm/oplib.h>
-#include <asm/auxio.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/irq.h>
-
-/* We don't need no stinkin' I/O port allocation crap. */
-#undef release_region
-#undef request_region
-#define release_region(X, Y) do { } while(0)
-#define request_region(X, Y, Z) (1)
-
-/* References:
- * 1) Netbsd Sun floppy driver.
- * 2) NCR 82077 controller manual
- * 3) Intel 82077 controller manual
- */
-struct sun_flpy_controller {
- volatile unsigned char status_82072; /* Main Status reg. */
-#define dcr_82072 status_82072 /* Digital Control reg. */
-#define status1_82077 status_82072 /* Auxiliary Status reg. 1 */
-
- volatile unsigned char data_82072; /* Data fifo. */
-#define status2_82077 data_82072 /* Auxiliary Status reg. 2 */
-
- volatile unsigned char dor_82077; /* Digital Output reg. */
- volatile unsigned char tapectl_82077; /* What the? Tape control reg? */
-
- volatile unsigned char status_82077; /* Main Status Register. */
-#define drs_82077 status_82077 /* Digital Rate Select reg. */
-
- volatile unsigned char data_82077; /* Data fifo. */
- volatile unsigned char ___unused;
- volatile unsigned char dir_82077; /* Digital Input reg. */
-#define dcr_82077 dir_82077 /* Config Control reg. */
-};
-
-/* You'll only ever find one controller on a SparcStation anyways. */
-static struct sun_flpy_controller *sun_fdc = NULL;
-
-struct sun_floppy_ops {
- unsigned char (*fd_inb)(int port);
- void (*fd_outb)(unsigned char value, int port);
-};
-
-static struct sun_floppy_ops sun_fdops;
-
-#define fd_inb(base, reg) sun_fdops.fd_inb(reg)
-#define fd_outb(value, base, reg) sun_fdops.fd_outb(value, reg)
-#define fd_enable_dma() sun_fd_enable_dma()
-#define fd_disable_dma() sun_fd_disable_dma()
-#define fd_request_dma() (0) /* nothing... */
-#define fd_free_dma() /* nothing... */
-#define fd_clear_dma_ff() /* nothing... */
-#define fd_set_dma_mode(mode) sun_fd_set_dma_mode(mode)
-#define fd_set_dma_addr(addr) sun_fd_set_dma_addr(addr)
-#define fd_set_dma_count(count) sun_fd_set_dma_count(count)
-#define fd_enable_irq() /* nothing... */
-#define fd_disable_irq() /* nothing... */
-#define fd_request_irq() sun_fd_request_irq()
-#define fd_free_irq() /* nothing... */
-#if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
-#define fd_dma_mem_alloc(size) ((unsigned long) vmalloc(size))
-#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
-#endif
-
-/* XXX This isn't really correct. XXX */
-#define get_dma_residue(x) (0)
-
-#define FLOPPY0_TYPE 4
-#define FLOPPY1_TYPE 0
-
-/* Super paranoid... */
-#undef HAVE_DISABLE_HLT
-
-/* Here is where we catch the floppy driver trying to initialize,
- * therefore this is where we call the PROM device tree probing
- * routine etc. on the Sparc.
- */
-#define FDC1 sun_floppy_init()
-
-#define N_FDC 1
-#define N_DRIVE 8
-
-/* No 64k boundary crossing problems on the Sparc. */
-#define CROSS_64KB(a,s) (0)
-
-/* Routines unique to each controller type on a Sun. */
-static void sun_set_dor(unsigned char value, int fdc_82077)
-{
- if (fdc_82077)
- sun_fdc->dor_82077 = value;
-}
-
-static unsigned char sun_read_dir(void)
-{
- return sun_fdc->dir_82077;
-}
-
-static unsigned char sun_82072_fd_inb(int port)
-{
- udelay(5);
- switch (port) {
- default:
- printk("floppy: Asked to read unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case FD_STATUS:
- return sun_fdc->status_82072 & ~STATUS_DMA;
- case FD_DATA:
- return sun_fdc->data_82072;
- case FD_DIR:
- return sun_read_dir();
- }
- panic("sun_82072_fd_inb: How did I get here?");
-}
-
-static void sun_82072_fd_outb(unsigned char value, int port)
-{
- udelay(5);
- switch (port) {
- default:
- printk("floppy: Asked to write to unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case FD_DOR:
- sun_set_dor(value, 0);
- break;
- case FD_DATA:
- sun_fdc->data_82072 = value;
- break;
- case FD_DCR:
- sun_fdc->dcr_82072 = value;
- break;
- case FD_DSR:
- sun_fdc->status_82072 = value;
- break;
- }
- return;
-}
-
-static unsigned char sun_82077_fd_inb(int port)
-{
- udelay(5);
- switch (port) {
- default:
- printk("floppy: Asked to read unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case FD_SRA:
- return sun_fdc->status1_82077;
- case FD_SRB:
- return sun_fdc->status2_82077;
- case FD_DOR:
- return sun_fdc->dor_82077;
- case FD_TDR:
- return sun_fdc->tapectl_82077;
- case FD_STATUS:
- return sun_fdc->status_82077 & ~STATUS_DMA;
- case FD_DATA:
- return sun_fdc->data_82077;
- case FD_DIR:
- return sun_read_dir();
- }
- panic("sun_82077_fd_inb: How did I get here?");
-}
-
-static void sun_82077_fd_outb(unsigned char value, int port)
-{
- udelay(5);
- switch (port) {
- default:
- printk("floppy: Asked to write to unknown port %d\n", port);
- panic("floppy: Port bolixed.");
- case FD_DOR:
- sun_set_dor(value, 1);
- break;
- case FD_DATA:
- sun_fdc->data_82077 = value;
- break;
- case FD_DCR:
- sun_fdc->dcr_82077 = value;
- break;
- case FD_DSR:
- sun_fdc->status_82077 = value;
- break;
- case FD_TDR:
- sun_fdc->tapectl_82077 = value;
- break;
- }
- return;
-}
-
-/* For pseudo-dma (Sun floppy drives have no real DMA available to
- * them so we must eat the data fifo bytes directly ourselves) we have
- * three state variables. doing_pdma tells our inline low-level
- * assembly floppy interrupt entry point whether it should sit and eat
- * bytes from the fifo or just transfer control up to the higher level
- * floppy interrupt c-code. I tried very hard but I could not get the
- * pseudo-dma to work in c-code without getting many overruns and
- * underruns. If non-zero, doing_pdma encodes the direction of
- * the transfer for debugging. 1=read 2=write
- */
-
-/* Common routines to all controller types on the Sparc. */
-static inline void virtual_dma_init(void)
-{
- /* nothing... */
-}
-
-static inline void sun_fd_disable_dma(void)
-{
- doing_pdma = 0;
- pdma_base = NULL;
-}
-
-static inline void sun_fd_set_dma_mode(int mode)
-{
- switch(mode) {
- case DMA_MODE_READ:
- doing_pdma = 1;
- break;
- case DMA_MODE_WRITE:
- doing_pdma = 2;
- break;
- default:
- printk("Unknown dma mode %d\n", mode);
- panic("floppy: Giving up...");
- }
-}
-
-static inline void sun_fd_set_dma_addr(char *buffer)
-{
- pdma_vaddr = buffer;
-}
-
-static inline void sun_fd_set_dma_count(int length)
-{
- pdma_size = length;
-}
-
-static inline void sun_fd_enable_dma(void)
-{
- pdma_base = pdma_vaddr;
- pdma_areasize = pdma_size;
-}
-
-int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler);
-
-static int sun_fd_request_irq(void)
-{
- static int once = 0;
-
- if (!once) {
- once = 1;
- return sparc_floppy_request_irq(FLOPPY_IRQ, floppy_interrupt);
- } else {
- return 0;
- }
-}
-
-static struct linux_prom_registers fd_regs[2];
-
-static int sun_floppy_init(void)
-{
- struct platform_device *op;
- struct device_node *dp;
- struct resource r;
- char state[128];
- phandle fd_node;
- phandle tnode;
- int num_regs;
-
- use_virtual_dma = 1;
-
- /* Forget it if we aren't on a machine that could possibly
- * ever have a floppy drive.
- */
- if (sparc_cpu_model != sun4m) {
- /* We certainly don't have a floppy controller. */
- goto no_sun_fdc;
- }
- /* Well, try to find one. */
- tnode = prom_getchild(prom_root_node);
- fd_node = prom_searchsiblings(tnode, "obio");
- if (fd_node != 0) {
- tnode = prom_getchild(fd_node);
- fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
- } else {
- fd_node = prom_searchsiblings(tnode, "fd");
- }
- if (fd_node == 0) {
- goto no_sun_fdc;
- }
-
- /* The sun4m lets us know if the controller is actually usable. */
- if (prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
- if(!strcmp(state, "disabled")) {
- goto no_sun_fdc;
- }
- }
- num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs));
- num_regs = (num_regs / sizeof(fd_regs[0]));
- prom_apply_obio_ranges(fd_regs, num_regs);
- memset(&r, 0, sizeof(r));
- r.flags = fd_regs[0].which_io;
- r.start = fd_regs[0].phys_addr;
- sun_fdc = of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
-
- /* Look up irq in platform_device.
- * We try "SUNW,fdtwo" and "fd"
- */
- op = NULL;
- for_each_node_by_name(dp, "SUNW,fdtwo") {
- op = of_find_device_by_node(dp);
- if (op)
- break;
- }
- if (!op) {
- for_each_node_by_name(dp, "fd") {
- op = of_find_device_by_node(dp);
- if (op)
- break;
- }
- }
- if (!op)
- goto no_sun_fdc;
-
- FLOPPY_IRQ = op->archdata.irqs[0];
-
- /* Last minute sanity check... */
- if (sun_fdc->status_82072 == 0xff) {
- sun_fdc = NULL;
- goto no_sun_fdc;
- }
-
- sun_fdops.fd_inb = sun_82077_fd_inb;
- sun_fdops.fd_outb = sun_82077_fd_outb;
- fdc_status = &sun_fdc->status_82077;
-
- if (sun_fdc->dor_82077 == 0x80) {
- sun_fdc->dor_82077 = 0x02;
- if (sun_fdc->dor_82077 == 0x80) {
- sun_fdops.fd_inb = sun_82072_fd_inb;
- sun_fdops.fd_outb = sun_82072_fd_outb;
- fdc_status = &sun_fdc->status_82072;
- }
- }
-
- /* Success... */
- allowed_drive_mask = 0x01;
- return (int) sun_fdc;
-
-no_sun_fdc:
- return -1;
-}
-
-static int sparc_eject(void)
-{
- set_dor(0x00, 0xff, 0x90);
- udelay(500);
- set_dor(0x00, 0x6f, 0x00);
- udelay(500);
- return 0;
-}
-
-#define fd_eject(drive) sparc_eject()
-
-#define EXTRA_FLOPPY_PARAMS
-
-static DEFINE_SPINLOCK(dma_spin_lock);
-
-#define claim_dma_lock() \
-({ unsigned long flags; \
- spin_lock_irqsave(&dma_spin_lock, flags); \
- flags; \
-})
-
-#define release_dma_lock(__flags) \
- spin_unlock_irqrestore(&dma_spin_lock, __flags);
-
-#endif /* !(__ASM_SPARC_FLOPPY_H) */
diff --git a/arch/sparc/include/asm/setup.h b/arch/sparc/include/asm/setup.h
index 72205684e51e..b3c5d02eb1e7 100644
--- a/arch/sparc/include/asm/setup.h
+++ b/arch/sparc/include/asm/setup.h
@@ -25,18 +25,6 @@ static inline int con_is_present(void)
return serial_console ? 0 : 1;
}
-/* from irq_32.c */
-extern volatile unsigned char *fdc_status;
-extern char *pdma_vaddr;
-extern unsigned long pdma_size;
-extern volatile int doing_pdma;
-
-/* This is software state */
-extern char *pdma_base;
-extern unsigned long pdma_areasize;
-
-int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler);
-
/* setup_32.c */
extern unsigned long cmdline_memory_size;
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index a3fdee4cd6fa..c6a5cb949381 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -55,143 +55,6 @@ arch_kgdb_breakpoint:
.size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
#endif
-#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
- .align 4
- .globl floppy_hardint
-floppy_hardint:
- /*
- * This code cannot touch registers %l0 %l1 and %l2
- * because SAVE_ALL depends on their values. It depends
- * on %l3 also, but we regenerate it before a call.
- * Other registers are:
- * %l3 -- base address of fdc registers
- * %l4 -- pdma_vaddr
- * %l5 -- scratch for ld/st address
- * %l6 -- pdma_size
- * %l7 -- scratch [floppy byte, ld/st address, aux. data]
- */
-
- /* Do we have work to do? */
- sethi %hi(doing_pdma), %l7
- ld [%l7 + %lo(doing_pdma)], %l7
- cmp %l7, 0
- be floppy_dosoftint
- nop
-
- /* Load fdc register base */
- sethi %hi(fdc_status), %l3
- ld [%l3 + %lo(fdc_status)], %l3
-
- /* Setup register addresses */
- sethi %hi(pdma_vaddr), %l5 ! transfer buffer
- ld [%l5 + %lo(pdma_vaddr)], %l4
- sethi %hi(pdma_size), %l5 ! bytes to go
- ld [%l5 + %lo(pdma_size)], %l6
-next_byte:
- ldub [%l3], %l7
-
- andcc %l7, 0x80, %g0 ! Does fifo still have data
- bz floppy_fifo_emptied ! fifo has been emptied...
- andcc %l7, 0x20, %g0 ! in non-dma mode still?
- bz floppy_overrun ! nope, overrun
- andcc %l7, 0x40, %g0 ! 0=write 1=read
- bz floppy_write
- sub %l6, 0x1, %l6
-
- /* Ok, actually read this byte */
- ldub [%l3 + 1], %l7
- orcc %g0, %l6, %g0
- stb %l7, [%l4]
- bne next_byte
- add %l4, 0x1, %l4
-
- b floppy_tdone
- nop
-
-floppy_write:
- /* Ok, actually write this byte */
- ldub [%l4], %l7
- orcc %g0, %l6, %g0
- stb %l7, [%l3 + 1]
- bne next_byte
- add %l4, 0x1, %l4
-
- /* fall through... */
-floppy_tdone:
- sethi %hi(pdma_vaddr), %l5
- st %l4, [%l5 + %lo(pdma_vaddr)]
- sethi %hi(pdma_size), %l5
- st %l6, [%l5 + %lo(pdma_size)]
- /* Flip terminal count pin */
- set auxio_register, %l7
- ld [%l7], %l7
-
- ldub [%l7], %l5
-
- or %l5, 0xc2, %l5
- stb %l5, [%l7]
- andn %l5, 0x02, %l5
-
-2:
- /* Kill some time so the bits set */
- WRITE_PAUSE
- WRITE_PAUSE
-
- stb %l5, [%l7]
-
- /* Prevent recursion */
- sethi %hi(doing_pdma), %l7
- b floppy_dosoftint
- st %g0, [%l7 + %lo(doing_pdma)]
-
- /* We emptied the FIFO, but we haven't read everything
- * as of yet. Store the current transfer address and
- * bytes left to read so we can continue when the next
- * fast IRQ comes in.
- */
-floppy_fifo_emptied:
- sethi %hi(pdma_vaddr), %l5
- st %l4, [%l5 + %lo(pdma_vaddr)]
- sethi %hi(pdma_size), %l7
- st %l6, [%l7 + %lo(pdma_size)]
-
- /* Restore condition codes */
- wr %l0, 0x0, %psr
- WRITE_PAUSE
-
- jmp %l1
- rett %l2
-
-floppy_overrun:
- sethi %hi(pdma_vaddr), %l5
- st %l4, [%l5 + %lo(pdma_vaddr)]
- sethi %hi(pdma_size), %l5
- st %l6, [%l5 + %lo(pdma_size)]
- /* Prevent recursion */
- sethi %hi(doing_pdma), %l7
- st %g0, [%l7 + %lo(doing_pdma)]
-
- /* fall through... */
-floppy_dosoftint:
- rd %wim, %l3
- SAVE_ALL
-
- /* Set all IRQs off. */
- or %l0, PSR_PIL, %l4
- wr %l4, 0x0, %psr
- WRITE_PAUSE
- wr %l4, PSR_ET, %psr
- WRITE_PAUSE
-
- mov 11, %o0 ! floppy irq level (unused anyway)
- mov %g0, %o1 ! devid is not used in fast interrupts
- call sparc_floppy_irq
- add %sp, STACKFRAME_SZ, %o2 ! struct pt_regs *regs
-
- RESTORE_ALL
-
-#endif /* (CONFIG_BLK_DEV_FD) */
-
/* Bad trap handler */
.globl bad_trap_handler
bad_trap_handler:
diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h
index b02026ad6e34..0d9b740725b4 100644
--- a/arch/sparc/kernel/irq.h
+++ b/arch/sparc/kernel/irq.h
@@ -83,9 +83,6 @@ void handler_irq(unsigned int pil, struct pt_regs *regs);
unsigned long leon_get_irqmask(unsigned int irq);
-/* irq_32.c */
-void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs);
-
/* sun4m_irq.c */
void sun4m_nmi(struct pt_regs *regs);
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index 8605dd710f3c..510184c3aa17 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -235,99 +235,6 @@ void handler_irq(unsigned int pil, struct pt_regs *regs)
set_irq_regs(old_regs);
}
-#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
-static unsigned int floppy_irq;
-
-int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler)
-{
- unsigned int cpu_irq;
- int err;
-
-
- err = request_irq(irq, irq_handler, 0, "floppy", NULL);
- if (err)
- return -1;
-
- /* Save for later use in floppy interrupt handler */
- floppy_irq = irq;
-
- cpu_irq = (irq & (NR_IRQS - 1));
-
- /* Dork with trap table if we get this far. */
-#define INSTANTIATE(table) \
- table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \
- table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \
- SPARC_BRANCH((unsigned long) floppy_hardint, \
- (unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\
- table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \
- table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;
-
- INSTANTIATE(sparc_ttable)
-
-#if defined CONFIG_SMP
- if (sparc_cpu_model != sparc_leon) {
- struct tt_entry *trap_table;
-
- trap_table = &trapbase_cpu1[0];
- INSTANTIATE(trap_table)
- trap_table = &trapbase_cpu2[0];
- INSTANTIATE(trap_table)
- trap_table = &trapbase_cpu3[0];
- INSTANTIATE(trap_table)
- }
-#endif
-#undef INSTANTIATE
- /*
- * XXX Correct thing whould be to flush only I- and D-cache lines
- * which contain the handler in question. But as of time of the
- * writing we have no CPU-neutral interface to fine-grained flushes.
- */
- flush_cache_all();
- return 0;
-}
-EXPORT_SYMBOL(sparc_floppy_request_irq);
-
-/*
- * These variables are used to access state from the assembler
- * interrupt handler, floppy_hardint, so we cannot put these in
- * the floppy driver image because that would not work in the
- * modular case.
- */
-volatile unsigned char *fdc_status;
-EXPORT_SYMBOL(fdc_status);
-
-char *pdma_vaddr;
-EXPORT_SYMBOL(pdma_vaddr);
-
-unsigned long pdma_size;
-EXPORT_SYMBOL(pdma_size);
-
-volatile int doing_pdma;
-EXPORT_SYMBOL(doing_pdma);
-
-char *pdma_base;
-EXPORT_SYMBOL(pdma_base);
-
-unsigned long pdma_areasize;
-EXPORT_SYMBOL(pdma_areasize);
-
-/* Use the generic irq support to call floppy_interrupt
- * which was setup using request_irq() in sparc_floppy_request_irq().
- * We only have one floppy interrupt so we do not need to check
- * for additional handlers being wired up by irq_link()
- */
-void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
-
- old_regs = set_irq_regs(regs);
- irq_enter();
- generic_handle_irq(floppy_irq);
- irq_exit();
- set_irq_regs(old_regs);
-}
-#endif
-
/* djhr
* This could probably be made indirect too and assigned in the CPU
* bits of the code. That would be much nicer I think and would also
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index a8fb7c0bf053..3a0d39caa42a 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -151,8 +151,6 @@ extern unsigned int real_irq_entry[];
extern unsigned int smp4d_ticker[];
extern unsigned int patchme_maybe_smp_msg[];
-void floppy_hardint(void);
-
/* trampoline_32.S */
extern unsigned long sun4m_cpu_startup;
extern unsigned long sun4d_cpu_startup;
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop the two sun specific apc and pmc drivers.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/Kconfig | 7 --
arch/sparc/kernel/Makefile | 1 -
arch/sparc/kernel/apc.c | 196 ---------------------------------------------
arch/sparc/kernel/pmc.c | 100 -----------------------
4 files changed, 304 deletions(-)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index df88ad5df470..23cdf1959991 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -320,13 +320,6 @@ config CMDLINE
NOTE: This option WILL override the PROM bootargs setting!
-config SUN_PM
- bool
- default y if SPARC32
- help
- Enable power management and CPU standby features on supported
- SPARC platforms.
-
config SERIAL_CONSOLE
bool
depends on SPARC32
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index d3a0e0ebcfe7..1a942546dd00 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -83,7 +83,6 @@ obj-$(CONFIG_SPARC32_SMP) += sun4m_smp.o sun4d_smp.o leon_smp.o
obj-$(CONFIG_SPARC64_SMP) += hvtramp.o
obj-y += auxio_$(BITS).o
-obj-$(CONFIG_SUN_PM) += apc.o pmc.o
obj-y += termios.o
diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c
deleted file mode 100644
index d44725d37e30..000000000000
--- a/arch/sparc/kernel/apc.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* apc - Driver implementation for power management functions
- * of Aurora Personality Chip (APC) on SPARCstation-4/5 and
- * derivatives.
- *
- * Copyright (c) 2002 Eric Brower ([email protected])
- */
-
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/miscdevice.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-
-#include <asm/io.h>
-#include <asm/oplib.h>
-#include <linux/uaccess.h>
-#include <asm/auxio.h>
-#include <asm/apc.h>
-#include <asm/processor.h>
-
-/* Debugging
- *
- * #define APC_DEBUG_LED
- */
-
-#define APC_MINOR MISC_DYNAMIC_MINOR
-#define APC_OBPNAME "power-management"
-#define APC_DEVNAME "apc"
-
-static u8 __iomem *regs;
-static int apc_no_idle = 0;
-
-#define apc_readb(offs) (sbus_readb(regs+offs))
-#define apc_writeb(val, offs) (sbus_writeb(val, regs+offs))
-
-/* Specify "apc=noidle" on the kernel command line to
- * disable APC CPU standby support. Certain prototype
- * systems (SPARCstation-Fox) do not play well with APC
- * CPU idle, so disable this if your system has APC and
- * crashes randomly.
- */
-static int __init apc_setup(char *str)
-{
- if(!strncmp(str, "noidle", strlen("noidle"))) {
- apc_no_idle = 1;
- return 1;
- }
- return 0;
-}
-__setup("apc=", apc_setup);
-
-/*
- * CPU idle callback function
- * See .../arch/sparc/kernel/process.c
- */
-static void apc_swift_idle(void)
-{
-#ifdef APC_DEBUG_LED
- set_auxio(0x00, AUXIO_LED);
-#endif
-
- apc_writeb(apc_readb(APC_IDLE_REG) | APC_IDLE_ON, APC_IDLE_REG);
-
-#ifdef APC_DEBUG_LED
- set_auxio(AUXIO_LED, 0x00);
-#endif
-}
-
-static inline void apc_free(struct platform_device *op)
-{
- of_iounmap(&op->resource[0], regs, resource_size(&op->resource[0]));
-}
-
-static int apc_open(struct inode *inode, struct file *f)
-{
- return 0;
-}
-
-static int apc_release(struct inode *inode, struct file *f)
-{
- return 0;
-}
-
-static long apc_ioctl(struct file *f, unsigned int cmd, unsigned long __arg)
-{
- __u8 inarg, __user *arg = (__u8 __user *) __arg;
-
- switch (cmd) {
- case APCIOCGFANCTL:
- if (put_user(apc_readb(APC_FANCTL_REG) & APC_REGMASK, arg))
- return -EFAULT;
- break;
-
- case APCIOCGCPWR:
- if (put_user(apc_readb(APC_CPOWER_REG) & APC_REGMASK, arg))
- return -EFAULT;
- break;
-
- case APCIOCGBPORT:
- if (put_user(apc_readb(APC_BPORT_REG) & APC_BPMASK, arg))
- return -EFAULT;
- break;
-
- case APCIOCSFANCTL:
- if (get_user(inarg, arg))
- return -EFAULT;
- apc_writeb(inarg & APC_REGMASK, APC_FANCTL_REG);
- break;
-
- case APCIOCSCPWR:
- if (get_user(inarg, arg))
- return -EFAULT;
- apc_writeb(inarg & APC_REGMASK, APC_CPOWER_REG);
- break;
-
- case APCIOCSBPORT:
- if (get_user(inarg, arg))
- return -EFAULT;
- apc_writeb(inarg & APC_BPMASK, APC_BPORT_REG);
- break;
-
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static const struct file_operations apc_fops = {
- .unlocked_ioctl = apc_ioctl,
- .open = apc_open,
- .release = apc_release,
- .llseek = noop_llseek,
-};
-
-static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops };
-
-static int apc_probe(struct platform_device *op)
-{
- int err;
-
- regs = of_ioremap(&op->resource[0], 0,
- resource_size(&op->resource[0]), APC_OBPNAME);
- if (!regs) {
- printk(KERN_ERR "%s: unable to map registers\n", APC_DEVNAME);
- return -ENODEV;
- }
-
- err = misc_register(&apc_miscdev);
- if (err) {
- printk(KERN_ERR "%s: unable to register device\n", APC_DEVNAME);
- apc_free(op);
- return -ENODEV;
- }
-
- /* Assign power management IDLE handler */
- if (!apc_no_idle)
- sparc_idle = apc_swift_idle;
-
- printk(KERN_INFO "%s: power management initialized%s\n",
- APC_DEVNAME, apc_no_idle ? " (CPU idle disabled)" : "");
-
- return 0;
-}
-
-static const struct of_device_id apc_match[] = {
- {
- .name = APC_OBPNAME,
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, apc_match);
-
-static struct platform_driver apc_driver = {
- .driver = {
- .name = "apc",
- .of_match_table = apc_match,
- },
- .probe = apc_probe,
-};
-
-static int __init apc_init(void)
-{
- return platform_driver_register(&apc_driver);
-}
-
-/* This driver is not critical to the boot process
- * and is easiest to ioremap when SBus is already
- * initialized, so we install ourselves thusly:
- */
-__initcall(apc_init);
diff --git a/arch/sparc/kernel/pmc.c b/arch/sparc/kernel/pmc.c
deleted file mode 100644
index 69a0206e56f0..000000000000
--- a/arch/sparc/kernel/pmc.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* pmc - Driver implementation for power management functions
- * of Power Management Controller (PMC) on SPARCstation-Voyager.
- *
- * Copyright (c) 2002 Eric Brower ([email protected])
- */
-
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-
-#include <asm/io.h>
-#include <asm/oplib.h>
-#include <linux/uaccess.h>
-#include <asm/auxio.h>
-#include <asm/processor.h>
-
-/* Debug
- *
- * #define PMC_DEBUG_LED
- * #define PMC_NO_IDLE
- */
-
-#define PMC_OBPNAME "SUNW,pmc"
-#define PMC_DEVNAME "pmc"
-
-#define PMC_IDLE_REG 0x00
-#define PMC_IDLE_ON 0x01
-
-static u8 __iomem *regs;
-
-#define pmc_readb(offs) (sbus_readb(regs+offs))
-#define pmc_writeb(val, offs) (sbus_writeb(val, regs+offs))
-
-/*
- * CPU idle callback function
- * See .../arch/sparc/kernel/process.c
- */
-static void pmc_swift_idle(void)
-{
-#ifdef PMC_DEBUG_LED
- set_auxio(0x00, AUXIO_LED);
-#endif
-
- pmc_writeb(pmc_readb(PMC_IDLE_REG) | PMC_IDLE_ON, PMC_IDLE_REG);
-
-#ifdef PMC_DEBUG_LED
- set_auxio(AUXIO_LED, 0x00);
-#endif
-}
-
-static int pmc_probe(struct platform_device *op)
-{
- regs = of_ioremap(&op->resource[0], 0,
- resource_size(&op->resource[0]), PMC_OBPNAME);
- if (!regs) {
- printk(KERN_ERR "%s: unable to map registers\n", PMC_DEVNAME);
- return -ENODEV;
- }
-
-#ifndef PMC_NO_IDLE
- /* Assign power management IDLE handler */
- sparc_idle = pmc_swift_idle;
-#endif
-
- printk(KERN_INFO "%s: power management initialized\n", PMC_DEVNAME);
- return 0;
-}
-
-static const struct of_device_id pmc_match[] = {
- {
- .name = PMC_OBPNAME,
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, pmc_match);
-
-static struct platform_driver pmc_driver = {
- .driver = {
- .name = "pmc",
- .of_match_table = pmc_match,
- },
- .probe = pmc_probe,
-};
-
-static int __init pmc_init(void)
-{
- return platform_driver_register(&pmc_driver);
-}
-
-/* This driver is not critical to the boot process
- * and is easiest to ioremap when SBus is already
- * initialized, so we install ourselves thusly:
- */
-__initcall(pmc_init);
--
2.34.1
From: Sam Ravnborg <[email protected]>
Not used and references stuff that will be dropped later.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/pgtable_32.h | 24 ------------------------
arch/sparc/include/asm/pgtsrmmu.h | 11 -----------
2 files changed, 35 deletions(-)
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index 9e85d57ac3f2..92b063531d5c 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -368,30 +368,6 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
return __pte(pte_val(pte) & ~SRMMU_SWP_EXCLUSIVE);
}
-static inline unsigned long
-__get_phys (unsigned long addr)
-{
- switch (sparc_cpu_model){
- case sun4m:
- case sun4d:
- return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
- default:
- return 0;
- }
-}
-
-static inline int
-__get_iospace (unsigned long addr)
-{
- switch (sparc_cpu_model){
- case sun4m:
- case sun4d:
- return (srmmu_get_pte (addr) >> 28);
- default:
- return -1;
- }
-}
-
/*
* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
* its high 4 bits. These macros/functions put it there or get it from there.
diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h
index 18e68d43f036..7cb5cbc83211 100644
--- a/arch/sparc/include/asm/pgtsrmmu.h
+++ b/arch/sparc/include/asm/pgtsrmmu.h
@@ -125,17 +125,6 @@ static inline void srmmu_flush_whole_tlb(void)
}
-static inline int
-srmmu_get_pte (unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
- "=r" (entry):
- "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
- return entry;
-}
-
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_PGTSRMMU_H) */
--
2.34.1
From: Sam Ravnborg <[email protected]>
There is no longer any need for the run-time patching of the ipi trap
with the removal of sun4m and sun4d. Remove the patching and drop the
ipi implementation for the two machines.
The patch includes removal of patching from pcic as this was needed to
fix the build. pcic will be removed in a later commit.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/kernel/entry.S | 70 ++-----------------------------------------
arch/sparc/kernel/kernel.h | 4 ---
arch/sparc/kernel/leon_smp.c | 3 --
arch/sparc/kernel/pcic.c | 11 -------
arch/sparc/kernel/sun4d_smp.c | 3 --
arch/sparc/kernel/ttable_32.S | 9 +++---
6 files changed, 7 insertions(+), 93 deletions(-)
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index c6a5cb949381..7cf148a996b9 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -174,32 +174,6 @@ maybe_smp4m_msg_check_resched:
maybe_smp4m_msg_out:
RESTORE_ALL
- .align 4
- .globl linux_trap_ipi15_sun4m
-linux_trap_ipi15_sun4m:
- SAVE_ALL
- sethi %hi(0x80000000), %o2
- GET_PROCESSOR4M_ID(o0)
- sethi %hi(sun4m_irq_percpu), %l5
- or %l5, %lo(sun4m_irq_percpu), %o5
- sll %o0, 2, %o0
- ld [%o5 + %o0], %o5
- ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
- andcc %o3, %o2, %g0
- be sun4m_nmi_error ! Must be an NMI async memory error
- st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000
- WRITE_PAUSE
- ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
- WRITE_PAUSE
- or %l0, PSR_PIL, %l4
- wr %l4, 0x0, %psr
- WRITE_PAUSE
- wr %l4, PSR_ET, %psr
- WRITE_PAUSE
- call smp4m_cross_call_irq
- nop
- b ret_trap_lockless_ipi
- clr %l6
.globl smp4d_ticker
/* SMP per-cpu ticker interrupts are handled specially. */
@@ -220,44 +194,6 @@ smp4d_ticker:
WRITE_PAUSE
RESTORE_ALL
- .align 4
- .globl linux_trap_ipi15_sun4d
-linux_trap_ipi15_sun4d:
- SAVE_ALL
- sethi %hi(CC_BASE), %o4
- sethi %hi(MXCC_ERR_ME|MXCC_ERR_PEW|MXCC_ERR_ASE|MXCC_ERR_PEE), %o2
- or %o4, (CC_EREG - CC_BASE), %o0
- ldda [%o0] ASI_M_MXCC, %o0
- andcc %o0, %o2, %g0
- bne 1f
- sethi %hi(BB_STAT2), %o2
- lduba [%o2] ASI_M_CTL, %o2
- andcc %o2, BB_STAT2_MASK, %g0
- bne 2f
- or %o4, (CC_ICLR - CC_BASE), %o0
- sethi %hi(1 << 15), %o1
- stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 15 in MXCC's ICLR */
- or %l0, PSR_PIL, %l4
- wr %l4, 0x0, %psr
- WRITE_PAUSE
- wr %l4, PSR_ET, %psr
- WRITE_PAUSE
- call smp4d_cross_call_irq
- nop
- b ret_trap_lockless_ipi
- clr %l6
-
-1: /* MXCC error */
-2: /* BB error */
- /* Disable PIL 15 */
- set CC_IMSK, %l4
- lduha [%l4] ASI_M_MXCC, %l5
- sethi %hi(1 << 15), %l7
- or %l5, %l7, %l5
- stha %l5, [%l4] ASI_M_MXCC
- /* FIXME */
-1: b,a 1b
-
.globl smpleon_ipi
.extern leon_ipi_interrupt
/* SMP per-cpu IPI interrupts are handled specially. */
@@ -618,11 +554,11 @@ sun4m_nmi_error:
#ifndef CONFIG_SMP
.align 4
- .globl linux_trap_ipi15_sun4m
-linux_trap_ipi15_sun4m:
+ .globl linux_trap_ipi15_leon
+linux_trap_ipi15_leon:
SAVE_ALL
- ba sun4m_nmi_error
+ ba sun4m_nmi_error
nop
#endif /* CONFIG_SMP */
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 64703be6c015..3ba842c6b6da 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -134,10 +134,6 @@ void leonsmp_ipi_interrupt(void);
void leon_cross_call_irq(void);
/* head_32.S */
-extern unsigned int t_nmi[];
-extern unsigned int linux_trap_ipi15_sun4d[];
-extern unsigned int linux_trap_ipi15_sun4m[];
-
extern struct tt_entry trapbase[];
extern struct tt_entry trapbase_cpu1[];
extern struct tt_entry trapbase_cpu2[];
diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c
index 1ee393abc463..7d5e423c186d 100644
--- a/arch/sparc/kernel/leon_smp.c
+++ b/arch/sparc/kernel/leon_smp.c
@@ -463,8 +463,5 @@ static const struct sparc32_ipi_ops leon_ipi_ops = {
void __init leon_init_smp(void)
{
- /* Patch ipi15 trap table */
- t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_leon - linux_trap_ipi15_sun4m);
-
sparc32_ipi_ops = &leon_ipi_ops;
}
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 25fe0a061732..d952bcbbc395 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -354,17 +354,6 @@ int __init pcic_probe(void)
prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
strcpy(pbm->prom_name, namebuf);
- {
- extern int pcic_nmi_trap_patch[4];
-
- t_nmi[0] = pcic_nmi_trap_patch[0];
- t_nmi[1] = pcic_nmi_trap_patch[1];
- t_nmi[2] = pcic_nmi_trap_patch[2];
- t_nmi[3] = pcic_nmi_trap_patch[3];
- swift_flush_dcache();
- pcic_regs = pcic->pcic_regs;
- }
-
prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
{
struct pcic_sn2list *p;
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 9a62a5cf3337..be5bcbee1af4 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -403,9 +403,6 @@ void __init sun4d_init_smp(void)
{
int i;
- /* Patch ipi15 trap table */
- t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
-
sparc32_ipi_ops = &sun4d_ipi_ops;
for (i = 0; i < NR_CPUS; i++) {
diff --git a/arch/sparc/kernel/ttable_32.S b/arch/sparc/kernel/ttable_32.S
index e79fd786fbbb..78bbf2548e1f 100644
--- a/arch/sparc/kernel/ttable_32.S
+++ b/arch/sparc/kernel/ttable_32.S
@@ -43,8 +43,7 @@ t_irq12:TRAP_ENTRY_INTERRUPT(12) /* IRQ Zilog serial chip */
t_irq13:TRAP_ENTRY_INTERRUPT(13) /* IRQ Audio Intr. */
t_irq14:TRAP_ENTRY_INTERRUPT(14) /* IRQ Timer #2 */
- .globl t_nmi
-t_nmi: TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+t_nmi: TRAP_ENTRY(0x1f, linux_trap_ipi15_leon)
t_racc: TRAP_ENTRY(0x20, do_reg_access) /* General Register Access Error */
t_iacce:BAD_TRAP(0x21) /* Instr Access Error */
@@ -146,7 +145,7 @@ trapbase_cpu1:
TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10)
TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12)
TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14)
- TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+ TRAP_ENTRY(0x1f, linux_trap_ipi15_leon)
TRAP_ENTRY(0x20, do_reg_access)
BAD_TRAP(0x21)
BAD_TRAP(0x22)
@@ -245,7 +244,7 @@ trapbase_cpu2:
TRAP_ENTRY_INTERRUPT(12)
TRAP_ENTRY_INTERRUPT(13)
TRAP_ENTRY_INTERRUPT(14)
- TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+ TRAP_ENTRY(0x1f, linux_trap_ipi15_leon)
TRAP_ENTRY(0x20, do_reg_access)
BAD_TRAP(0x21)
BAD_TRAP(0x22)
@@ -345,7 +344,7 @@ trapbase_cpu3:
TRAP_ENTRY_INTERRUPT(12)
TRAP_ENTRY_INTERRUPT(13)
TRAP_ENTRY_INTERRUPT(14)
- TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+ TRAP_ENTRY(0x1f, linux_trap_ipi15_leon)
TRAP_ENTRY(0x20, do_reg_access)
BAD_TRAP(0x21)
BAD_TRAP(0x22)
--
2.34.1
From: Sam Ravnborg <[email protected]>
auxio is not supported by LEON - so drop it.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/auxio_32.h | 73 +-------------------
arch/sparc/kernel/Makefile | 2 +-
arch/sparc/kernel/auxio_32.c | 139 --------------------------------------
arch/sparc/kernel/devices.c | 3 -
arch/sparc/kernel/kernel.h | 4 --
arch/sparc/kernel/process_32.c | 10 ---
arch/sparc/prom/misc_32.c | 2 -
7 files changed, 3 insertions(+), 230 deletions(-)
diff --git a/arch/sparc/include/asm/auxio_32.h b/arch/sparc/include/asm/auxio_32.h
index 852457c7a265..e2335ddd359d 100644
--- a/arch/sparc/include/asm/auxio_32.h
+++ b/arch/sparc/include/asm/auxio_32.h
@@ -1,43 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * auxio.h: Definitions and code for the Auxiliary I/O register.
+ * Dummy definitions for the Auxiliary I/O register.
*
* Copyright (C) 1995 David S. Miller ([email protected])
*/
#ifndef _SPARC_AUXIO_H
#define _SPARC_AUXIO_H
-#include <asm/vaddrs.h>
-
-/* This register is an unsigned char in IO space. It does two things.
- * First, it is used to control the front panel LED light on machines
- * that have it (good for testing entry points to trap handlers and irq's)
- * Secondly, it controls various floppy drive parameters.
- */
-#define AUXIO_ORMEIN 0xf0 /* All writes must set these bits. */
-#define AUXIO_ORMEIN4M 0xc0 /* sun4m - All writes must set these bits. */
-#define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */
-#define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */
-#define AUXIO_EDGE_ON 0x10 /* sun4m - On means Jumper block is in. */
-#define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */
-#define AUXIO_LINK_TEST 0x08 /* sun4m - On means TPE Carrier detect. */
-
-/* Set the following to one, then zero, after doing a pseudo DMA transfer. */
-#define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */
-
-/* Set the following to zero to eject the floppy. */
-#define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
-#define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */
-
-#ifndef __ASSEMBLY__
-
-/*
- * NOTE: these routines are implementation dependent--
- * understand the hardware you are querying!
- */
-void set_auxio(unsigned char bits_on, unsigned char bits_off);
-unsigned char get_auxio(void); /* .../asm/floppy.h */
-
/*
* The following routines are provided for driver-compatibility
* with sparc64 (primarily sunlance.c)
@@ -46,44 +15,6 @@ unsigned char get_auxio(void); /* .../asm/floppy.h */
#define AUXIO_LTE_ON 1
#define AUXIO_LTE_OFF 0
-/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
- *
- * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
- */
-#define auxio_set_lte(on) \
-do { \
- if(on) { \
- set_auxio(AUXIO_LINK_TEST, 0); \
- } else { \
- set_auxio(0, AUXIO_LINK_TEST); \
- } \
-} while (0)
-
-#define AUXIO_LED_ON 1
-#define AUXIO_LED_OFF 0
-
-/* auxio_set_led - Set system front panel LED
- *
- * on - AUXIO_LED_ON or AUXIO_LED_OFF
- */
-#define auxio_set_led(on) \
-do { \
- if(on) { \
- set_auxio(AUXIO_LED, 0); \
- } else { \
- set_auxio(0, AUXIO_LED); \
- } \
-} while (0)
-
-#endif /* !(__ASSEMBLY__) */
-
-
-/* AUXIO2 (Power Off Control) */
-extern volatile u8 __iomem *auxio_power_register;
-
-#define AUXIO_POWER_DETECT_FAILURE 32
-#define AUXIO_POWER_CLEAR_FAILURE 2
-#define AUXIO_POWER_OFF 1
-
+#define auxio_set_lte(on)
#endif /* !(_SPARC_AUXIO_H) */
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 1a942546dd00..b253b7e132ce 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -82,7 +82,7 @@ obj-$(CONFIG_SMP) += trampoline_$(BITS).o smp_$(BITS).o
obj-$(CONFIG_SPARC32_SMP) += sun4m_smp.o sun4d_smp.o leon_smp.o
obj-$(CONFIG_SPARC64_SMP) += hvtramp.o
-obj-y += auxio_$(BITS).o
+obj-$(CONFIG_SPARC64) += auxio_64.o
obj-y += termios.o
diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c
deleted file mode 100644
index 989860e890c4..000000000000
--- a/arch/sparc/kernel/auxio_32.c
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* auxio.c: Probing for the Sparc AUXIO register at boot time.
- *
- * Copyright (C) 1996 David S. Miller ([email protected])
- */
-
-#include <linux/stddef.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
-#include <linux/export.h>
-
-#include <asm/oplib.h>
-#include <asm/io.h>
-#include <asm/auxio.h>
-#include <asm/string.h> /* memset(), Linux has no bzero() */
-#include <asm/cpu_type.h>
-
-#include "kernel.h"
-
-/* Probe and map in the Auxiliary I/O register */
-
-/* auxio_register is not static because it is referenced
- * in entry.S::floppy_tdone
- */
-void __iomem *auxio_register = NULL;
-static DEFINE_SPINLOCK(auxio_lock);
-
-void __init auxio_probe(void)
-{
- phandle node, auxio_nd;
- struct linux_prom_registers auxregs[1];
- struct resource r;
-
- switch (sparc_cpu_model) {
- case sparc_leon:
- case sun4d:
- return;
- default:
- break;
- }
- node = prom_getchild(prom_root_node);
- auxio_nd = prom_searchsiblings(node, "auxiliary-io");
- if(!auxio_nd) {
- node = prom_searchsiblings(node, "obio");
- node = prom_getchild(node);
- auxio_nd = prom_searchsiblings(node, "auxio");
- if(!auxio_nd) {
-#ifdef CONFIG_PCI
- /* There may be auxio on Ebus */
- return;
-#else
- if(prom_searchsiblings(node, "leds")) {
- /* VME chassis sun4m machine, no auxio exists. */
- return;
- }
- prom_printf("Cannot find auxio node, cannot continue...\n");
- prom_halt();
-#endif
- }
- }
- if(prom_getproperty(auxio_nd, "reg", (char *) auxregs, sizeof(auxregs)) <= 0)
- return;
- prom_apply_obio_ranges(auxregs, 0x1);
- /* Map the register both read and write */
- r.flags = auxregs[0].which_io & 0xF;
- r.start = auxregs[0].phys_addr;
- r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1;
- auxio_register = of_ioremap(&r, 0, auxregs[0].reg_size, "auxio");
- /* Fix the address on sun4m. */
- if ((((unsigned long) auxregs[0].phys_addr) & 3) == 3)
- auxio_register += (3 - ((unsigned long)auxio_register & 3));
-
- set_auxio(AUXIO_LED, 0);
-}
-
-unsigned char get_auxio(void)
-{
- if(auxio_register)
- return sbus_readb(auxio_register);
- return 0;
-}
-EXPORT_SYMBOL(get_auxio);
-
-void set_auxio(unsigned char bits_on, unsigned char bits_off)
-{
- unsigned char regval;
- unsigned long flags;
- spin_lock_irqsave(&auxio_lock, flags);
- switch (sparc_cpu_model) {
- case sun4m:
- if(!auxio_register)
- break; /* VME chassis sun4m, no auxio. */
- regval = sbus_readb(auxio_register);
- sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M,
- auxio_register);
- break;
- case sun4d:
- break;
- default:
- panic("Can't set AUXIO register on this machine.");
- }
- spin_unlock_irqrestore(&auxio_lock, flags);
-}
-EXPORT_SYMBOL(set_auxio);
-
-/* sun4m power control register (AUXIO2) */
-
-volatile u8 __iomem *auxio_power_register = NULL;
-
-void __init auxio_power_probe(void)
-{
- struct linux_prom_registers regs;
- phandle node;
- struct resource r;
-
- /* Attempt to find the sun4m power control node. */
- node = prom_getchild(prom_root_node);
- node = prom_searchsiblings(node, "obio");
- node = prom_getchild(node);
- node = prom_searchsiblings(node, "power");
- if (node == 0 || (s32)node == -1)
- return;
-
- /* Map the power control register. */
- if (prom_getproperty(node, "reg", (char *)®s, sizeof(regs)) <= 0)
- return;
- prom_apply_obio_ranges(®s, 1);
- memset(&r, 0, sizeof(r));
- r.flags = regs.which_io & 0xF;
- r.start = regs.phys_addr;
- r.end = regs.phys_addr + regs.reg_size - 1;
- auxio_power_register =
- (u8 __iomem *)of_ioremap(&r, 0, regs.reg_size, "auxpower");
-
- /* Display a quick message on the console. */
- if (auxio_power_register)
- printk(KERN_INFO "Power off control detected.\n");
-}
diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c
index 23b6e50d4ada..b3c2d51b22c4 100644
--- a/arch/sparc/kernel/devices.c
+++ b/arch/sparc/kernel/devices.c
@@ -132,7 +132,4 @@ void __init device_scan(void)
0);
}
#endif /* !CONFIG_SMP */
-
- auxio_probe();
- auxio_power_probe();
}
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 3a0d39caa42a..64703be6c015 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -174,10 +174,6 @@ asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn);
/* windows.c */
void try_to_clear_window_buffer(struct pt_regs *regs, int who);
-/* auxio_32.c */
-void __init auxio_probe(void);
-void __init auxio_power_probe(void);
-
/* pcic.c */
extern void __iomem *pcic_regs;
void pcic_nmi(unsigned int pend, struct pt_regs *regs);
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index 9c7c662cb565..2e2836f314ca 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -27,7 +27,6 @@
#include <linux/slab.h>
#include <linux/cpu.h>
-#include <asm/auxio.h>
#include <asm/oplib.h>
#include <linux/uaccess.h>
#include <asm/page.h>
@@ -49,8 +48,6 @@ void (*sparc_idle)(void);
/*
* Power-off handler instantiation for pm.h compliance
- * This is done via auxio, but could be used as a fallback
- * handler when auxio is not present-- unused for now...
*/
void (*pm_power_off)(void) = machine_power_off;
EXPORT_SYMBOL(pm_power_off);
@@ -103,13 +100,6 @@ void machine_restart(char * cmd)
void machine_power_off(void)
{
- if (auxio_power_register &&
- (!of_node_is_type(of_console_device, "serial") || scons_pwroff)) {
- u8 power_register = sbus_readb(auxio_power_register);
- power_register |= AUXIO_POWER_OFF;
- sbus_writeb(power_register, auxio_power_register);
- }
-
machine_halt();
}
diff --git a/arch/sparc/prom/misc_32.c b/arch/sparc/prom/misc_32.c
index 625750924860..78dde6bfbf0f 100644
--- a/arch/sparc/prom/misc_32.c
+++ b/arch/sparc/prom/misc_32.c
@@ -13,7 +13,6 @@
#include <asm/openprom.h>
#include <asm/oplib.h>
-#include <asm/auxio.h>
extern void restore_current(void);
@@ -60,7 +59,6 @@ prom_cmdline(void)
(*(romvec->pv_abort))();
restore_current();
spin_unlock_irqrestore(&prom_lock, flags);
- set_auxio(AUXIO_LED, 0);
}
/* Drop into the prom, but completely terminate the program.
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop the sun4m specific handling and the patching that
takes place in sun4d and LEON.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/kernel/entry.S | 98 -----------------------------------------
arch/sparc/kernel/kernel.h | 1 -
arch/sparc/kernel/leon_kernel.c | 16 -------
arch/sparc/kernel/sun4d_irq.c | 25 -----------
4 files changed, 140 deletions(-)
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 7cf148a996b9..9bd3813b872d 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -79,15 +79,6 @@ bad_trap_handler:
real_irq_entry:
SAVE_ALL
-#ifdef CONFIG_SMP
- .globl patchme_maybe_smp_msg
-
- cmp %l7, 11
-patchme_maybe_smp_msg:
- bgu maybe_smp4m_msg
- nop
-#endif
-
real_irq_continue:
or %l0, PSR_PIL, %g2
wr %g2, 0x0, %psr
@@ -105,95 +96,6 @@ patch_handler_irq:
RESTORE_ALL
#ifdef CONFIG_SMP
- /* SMP per-cpu ticker interrupts are handled specially. */
-smp4m_ticker:
- bne real_irq_continue+4
- or %l0, PSR_PIL, %g2
- wr %g2, 0x0, %psr
- WRITE_PAUSE
- wr %g2, PSR_ET, %psr
- WRITE_PAUSE
- call smp4m_percpu_timer_interrupt
- add %sp, STACKFRAME_SZ, %o0
- wr %l0, PSR_ET, %psr
- WRITE_PAUSE
- RESTORE_ALL
-
-#define GET_PROCESSOR4M_ID(reg) \
- rd %tbr, %reg; \
- srl %reg, 12, %reg; \
- and %reg, 3, %reg;
-
- /* Here is where we check for possible SMP IPI passed to us
- * on some level other than 15 which is the NMI and only used
- * for cross calls. That has a separate entry point below.
- *
- * IPIs are sent on Level 12, 13 and 14. See IRQ_IPI_*.
- */
-maybe_smp4m_msg:
- GET_PROCESSOR4M_ID(o3)
- sethi %hi(sun4m_irq_percpu), %l5
- sll %o3, 2, %o3
- or %l5, %lo(sun4m_irq_percpu), %o5
- sethi %hi(0x70000000), %o2 ! Check all soft-IRQs
- ld [%o5 + %o3], %o1
- ld [%o1 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
- andcc %o3, %o2, %g0
- be,a smp4m_ticker
- cmp %l7, 14
- /* Soft-IRQ IPI */
- st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x70000000
- WRITE_PAUSE
- ld [%o1 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
- WRITE_PAUSE
- or %l0, PSR_PIL, %l4
- wr %l4, 0x0, %psr
- WRITE_PAUSE
- wr %l4, PSR_ET, %psr
- WRITE_PAUSE
- srl %o3, 28, %o2 ! shift for simpler checks below
-maybe_smp4m_msg_check_single:
- andcc %o2, 0x1, %g0
- beq,a maybe_smp4m_msg_check_mask
- andcc %o2, 0x2, %g0
- call smp_call_function_single_interrupt
- nop
- andcc %o2, 0x2, %g0
-maybe_smp4m_msg_check_mask:
- beq,a maybe_smp4m_msg_check_resched
- andcc %o2, 0x4, %g0
- call smp_call_function_interrupt
- nop
- andcc %o2, 0x4, %g0
-maybe_smp4m_msg_check_resched:
- /* rescheduling is done in RESTORE_ALL regardless, but incr stats */
- beq,a maybe_smp4m_msg_out
- nop
- call smp_resched_interrupt
- nop
-maybe_smp4m_msg_out:
- RESTORE_ALL
-
-
- .globl smp4d_ticker
- /* SMP per-cpu ticker interrupts are handled specially. */
-smp4d_ticker:
- SAVE_ALL
- or %l0, PSR_PIL, %g2
- sethi %hi(CC_ICLR), %o0
- sethi %hi(1 << 14), %o1
- or %o0, %lo(CC_ICLR), %o0
- stha %o1, [%o0] ASI_M_MXCC /* Clear PIL 14 in MXCC's ICLR */
- wr %g2, 0x0, %psr
- WRITE_PAUSE
- wr %g2, PSR_ET, %psr
- WRITE_PAUSE
- call smp4d_percpu_timer_interrupt
- add %sp, STACKFRAME_SZ, %o0
- wr %l0, PSR_ET, %psr
- WRITE_PAUSE
- RESTORE_ALL
-
.globl smpleon_ipi
.extern leon_ipi_interrupt
/* SMP per-cpu IPI interrupts are handled specially. */
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 3ba842c6b6da..6165e1b26df7 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -145,7 +145,6 @@ extern char cputypval[];
extern unsigned long lvl14_save[4];
extern unsigned int real_irq_entry[];
extern unsigned int smp4d_ticker[];
-extern unsigned int patchme_maybe_smp_msg[];
/* trampoline_32.S */
extern unsigned long sun4m_cpu_startup;
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index 4c61da491fee..ea04bad6a118 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -421,22 +421,6 @@ void __init leon_init_timers(void)
if (eirq != 0)
leon_eirq_setup(eirq);
-#ifdef CONFIG_SMP
- {
- unsigned long flags;
-
- /*
- * In SMP, sun4m adds a IPI handler to IRQ trap handler that
- * LEON never must take, sun4d and LEON overwrites the branch
- * with a NOP.
- */
- local_irq_save(flags);
- patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
- local_ops->cache_all();
- local_irq_restore(flags);
- }
-#endif
-
config = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config);
if (config & (1 << LEON3_GPTIMER_SEPIRQ))
leon3_gptimer_irq += leon3_gptimer_idx;
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
index 9a137c70e8d1..7140cff04b54 100644
--- a/arch/sparc/kernel/sun4d_irq.c
+++ b/arch/sparc/kernel/sun4d_irq.c
@@ -391,30 +391,6 @@ static unsigned int sun4d_build_timer_irq(unsigned int board,
}
-static void __init sun4d_fixup_trap_table(void)
-{
-#ifdef CONFIG_SMP
- unsigned long flags;
- struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
-
- /* Adjust so that we jump directly to smp4d_ticker */
- lvl14_save[2] += smp4d_ticker - real_irq_entry;
-
- /* For SMP we use the level 14 ticker, however the bootup code
- * has copied the firmware's level 14 vector into the boot cpu's
- * trap table, we must fix this now or we get squashed.
- */
- local_irq_save(flags);
- patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
- trap_table->inst_one = lvl14_save[0];
- trap_table->inst_two = lvl14_save[1];
- trap_table->inst_three = lvl14_save[2];
- trap_table->inst_four = lvl14_save[3];
- local_ops->cache_all();
- local_irq_restore(flags);
-#endif
-}
-
static void __init sun4d_init_timers(void)
{
struct device_node *dp;
@@ -478,7 +454,6 @@ static void __init sun4d_init_timers(void)
prom_halt();
}
sun4d_load_profile_irqs();
- sun4d_fixup_trap_table();
}
void __init sun4d_init_sbi_irq(void)
--
2.34.1
From: Sam Ravnborg <[email protected]>
Only used by older SPARC HW, not used by LEON.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/elf_32.h | 2 -
arch/sparc/include/asm/mbus.h | 97 -----------------------------------------
arch/sparc/kernel/cpu.c | 1 -
arch/sparc/kernel/setup_32.c | 1 -
arch/sparc/mm/iommu.c | 18 ++------
arch/sparc/mm/srmmu.c | 48 --------------------
6 files changed, 3 insertions(+), 164 deletions(-)
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
index 37a6016c9ccd..b2cca9be55c2 100644
--- a/arch/sparc/include/asm/elf_32.h
+++ b/arch/sparc/include/asm/elf_32.h
@@ -91,8 +91,6 @@ typedef struct {
unsigned int pr_q[64];
} elf_fpregset_t;
-#include <asm/mbus.h>
-
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
diff --git a/arch/sparc/include/asm/mbus.h b/arch/sparc/include/asm/mbus.h
deleted file mode 100644
index 8b6dbe701b9b..000000000000
--- a/arch/sparc/include/asm/mbus.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * mbus.h: Various defines for MBUS modules.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_MBUS_H
-#define _SPARC_MBUS_H
-
-#include <asm/ross.h> /* HyperSparc stuff */
-#include <asm/viking.h> /* Ugh, bug city... */
-
-enum mbus_module {
- HyperSparc = 0,
- Swift_ok = 4,
- Swift_bad_c = 5,
- Swift_lots_o_bugs = 6,
- Tsunami = 7,
- Viking_12 = 8,
- Viking_2x = 9,
- Viking_30 = 10,
- Viking_35 = 11,
- Viking_new = 12,
- TurboSparc = 13,
- SRMMU_INVAL_MOD = 14,
-};
-
-extern enum mbus_module srmmu_modtype;
-extern unsigned int viking_rev, swift_rev, cypress_rev;
-
-/* HW Mbus module bugs we have to deal with */
-#define HWBUG_COPYBACK_BROKEN 0x00000001
-#define HWBUG_ASIFLUSH_BROKEN 0x00000002
-#define HWBUG_VACFLUSH_BITROT 0x00000004
-#define HWBUG_KERN_ACCBROKEN 0x00000008
-#define HWBUG_KERN_CBITBROKEN 0x00000010
-#define HWBUG_MODIFIED_BITROT 0x00000020
-#define HWBUG_PC_BADFAULT_ADDR 0x00000040
-#define HWBUG_SUPERSCALAR_BAD 0x00000080
-#define HWBUG_PACINIT_BITROT 0x00000100
-
-/* First the module type values. To find out which you have, just load
- * the mmu control register from ASI_M_MMUREG alternate address space and
- * shift the value right 28 bits.
- */
-/* IMPL field means the company which produced the chip. */
-#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
-#define MBUS_LSI 0x3 /* LSI Logics */
-#define MBUS_ROSS 0x1 /* Ross is nice */
-#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
-
-/* Ross Module versions */
-#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
-#define ROSS_604_REV_F 0x1 /* revision f */
-#define ROSS_605 0xf /* revision a, a.1, and a.2 */
-#define ROSS_605_REV_B 0xe /* revision b */
-
-/* TI Viking Module versions */
-#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
-#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
-#define VIKING_REV_30 0x3 /* Version 3.0 */
-#define VIKING_REV_35 0x4 /* Version 3.5 */
-
-/* LSI Logics. */
-#define LSI_L64815 0x0
-
-/* Fujitsu */
-#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
-#define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
-
-/* For multiprocessor support we need to be able to obtain the CPU id and
- * the MBUS Module id.
- */
-
-/* The CPU ID is encoded in the trap base register, 20 bits to the left of
- * bit zero, with 2 bits being significant.
- */
-#define TBR_ID_SHIFT 20
-
-static inline int get_cpuid(void)
-{
- register int retval;
- __asm__ __volatile__("rd %%tbr, %0\n\t"
- "srl %0, %1, %0\n\t" :
- "=r" (retval) :
- "i" (TBR_ID_SHIFT));
- return (retval & 3);
-}
-
-static inline int get_modid(void)
-{
- return (get_cpuid() | 0x8);
-}
-
-
-#endif /* !(_SPARC_MBUS_H) */
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 79cd6ccfeac0..cca7de051593 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -19,7 +19,6 @@
#include <asm/page.h>
#include <asm/head.h>
#include <asm/psr.h>
-#include <asm/mbus.h>
#include <asm/cpudata.h>
#include "kernel.h"
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 704375c061e7..3c6c16fde8c3 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -41,7 +41,6 @@
#include <asm/page.h>
#include <asm/traps.h>
#include <asm/vaddrs.h>
-#include <asm/mbus.h>
#include <asm/idprom.h>
#include <asm/cpudata.h>
#include <asm/setup.h>
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index 5a5080db800f..832e5ff8b663 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -19,7 +19,6 @@
#include <asm/io.h>
#include <asm/mxcc.h>
-#include <asm/mbus.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/bitext.h>
@@ -117,13 +116,7 @@ static void __init sbus_iommu_init(struct platform_device *op)
prom_halt();
}
bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
- /* To be coherent on HyperSparc, the page color of DVMA
- * and physical addresses must match.
- */
- if (srmmu_modtype == HyperSparc)
- iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
- else
- iommu->usemap.num_colors = 1;
+ iommu->usemap.num_colors = 1;
printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
impl, vers, iommu->page_table,
@@ -445,11 +438,6 @@ static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
void __init ld_mmu_iommu(void)
{
- if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
- dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
- ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
- } else {
- dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
- ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
- }
+ dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
+ ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
}
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 04d9653890c5..3a7e10729a02 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -34,7 +34,6 @@
#include <asm/cache.h>
#include <asm/traps.h>
#include <asm/oplib.h>
-#include <asm/mbus.h>
#include <asm/page.h>
#include <asm/asi.h>
#include <asm/smp.h>
@@ -51,8 +50,6 @@
#include "mm_32.h"
-enum mbus_module srmmu_modtype;
-static unsigned int hwbug_bitmask;
int vac_cache_size;
EXPORT_SYMBOL(vac_cache_size);
int vac_line_size;
@@ -1117,7 +1114,6 @@ static const struct sparc32_cachetlb_ops hypersparc_ops = {
static void __init init_hypersparc(void)
{
srmmu_name = "ROSS HyperSparc";
- srmmu_modtype = HyperSparc;
init_vac_layout();
@@ -1176,45 +1172,6 @@ static void __init init_swift(void)
"=r" (swift_rev) :
"r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
srmmu_name = "Fujitsu Swift";
- switch (swift_rev) {
- case 0x11:
- case 0x20:
- case 0x23:
- case 0x30:
- srmmu_modtype = Swift_lots_o_bugs;
- hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
- /*
- * Gee george, I wonder why Sun is so hush hush about
- * this hardware bug... really braindamage stuff going
- * on here. However I think we can find a way to avoid
- * all of the workaround overhead under Linux. Basically,
- * any page fault can cause kernel pages to become user
- * accessible (the mmu gets confused and clears some of
- * the ACC bits in kernel ptes). Aha, sounds pretty
- * horrible eh? But wait, after extensive testing it appears
- * that if you use pgd_t level large kernel pte's (like the
- * 4MB pages on the Pentium) the bug does not get tripped
- * at all. This avoids almost all of the major overhead.
- * Welcome to a world where your vendor tells you to,
- * "apply this kernel patch" instead of "sorry for the
- * broken hardware, send it back and we'll give you
- * properly functioning parts"
- */
- break;
- case 0x25:
- case 0x31:
- srmmu_modtype = Swift_bad_c;
- hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
- /*
- * You see Sun allude to this hardware bug but never
- * admit things directly, they'll say things like,
- * "the Swift chip cache problems" or similar.
- */
- break;
- default:
- srmmu_modtype = Swift_ok;
- break;
- }
sparc32_cachetlb_ops = &swift_ops;
flush_page_for_dma_global = 0;
@@ -1367,7 +1324,6 @@ static const struct sparc32_cachetlb_ops turbosparc_ops = {
static void __init init_turbosparc(void)
{
srmmu_name = "Fujitsu TurboSparc";
- srmmu_modtype = TurboSparc;
sparc32_cachetlb_ops = &turbosparc_ops;
poke_srmmu = poke_turbosparc;
}
@@ -1406,7 +1362,6 @@ static void __init init_tsunami(void)
*/
srmmu_name = "TI Tsunami";
- srmmu_modtype = Tsunami;
sparc32_cachetlb_ops = &tsunami_ops;
poke_srmmu = poke_tsunami;
@@ -1546,9 +1501,6 @@ static void __init get_srmmu_type(void)
unsigned long mreg, psr;
unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
- srmmu_modtype = SRMMU_INVAL_MOD;
- hwbug_bitmask = 0;
-
mreg = srmmu_get_mmureg(); psr = get_psr();
mod_typ = (mreg & 0xf0000000) >> 28;
mod_rev = (mreg & 0x0f000000) >> 24;
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop the sun4m and sun4d smp support code.
The sparc32 kernel will not boot unless this is a LEON system,
so drop checks for other systems as they will not trigger.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/kernel/Makefile | 2 +-
arch/sparc/kernel/kernel.h | 18 --
arch/sparc/kernel/smp_32.c | 102 +----------
arch/sparc/kernel/sun4d_smp.c | 408 ------------------------------------------
arch/sparc/kernel/sun4m_smp.c | 275 ----------------------------
arch/sparc/mm/srmmu.c | 10 +-
6 files changed, 8 insertions(+), 807 deletions(-)
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index d3d21e58b4e6..bd31bdd0b13e 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -79,7 +79,7 @@ obj-$(CONFIG_SPARC_GRPCI2)+= leon_pci_grpci2.o
obj-$(CONFIG_SPARC_GRPCI1)+= leon_pci_grpci1.o
obj-$(CONFIG_SMP) += trampoline_$(BITS).o smp_$(BITS).o
-obj-$(CONFIG_SPARC32_SMP) += sun4m_smp.o sun4d_smp.o leon_smp.o
+obj-$(CONFIG_SPARC32_SMP) += leon_smp.o
obj-$(CONFIG_SPARC64_SMP) += hvtramp.o
obj-$(CONFIG_SPARC64) += auxio_64.o
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index c467b1425506..621fb7b6ec64 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -96,24 +96,6 @@ void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs);
void sun4m_unmask_profile_irq(void);
void sun4m_clear_profile_irq(int cpu);
-/* sun4m_smp.c */
-void sun4m_cpu_pre_starting(void *arg);
-void sun4m_cpu_pre_online(void *arg);
-void __init smp4m_boot_cpus(void);
-int smp4m_boot_one_cpu(int i, struct task_struct *idle);
-void __init smp4m_smp_done(void);
-void smp4m_cross_call_irq(void);
-void smp4m_percpu_timer_interrupt(struct pt_regs *regs);
-
-/* sun4d_smp.c */
-void sun4d_cpu_pre_starting(void *arg);
-void sun4d_cpu_pre_online(void *arg);
-void __init smp4d_boot_cpus(void);
-int smp4d_boot_one_cpu(int i, struct task_struct *idle);
-void __init smp4d_smp_done(void);
-void smp4d_cross_call_irq(void);
-void smp4d_percpu_timer_interrupt(struct pt_regs *regs);
-
/* leon_smp.c */
void leon_cpu_pre_starting(void *arg);
void leon_cpu_pre_online(void *arg);
diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c
index 87eaa7719fa2..42fb90577a82 100644
--- a/arch/sparc/kernel/smp_32.c
+++ b/arch/sparc/kernel/smp_32.c
@@ -87,29 +87,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
num, bogosum/(500000/HZ),
(bogosum/(5000/HZ))%100);
- switch(sparc_cpu_model) {
- case sun4m:
- smp4m_smp_done();
- break;
- case sun4d:
- smp4d_smp_done();
- break;
- case sparc_leon:
- leon_smp_done();
- break;
- case sun4e:
- printk("SUN4E\n");
- BUG();
- break;
- case sun4u:
- printk("SUN4U\n");
- BUG();
- break;
- default:
- printk("UNKNOWN!\n");
- BUG();
- break;
- }
+ leon_smp_done();
}
void cpu_panic(void)
@@ -191,29 +169,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
smp_store_cpu_info(boot_cpu_id);
- switch(sparc_cpu_model) {
- case sun4m:
- smp4m_boot_cpus();
- break;
- case sun4d:
- smp4d_boot_cpus();
- break;
- case sparc_leon:
- leon_boot_cpus();
- break;
- case sun4e:
- printk("SUN4E\n");
- BUG();
- break;
- case sun4u:
- printk("SUN4U\n");
- BUG();
- break;
- default:
- printk("UNKNOWN!\n");
- BUG();
- break;
- }
+ leon_boot_cpus();
}
/* Set this up early so that things like the scheduler can init
@@ -252,31 +208,7 @@ void __init smp_prepare_boot_cpu(void)
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
- int ret=0;
-
- switch(sparc_cpu_model) {
- case sun4m:
- ret = smp4m_boot_one_cpu(cpu, tidle);
- break;
- case sun4d:
- ret = smp4d_boot_one_cpu(cpu, tidle);
- break;
- case sparc_leon:
- ret = leon_boot_one_cpu(cpu, tidle);
- break;
- case sun4e:
- printk("SUN4E\n");
- BUG();
- break;
- case sun4u:
- printk("SUN4U\n");
- BUG();
- break;
- default:
- printk("UNKNOWN!\n");
- BUG();
- break;
- }
+ int ret = leon_boot_one_cpu(cpu, tidle);
if (!ret) {
cpumask_set_cpu(cpu, &smp_commenced_mask);
@@ -291,19 +223,7 @@ static void arch_cpu_pre_starting(void *arg)
local_ops->cache_all();
local_ops->tlb_all();
- switch(sparc_cpu_model) {
- case sun4m:
- sun4m_cpu_pre_starting(arg);
- break;
- case sun4d:
- sun4d_cpu_pre_starting(arg);
- break;
- case sparc_leon:
- leon_cpu_pre_starting(arg);
- break;
- default:
- BUG();
- }
+ leon_cpu_pre_starting(arg);
}
static void arch_cpu_pre_online(void *arg)
@@ -318,19 +238,7 @@ static void arch_cpu_pre_online(void *arg)
local_ops->cache_all();
local_ops->tlb_all();
- switch(sparc_cpu_model) {
- case sun4m:
- sun4m_cpu_pre_online(arg);
- break;
- case sun4d:
- sun4d_cpu_pre_online(arg);
- break;
- case sparc_leon:
- leon_cpu_pre_online(arg);
- break;
- default:
- BUG();
- }
+ leon_cpu_pre_online(arg);
}
static void sparc_start_secondary(void *arg)
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
deleted file mode 100644
index 7f49a8fa3e3a..000000000000
--- a/arch/sparc/kernel/sun4d_smp.c
+++ /dev/null
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Sparc SS1000/SC2000 SMP support.
- *
- * Copyright (C) 1998 Jakub Jelinek ([email protected])
- *
- * Based on sun4m's smp.c, which is:
- * Copyright (C) 1996 David S. Miller ([email protected])
- */
-
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/profile.h>
-#include <linux/delay.h>
-#include <linux/sched/mm.h>
-#include <linux/cpu.h>
-
-#include <asm/cacheflush.h>
-#include <asm/switch_to.h>
-#include <asm/tlbflush.h>
-#include <asm/timer.h>
-#include <asm/oplib.h>
-#include <asm/sbi.h>
-#include <asm/mmu.h>
-
-#include "kernel.h"
-#include "irq.h"
-
-#define IRQ_CROSS_CALL 15
-
-static volatile int smp_processors_ready;
-static int smp_highest_cpu;
-
-static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
-{
- __asm__ __volatile__("swap [%1], %0\n\t" :
- "=&r" (val), "=&r" (ptr) :
- "0" (val), "1" (ptr));
- return val;
-}
-
-static void smp4d_ipi_init(void);
-
-static unsigned char cpu_leds[32];
-
-static inline void show_leds(int cpuid)
-{
- cpuid &= 0x1e;
- __asm__ __volatile__ ("stba %0, [%1] %2" : :
- "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
- "r" (ECSR_BASE(cpuid) | BB_LEDS),
- "i" (ASI_M_CTL));
-}
-
-void sun4d_cpu_pre_starting(void *arg)
-{
- int cpuid = hard_smp_processor_id();
-
- /* Show we are alive */
- cpu_leds[cpuid] = 0x6;
- show_leds(cpuid);
-
- /* Enable level15 interrupt, disable level14 interrupt for now */
- cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
-}
-
-void sun4d_cpu_pre_online(void *arg)
-{
- int cpuid;
-
- cpuid = hard_smp_processor_id();
-
- /* Unblock the master CPU _only_ when the scheduler state
- * of all secondary CPUs will be up-to-date, so after
- * the SMP initialization the master will be just allowed
- * to call the scheduler code.
- */
- sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
- local_ops->cache_all();
- local_ops->tlb_all();
-
- while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
- barrier();
-
- while (current_set[cpuid]->cpu != cpuid)
- barrier();
-
- /* Fix idle thread fields. */
- __asm__ __volatile__("ld [%0], %%g6\n\t"
- : : "r" (¤t_set[cpuid])
- : "memory" /* paranoid */);
-
- cpu_leds[cpuid] = 0x9;
- show_leds(cpuid);
-
- /* Attach to the address space of init_task. */
- mmgrab(&init_mm);
- current->active_mm = &init_mm;
-
- local_ops->cache_all();
- local_ops->tlb_all();
-
- while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
- barrier();
-
- cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
-}
-
-/*
- * Cycle through the processors asking the PROM to start each one.
- */
-void __init smp4d_boot_cpus(void)
-{
- smp4d_ipi_init();
- if (boot_cpu_id)
- current_set[0] = NULL;
- local_ops->cache_all();
-}
-
-int smp4d_boot_one_cpu(int i, struct task_struct *idle)
-{
- unsigned long *entry = &sun4d_cpu_startup;
- int timeout;
- int cpu_node;
-
- cpu_find_by_instance(i, &cpu_node, NULL);
- current_set[i] = task_thread_info(idle);
- /*
- * Initialize the contexts table
- * Since the call to prom_startcpu() trashes the structure,
- * we need to re-initialize it for each cpu
- */
- smp_penguin_ctable.which_io = 0;
- smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
- smp_penguin_ctable.reg_size = 0;
-
- /* whirrr, whirrr, whirrrrrrrrr... */
- printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
- local_ops->cache_all();
- prom_startcpu(cpu_node,
- &smp_penguin_ctable, 0, (char *)entry);
-
- printk(KERN_INFO "prom_startcpu returned :)\n");
-
- /* wheee... it's going... */
- for (timeout = 0; timeout < 10000; timeout++) {
- if (cpu_callin_map[i])
- break;
- udelay(200);
- }
-
- if (!(cpu_callin_map[i])) {
- printk(KERN_ERR "Processor %d is stuck.\n", i);
- return -ENODEV;
-
- }
- local_ops->cache_all();
- return 0;
-}
-
-void __init smp4d_smp_done(void)
-{
- int i, first;
- int *prev;
-
- /* setup cpu list for irq rotation */
- first = 0;
- prev = &first;
- for_each_online_cpu(i) {
- *prev = i;
- prev = &cpu_data(i).next;
- }
- *prev = first;
- local_ops->cache_all();
-
- /* Ok, they are spinning and ready to go. */
- smp_processors_ready = 1;
-}
-
-/* Memory structure giving interrupt handler information about IPI generated */
-struct sun4d_ipi_work {
- int single;
- int msk;
- int resched;
-};
-
-static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
-
-/* Initialize IPIs on the SUN4D SMP machine */
-static void __init smp4d_ipi_init(void)
-{
- int cpu;
- struct sun4d_ipi_work *work;
-
- printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
-
- for_each_possible_cpu(cpu) {
- work = &per_cpu(sun4d_ipi_work, cpu);
- work->single = work->msk = work->resched = 0;
- }
-}
-
-void sun4d_ipi_interrupt(void)
-{
- struct sun4d_ipi_work *work = this_cpu_ptr(&sun4d_ipi_work);
-
- if (work->single) {
- work->single = 0;
- smp_call_function_single_interrupt();
- }
- if (work->msk) {
- work->msk = 0;
- smp_call_function_interrupt();
- }
- if (work->resched) {
- work->resched = 0;
- smp_resched_interrupt();
- }
-}
-
-/* +-------+-------------+-----------+------------------------------------+
- * | bcast | devid | sid | levels mask |
- * +-------+-------------+-----------+------------------------------------+
- * 31 30 23 22 15 14 0
- */
-#define IGEN_MESSAGE(bcast, devid, sid, levels) \
- (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
-
-static void sun4d_send_ipi(int cpu, int level)
-{
- cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
-}
-
-static void sun4d_ipi_single(int cpu)
-{
- struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
-
- /* Mark work */
- work->single = 1;
-
- /* Generate IRQ on the CPU */
- sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
-}
-
-static void sun4d_ipi_mask_one(int cpu)
-{
- struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
-
- /* Mark work */
- work->msk = 1;
-
- /* Generate IRQ on the CPU */
- sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
-}
-
-static void sun4d_ipi_resched(int cpu)
-{
- struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
-
- /* Mark work */
- work->resched = 1;
-
- /* Generate IRQ on the CPU (any IRQ will cause resched) */
- sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
-}
-
-static struct smp_funcall {
- void *func;
- unsigned long arg1;
- unsigned long arg2;
- unsigned long arg3;
- unsigned long arg4;
- unsigned long arg5;
- unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
- unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
-} ccall_info __attribute__((aligned(8)));
-
-static DEFINE_SPINLOCK(cross_call_lock);
-
-/* Cross calls must be serialized, at least currently. */
-static void sun4d_cross_call(void *func, cpumask_t mask, unsigned long arg1,
- unsigned long arg2, unsigned long arg3,
- unsigned long arg4)
-{
- if (smp_processors_ready) {
- register int high = smp_highest_cpu;
- unsigned long flags;
-
- spin_lock_irqsave(&cross_call_lock, flags);
-
- {
- /*
- * If you make changes here, make sure
- * gcc generates proper code...
- */
- register void *f asm("i0") = func;
- register unsigned long a1 asm("i1") = arg1;
- register unsigned long a2 asm("i2") = arg2;
- register unsigned long a3 asm("i3") = arg3;
- register unsigned long a4 asm("i4") = arg4;
- register unsigned long a5 asm("i5") = 0;
-
- __asm__ __volatile__(
- "std %0, [%6]\n\t"
- "std %2, [%6 + 8]\n\t"
- "std %4, [%6 + 16]\n\t" : :
- "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
- "r" (&ccall_info.func));
- }
-
- /* Init receive/complete mapping, plus fire the IPI's off. */
- {
- register int i;
-
- cpumask_clear_cpu(smp_processor_id(), &mask);
- cpumask_and(&mask, cpu_online_mask, &mask);
- for (i = 0; i <= high; i++) {
- if (cpumask_test_cpu(i, &mask)) {
- ccall_info.processors_in[i] = 0;
- ccall_info.processors_out[i] = 0;
- sun4d_send_ipi(i, IRQ_CROSS_CALL);
- }
- }
- }
-
- {
- register int i;
-
- i = 0;
- do {
- if (!cpumask_test_cpu(i, &mask))
- continue;
- while (!ccall_info.processors_in[i])
- barrier();
- } while (++i <= high);
-
- i = 0;
- do {
- if (!cpumask_test_cpu(i, &mask))
- continue;
- while (!ccall_info.processors_out[i])
- barrier();
- } while (++i <= high);
- }
-
- spin_unlock_irqrestore(&cross_call_lock, flags);
- }
-}
-
-/* Running cross calls. */
-void smp4d_cross_call_irq(void)
-{
- void (*func)(unsigned long, unsigned long, unsigned long, unsigned long,
- unsigned long) = ccall_info.func;
- int i = hard_smp_processor_id();
-
- ccall_info.processors_in[i] = 1;
- func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4,
- ccall_info.arg5);
- ccall_info.processors_out[i] = 1;
-}
-
-void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
- int cpu = hard_smp_processor_id();
- struct clock_event_device *ce;
- static int cpu_tick[NR_CPUS];
- static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
-
- old_regs = set_irq_regs(regs);
- bw_get_prof_limit(cpu);
- bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
-
- cpu_tick[cpu]++;
- if (!(cpu_tick[cpu] & 15)) {
- if (cpu_tick[cpu] == 0x60)
- cpu_tick[cpu] = 0;
- cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
- show_leds(cpu);
- }
-
- ce = &per_cpu(sparc32_clockevent, cpu);
-
- irq_enter();
- ce->event_handler(ce);
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-static const struct sparc32_ipi_ops sun4d_ipi_ops = {
- .cross_call = sun4d_cross_call,
- .resched = sun4d_ipi_resched,
- .single = sun4d_ipi_single,
- .mask_one = sun4d_ipi_mask_one,
-};
-
-void __init sun4d_init_smp(void)
-{
- int i;
-
- sparc32_ipi_ops = &sun4d_ipi_ops;
-
- for (i = 0; i < NR_CPUS; i++) {
- ccall_info.processors_in[i] = 1;
- ccall_info.processors_out[i] = 1;
- }
-}
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
deleted file mode 100644
index 056df034e79e..000000000000
--- a/arch/sparc/kernel/sun4m_smp.c
+++ /dev/null
@@ -1,275 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * sun4m SMP support.
- *
- * Copyright (C) 1996 David S. Miller ([email protected])
- */
-
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/profile.h>
-#include <linux/delay.h>
-#include <linux/sched/mm.h>
-#include <linux/cpu.h>
-
-#include <asm/cacheflush.h>
-#include <asm/switch_to.h>
-#include <asm/tlbflush.h>
-#include <asm/timer.h>
-#include <asm/oplib.h>
-
-#include "irq.h"
-#include "kernel.h"
-
-#define IRQ_IPI_SINGLE 12
-#define IRQ_IPI_MASK 13
-#define IRQ_IPI_RESCHED 14
-#define IRQ_CROSS_CALL 15
-
-static inline unsigned long
-swap_ulong(volatile unsigned long *ptr, unsigned long val)
-{
- __asm__ __volatile__("swap [%1], %0\n\t" :
- "=&r" (val), "=&r" (ptr) :
- "0" (val), "1" (ptr));
- return val;
-}
-
-void sun4m_cpu_pre_starting(void *arg)
-{
-}
-
-void sun4m_cpu_pre_online(void *arg)
-{
- int cpuid = hard_smp_processor_id();
-
- /* Allow master to continue. The master will then give us the
- * go-ahead by setting the smp_commenced_mask and will wait without
- * timeouts until our setup is completed fully (signified by
- * our bit being set in the cpu_online_mask).
- */
- swap_ulong(&cpu_callin_map[cpuid], 1);
-
- /* XXX: What's up with all the flushes? */
- local_ops->cache_all();
- local_ops->tlb_all();
-
- /* Fix idle thread fields. */
- __asm__ __volatile__("ld [%0], %%g6\n\t"
- : : "r" (¤t_set[cpuid])
- : "memory" /* paranoid */);
-
- /* Attach to the address space of init_task. */
- mmgrab(&init_mm);
- current->active_mm = &init_mm;
-
- while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
- mb();
-}
-
-/*
- * Cycle through the processors asking the PROM to start each one.
- */
-void __init smp4m_boot_cpus(void)
-{
- sun4m_unmask_profile_irq();
- local_ops->cache_all();
-}
-
-int smp4m_boot_one_cpu(int i, struct task_struct *idle)
-{
- unsigned long *entry = &sun4m_cpu_startup;
- int timeout;
- int cpu_node;
-
- cpu_find_by_mid(i, &cpu_node);
- current_set[i] = task_thread_info(idle);
-
- /* See trampoline.S for details... */
- entry += ((i - 1) * 3);
-
- /*
- * Initialize the contexts table
- * Since the call to prom_startcpu() trashes the structure,
- * we need to re-initialize it for each cpu
- */
- smp_penguin_ctable.which_io = 0;
- smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
- smp_penguin_ctable.reg_size = 0;
-
- /* whirrr, whirrr, whirrrrrrrrr... */
- printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
- local_ops->cache_all();
- prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
-
- /* wheee... it's going... */
- for (timeout = 0; timeout < 10000; timeout++) {
- if (cpu_callin_map[i])
- break;
- udelay(200);
- }
-
- if (!(cpu_callin_map[i])) {
- printk(KERN_ERR "Processor %d is stuck.\n", i);
- return -ENODEV;
- }
-
- local_ops->cache_all();
- return 0;
-}
-
-void __init smp4m_smp_done(void)
-{
- int i, first;
- int *prev;
-
- /* setup cpu list for irq rotation */
- first = 0;
- prev = &first;
- for_each_online_cpu(i) {
- *prev = i;
- prev = &cpu_data(i).next;
- }
- *prev = first;
- local_ops->cache_all();
-
- /* Ok, they are spinning and ready to go. */
-}
-
-static void sun4m_send_ipi(int cpu, int level)
-{
- sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
-}
-
-static void sun4m_ipi_resched(int cpu)
-{
- sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
-}
-
-static void sun4m_ipi_single(int cpu)
-{
- sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
-}
-
-static void sun4m_ipi_mask_one(int cpu)
-{
- sun4m_send_ipi(cpu, IRQ_IPI_MASK);
-}
-
-static struct smp_funcall {
- void *func;
- unsigned long arg1;
- unsigned long arg2;
- unsigned long arg3;
- unsigned long arg4;
- unsigned long arg5;
- unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
- unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
-} ccall_info;
-
-static DEFINE_SPINLOCK(cross_call_lock);
-
-/* Cross calls must be serialized, at least currently. */
-static void sun4m_cross_call(void *func, cpumask_t mask, unsigned long arg1,
- unsigned long arg2, unsigned long arg3,
- unsigned long arg4)
-{
- register int ncpus = SUN4M_NCPUS;
- unsigned long flags;
-
- spin_lock_irqsave(&cross_call_lock, flags);
-
- /* Init function glue. */
- ccall_info.func = func;
- ccall_info.arg1 = arg1;
- ccall_info.arg2 = arg2;
- ccall_info.arg3 = arg3;
- ccall_info.arg4 = arg4;
- ccall_info.arg5 = 0;
-
- /* Init receive/complete mapping, plus fire the IPI's off. */
- {
- register int i;
-
- cpumask_clear_cpu(smp_processor_id(), &mask);
- cpumask_and(&mask, cpu_online_mask, &mask);
- for (i = 0; i < ncpus; i++) {
- if (cpumask_test_cpu(i, &mask)) {
- ccall_info.processors_in[i] = 0;
- ccall_info.processors_out[i] = 0;
- sun4m_send_ipi(i, IRQ_CROSS_CALL);
- } else {
- ccall_info.processors_in[i] = 1;
- ccall_info.processors_out[i] = 1;
- }
- }
- }
-
- {
- register int i;
-
- i = 0;
- do {
- if (!cpumask_test_cpu(i, &mask))
- continue;
- while (!ccall_info.processors_in[i])
- barrier();
- } while (++i < ncpus);
-
- i = 0;
- do {
- if (!cpumask_test_cpu(i, &mask))
- continue;
- while (!ccall_info.processors_out[i])
- barrier();
- } while (++i < ncpus);
- }
- spin_unlock_irqrestore(&cross_call_lock, flags);
-}
-
-/* Running cross calls. */
-void smp4m_cross_call_irq(void)
-{
- void (*func)(unsigned long, unsigned long, unsigned long, unsigned long,
- unsigned long) = ccall_info.func;
- int i = smp_processor_id();
-
- ccall_info.processors_in[i] = 1;
- func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4,
- ccall_info.arg5);
- ccall_info.processors_out[i] = 1;
-}
-
-void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
- struct clock_event_device *ce;
- int cpu = smp_processor_id();
-
- old_regs = set_irq_regs(regs);
-
- ce = &per_cpu(sparc32_clockevent, cpu);
-
- if (clockevent_state_periodic(ce))
- sun4m_clear_profile_irq(cpu);
- else
- sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
-
- irq_enter();
- ce->event_handler(ce);
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-static const struct sparc32_ipi_ops sun4m_ipi_ops = {
- .cross_call = sun4m_cross_call,
- .resched = sun4m_ipi_resched,
- .single = sun4m_ipi_single,
- .mask_one = sun4m_ipi_mask_one,
-};
-
-void __init sun4m_init_smp(void)
-{
- sparc32_ipi_ops = &sun4m_ipi_ops;
-}
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 852085ada368..04d9653890c5 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -1816,14 +1816,8 @@ void __init load_mmu(void)
&smp_cachetlb_ops;
#endif
- if (sparc_cpu_model != sun4d)
- ld_mmu_iommu();
+ ld_mmu_iommu();
#ifdef CONFIG_SMP
- if (sparc_cpu_model == sun4d)
- sun4d_init_smp();
- else if (sparc_cpu_model == sparc_leon)
- leon_init_smp();
- else
- sun4m_init_smp();
+ leon_init_smp();
#endif
}
--
2.34.1
From: Sam Ravnborg <[email protected]>
Some of the sun4m irq infrastructure is used by LEON too,
so keep that and drop the rest.
The patch include a few extra fixes fix the build after
the removal of the irq support.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/irq_32.h | 2 -
arch/sparc/kernel/Makefile | 2 +-
arch/sparc/kernel/irq_32.c | 30 +--
arch/sparc/kernel/kernel.h | 13 --
arch/sparc/kernel/sun4d_irq.c | 494 ----------------------------------------
arch/sparc/kernel/sun4d_smp.c | 4 -
arch/sparc/kernel/sun4m_irq.c | 240 -------------------
arch/sparc/mm/io-unit.c | 2 -
8 files changed, 2 insertions(+), 785 deletions(-)
diff --git a/arch/sparc/include/asm/irq_32.h b/arch/sparc/include/asm/irq_32.h
index 6ee48321cbc2..c402c81b85a7 100644
--- a/arch/sparc/include/asm/irq_32.h
+++ b/arch/sparc/include/asm/irq_32.h
@@ -17,8 +17,6 @@
#define irq_canonicalize(irq) (irq)
-void __init sun4d_init_sbi_irq(void);
-
#define NO_IRQ 0xffffffff
#endif
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index b253b7e132ce..d3d21e58b4e6 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -28,7 +28,7 @@ obj-y += traps_$(BITS).o
# IRQ
obj-y += irq_$(BITS).o
-obj-$(CONFIG_SPARC32) += sun4m_irq.o sun4d_irq.o
+obj-$(CONFIG_SPARC32) += sun4m_irq.o
obj-y += process_$(BITS).o
obj-y += process.o
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index 510184c3aa17..135170f362c1 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -235,36 +235,8 @@ void handler_irq(unsigned int pil, struct pt_regs *regs)
set_irq_regs(old_regs);
}
-/* djhr
- * This could probably be made indirect too and assigned in the CPU
- * bits of the code. That would be much nicer I think and would also
- * fit in with the idea of being able to tune your kernel for your machine
- * by removing unrequired machine and device support.
- *
- */
-
void __init init_IRQ(void)
{
- switch (sparc_cpu_model) {
- case sun4m:
- pcic_probe();
- if (pcic_present())
- sun4m_pci_init_IRQ();
- else
- sun4m_init_IRQ();
- break;
-
- case sun4d:
- sun4d_init_IRQ();
- break;
-
- case sparc_leon:
- leon_init_IRQ();
- break;
-
- default:
- prom_printf("Cannot initialize IRQs on this Sun machine...");
- break;
- }
+ leon_init_IRQ();
}
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 6165e1b26df7..c467b1425506 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -93,7 +93,6 @@ extern spinlock_t irq_action_lock;
void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs);
/* sun4m_irq.c */
-void sun4m_init_IRQ(void);
void sun4m_unmask_profile_irq(void);
void sun4m_clear_profile_irq(int cpu);
@@ -106,18 +105,6 @@ void __init smp4m_smp_done(void);
void smp4m_cross_call_irq(void);
void smp4m_percpu_timer_interrupt(struct pt_regs *regs);
-/* sun4d_irq.c */
-extern spinlock_t sun4d_imsk_lock;
-
-void sun4d_init_IRQ(void);
-int sun4d_request_irq(unsigned int irq,
- irq_handler_t handler,
- unsigned long irqflags,
- const char *devname, void *dev_id);
-int show_sun4d_interrupts(struct seq_file *, void *);
-void sun4d_distribute_irqs(void);
-void sun4d_free_irq(unsigned int irq, void *dev_id);
-
/* sun4d_smp.c */
void sun4d_cpu_pre_starting(void *arg);
void sun4d_cpu_pre_online(void *arg);
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
deleted file mode 100644
index 7140cff04b54..000000000000
--- a/arch/sparc/kernel/sun4d_irq.c
+++ /dev/null
@@ -1,494 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SS1000/SC2000 interrupt handling.
- *
- * Copyright (C) 1997,1998 Jakub Jelinek ([email protected])
- * Heavily based on arch/sparc/kernel/irq.c.
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/slab.h>
-#include <linux/seq_file.h>
-
-#include <asm/timer.h>
-#include <asm/traps.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/sbi.h>
-#include <asm/cacheflush.h>
-#include <asm/setup.h>
-#include <asm/oplib.h>
-
-#include "kernel.h"
-#include "irq.h"
-
-/* Sun4d interrupts fall roughly into two categories. SBUS and
- * cpu local. CPU local interrupts cover the timer interrupts
- * and whatnot, and we encode those as normal PILs between
- * 0 and 15.
- * SBUS interrupts are encodes as a combination of board, level and slot.
- */
-
-struct sun4d_handler_data {
- unsigned int cpuid; /* target cpu */
- unsigned int real_irq; /* interrupt level */
-};
-
-
-static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
-{
- return (board + 1) << 5 | (lvl << 2) | slot;
-}
-
-struct sun4d_timer_regs {
- u32 l10_timer_limit;
- u32 l10_cur_countx;
- u32 l10_limit_noclear;
- u32 ctrl;
- u32 l10_cur_count;
-};
-
-static struct sun4d_timer_regs __iomem *sun4d_timers;
-
-#define SUN4D_TIMER_IRQ 10
-
-/* Specify which cpu handle interrupts from which board.
- * Index is board - value is cpu.
- */
-static unsigned char board_to_cpu[32];
-
-static int pil_to_sbus[] = {
- 0,
- 0,
- 1,
- 2,
- 0,
- 3,
- 0,
- 4,
- 0,
- 5,
- 0,
- 6,
- 0,
- 7,
- 0,
- 0,
-};
-
-/* Exported for sun4d_smp.c */
-DEFINE_SPINLOCK(sun4d_imsk_lock);
-
-/* SBUS interrupts are encoded integers including the board number
- * (plus one), the SBUS level, and the SBUS slot number. Sun4D
- * IRQ dispatch is done by:
- *
- * 1) Reading the BW local interrupt table in order to get the bus
- * interrupt mask.
- *
- * This table is indexed by SBUS interrupt level which can be
- * derived from the PIL we got interrupted on.
- *
- * 2) For each bus showing interrupt pending from #1, read the
- * SBI interrupt state register. This will indicate which slots
- * have interrupts pending for that SBUS interrupt level.
- *
- * 3) Call the genreric IRQ support.
- */
-static void sun4d_sbus_handler_irq(int sbusl)
-{
- unsigned int bus_mask;
- unsigned int sbino, slot;
- unsigned int sbil;
-
- bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
- bw_clear_intr_mask(sbusl, bus_mask);
-
- sbil = (sbusl << 2);
- /* Loop for each pending SBI */
- for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
- unsigned int idx, mask;
-
- if (!(bus_mask & 1))
- continue;
- /* XXX This seems to ACK the irq twice. acquire_sbi()
- * XXX uses swap, therefore this writes 0xf << sbil,
- * XXX then later release_sbi() will write the individual
- * XXX bits which were set again.
- */
- mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
- mask &= (0xf << sbil);
-
- /* Loop for each pending SBI slot */
- slot = (1 << sbil);
- for (idx = 0; mask != 0; idx++, slot <<= 1) {
- unsigned int pil;
- struct irq_bucket *p;
-
- if (!(mask & slot))
- continue;
-
- mask &= ~slot;
- pil = sun4d_encode_irq(sbino, sbusl, idx);
-
- p = irq_map[pil];
- while (p) {
- struct irq_bucket *next;
-
- next = p->next;
- generic_handle_irq(p->irq);
- p = next;
- }
- release_sbi(SBI2DEVID(sbino), slot);
- }
- }
-}
-
-void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
- /* SBUS IRQ level (1 - 7) */
- int sbusl = pil_to_sbus[pil];
-
- /* FIXME: Is this necessary?? */
- cc_get_ipen();
-
- cc_set_iclr(1 << pil);
-
-#ifdef CONFIG_SMP
- /*
- * Check IPI data structures after IRQ has been cleared. Hard and Soft
- * IRQ can happen at the same time, so both cases are always handled.
- */
- if (pil == SUN4D_IPI_IRQ)
- sun4d_ipi_interrupt();
-#endif
-
- old_regs = set_irq_regs(regs);
- irq_enter();
- if (sbusl == 0) {
- /* cpu interrupt */
- struct irq_bucket *p;
-
- p = irq_map[pil];
- while (p) {
- struct irq_bucket *next;
-
- next = p->next;
- generic_handle_irq(p->irq);
- p = next;
- }
- } else {
- /* SBUS interrupt */
- sun4d_sbus_handler_irq(sbusl);
- }
- irq_exit();
- set_irq_regs(old_regs);
-}
-
-
-static void sun4d_mask_irq(struct irq_data *data)
-{
- struct sun4d_handler_data *handler_data = irq_data_get_irq_handler_data(data);
- unsigned int real_irq;
-#ifdef CONFIG_SMP
- int cpuid = handler_data->cpuid;
- unsigned long flags;
-#endif
- real_irq = handler_data->real_irq;
-#ifdef CONFIG_SMP
- spin_lock_irqsave(&sun4d_imsk_lock, flags);
- cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
- spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
-#else
- cc_set_imsk(cc_get_imsk() | (1 << real_irq));
-#endif
-}
-
-static void sun4d_unmask_irq(struct irq_data *data)
-{
- struct sun4d_handler_data *handler_data = irq_data_get_irq_handler_data(data);
- unsigned int real_irq;
-#ifdef CONFIG_SMP
- int cpuid = handler_data->cpuid;
- unsigned long flags;
-#endif
- real_irq = handler_data->real_irq;
-
-#ifdef CONFIG_SMP
- spin_lock_irqsave(&sun4d_imsk_lock, flags);
- cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
- spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
-#else
- cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
-#endif
-}
-
-static unsigned int sun4d_startup_irq(struct irq_data *data)
-{
- irq_link(data->irq);
- sun4d_unmask_irq(data);
- return 0;
-}
-
-static void sun4d_shutdown_irq(struct irq_data *data)
-{
- sun4d_mask_irq(data);
- irq_unlink(data->irq);
-}
-
-static struct irq_chip sun4d_irq = {
- .name = "sun4d",
- .irq_startup = sun4d_startup_irq,
- .irq_shutdown = sun4d_shutdown_irq,
- .irq_unmask = sun4d_unmask_irq,
- .irq_mask = sun4d_mask_irq,
-};
-
-#ifdef CONFIG_SMP
-/* Setup IRQ distribution scheme. */
-void __init sun4d_distribute_irqs(void)
-{
- struct device_node *dp;
-
- int cpuid = cpu_logical_map(1);
-
- if (cpuid == -1)
- cpuid = cpu_logical_map(0);
- for_each_node_by_name(dp, "sbi") {
- int devid = of_getintprop_default(dp, "device-id", 0);
- int board = of_getintprop_default(dp, "board#", 0);
- board_to_cpu[board] = cpuid;
- set_sbi_tid(devid, cpuid << 3);
- }
- printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
-}
-#endif
-
-static void sun4d_clear_clock_irq(void)
-{
- sbus_readl(&sun4d_timers->l10_timer_limit);
-}
-
-static void sun4d_load_profile_irq(int cpu, unsigned int limit)
-{
- unsigned int value = limit ? timer_value(limit) : 0;
- bw_set_prof_limit(cpu, value);
-}
-
-static void __init sun4d_load_profile_irqs(void)
-{
- int cpu = 0, mid;
-
- while (!cpu_find_by_instance(cpu, NULL, &mid)) {
- sun4d_load_profile_irq(mid >> 3, 0);
- cpu++;
- }
-}
-
-static unsigned int _sun4d_build_device_irq(unsigned int real_irq,
- unsigned int pil,
- unsigned int board)
-{
- struct sun4d_handler_data *handler_data;
- unsigned int irq;
-
- irq = irq_alloc(real_irq, pil);
- if (irq == 0) {
- prom_printf("IRQ: allocate for %d %d %d failed\n",
- real_irq, pil, board);
- goto err_out;
- }
-
- handler_data = irq_get_handler_data(irq);
- if (unlikely(handler_data))
- goto err_out;
-
- handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
- if (unlikely(!handler_data)) {
- prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
- prom_halt();
- }
- handler_data->cpuid = board_to_cpu[board];
- handler_data->real_irq = real_irq;
- irq_set_chip_and_handler_name(irq, &sun4d_irq,
- handle_level_irq, "level");
- irq_set_handler_data(irq, handler_data);
-
-err_out:
- return irq;
-}
-
-
-
-static unsigned int sun4d_build_device_irq(struct platform_device *op,
- unsigned int real_irq)
-{
- struct device_node *dp = op->dev.of_node;
- struct device_node *board_parent, *bus = dp->parent;
- char *bus_connection;
- const struct linux_prom_registers *regs;
- unsigned int pil;
- unsigned int irq;
- int board, slot;
- int sbusl;
-
- irq = real_irq;
- while (bus) {
- if (of_node_name_eq(bus, "sbi")) {
- bus_connection = "io-unit";
- break;
- }
-
- if (of_node_name_eq(bus, "bootbus")) {
- bus_connection = "cpu-unit";
- break;
- }
-
- bus = bus->parent;
- }
- if (!bus)
- goto err_out;
-
- regs = of_get_property(dp, "reg", NULL);
- if (!regs)
- goto err_out;
-
- slot = regs->which_io;
-
- /*
- * If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
- * lacks a "board#" property, something is very wrong.
- */
- if (!of_node_name_eq(bus->parent, bus_connection)) {
- printk(KERN_ERR "%pOF: Error, parent is not %s.\n",
- bus, bus_connection);
- goto err_out;
- }
- board_parent = bus->parent;
- board = of_getintprop_default(board_parent, "board#", -1);
- if (board == -1) {
- printk(KERN_ERR "%pOF: Error, lacks board# property.\n",
- board_parent);
- goto err_out;
- }
-
- sbusl = pil_to_sbus[real_irq];
- if (sbusl)
- pil = sun4d_encode_irq(board, sbusl, slot);
- else
- pil = real_irq;
-
- irq = _sun4d_build_device_irq(real_irq, pil, board);
-err_out:
- return irq;
-}
-
-static unsigned int sun4d_build_timer_irq(unsigned int board,
- unsigned int real_irq)
-{
- return _sun4d_build_device_irq(real_irq, real_irq, board);
-}
-
-
-static void __init sun4d_init_timers(void)
-{
- struct device_node *dp;
- struct resource res;
- unsigned int irq;
- const u32 *reg;
- int err;
- int board;
-
- dp = of_find_node_by_name(NULL, "cpu-unit");
- if (!dp) {
- prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
- prom_halt();
- }
-
- /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
- * registers via any cpu's mapping. The first 'reg' property is the
- * bootbus.
- */
- reg = of_get_property(dp, "reg", NULL);
- if (!reg) {
- prom_printf("sun4d_init_timers: No reg property\n");
- prom_halt();
- }
-
- board = of_getintprop_default(dp, "board#", -1);
- if (board == -1) {
- prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
- prom_halt();
- }
-
- of_node_put(dp);
-
- res.start = reg[1];
- res.end = reg[2] - 1;
- res.flags = reg[0] & 0xff;
- sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
- sizeof(struct sun4d_timer_regs), "user timer");
- if (!sun4d_timers) {
- prom_printf("sun4d_init_timers: Can't map timer regs\n");
- prom_halt();
- }
-
-#ifdef CONFIG_SMP
- sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
-#else
- sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
- sparc_config.features |= FEAT_L10_CLOCKEVENT;
-#endif
- sparc_config.features |= FEAT_L10_CLOCKSOURCE;
- sbus_writel(timer_value(sparc_config.cs_period),
- &sun4d_timers->l10_timer_limit);
-
- master_l10_counter = &sun4d_timers->l10_cur_count;
-
- irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
- err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
- if (err) {
- prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
- err);
- prom_halt();
- }
- sun4d_load_profile_irqs();
-}
-
-void __init sun4d_init_sbi_irq(void)
-{
- struct device_node *dp;
- int target_cpu;
-
- target_cpu = boot_cpu_id;
- for_each_node_by_name(dp, "sbi") {
- int devid = of_getintprop_default(dp, "device-id", 0);
- int board = of_getintprop_default(dp, "board#", 0);
- unsigned int mask;
-
- set_sbi_tid(devid, target_cpu << 3);
- board_to_cpu[board] = target_cpu;
-
- /* Get rid of pending irqs from PROM */
- mask = acquire_sbi(devid, 0xffffffff);
- if (mask) {
- printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
- mask, board);
- release_sbi(devid, mask);
- }
- }
-}
-
-void __init sun4d_init_IRQ(void)
-{
- local_irq_disable();
-
- sparc_config.init_timers = sun4d_init_timers;
- sparc_config.build_device_irq = sun4d_build_device_irq;
- sparc_config.clock_rate = SBUS_CLOCK_RATE;
- sparc_config.clear_clock_irq = sun4d_clear_clock_irq;
- sparc_config.load_profile_irq = sun4d_load_profile_irq;
-
- /* Cannot enable interrupts until OBP ticker is disabled. */
-}
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index be5bcbee1af4..7f49a8fa3e3a 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -65,7 +65,6 @@ void sun4d_cpu_pre_starting(void *arg)
void sun4d_cpu_pre_online(void *arg)
{
- unsigned long flags;
int cpuid;
cpuid = hard_smp_processor_id();
@@ -103,9 +102,7 @@ void sun4d_cpu_pre_online(void *arg)
while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
barrier();
- spin_lock_irqsave(&sun4d_imsk_lock, flags);
cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
- spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
}
/*
@@ -177,7 +174,6 @@ void __init smp4d_smp_done(void)
/* Ok, they are spinning and ready to go. */
smp_processors_ready = 1;
- sun4d_distribute_irqs();
}
/* Memory structure giving interrupt handler information about IPI generated */
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index 1079638986b5..1a220a2b9ac3 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -187,103 +187,6 @@ static unsigned long sun4m_imask[0x50] = {
0, SUN4M_INT_VME(6), 0, 0
};
-static void sun4m_mask_irq(struct irq_data *data)
-{
- struct sun4m_handler_data *handler_data;
- int cpu = smp_processor_id();
-
- handler_data = irq_data_get_irq_handler_data(data);
- if (handler_data->mask) {
- unsigned long flags;
-
- local_irq_save(flags);
- if (handler_data->percpu) {
- sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
- } else {
- sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
- }
- local_irq_restore(flags);
- }
-}
-
-static void sun4m_unmask_irq(struct irq_data *data)
-{
- struct sun4m_handler_data *handler_data;
- int cpu = smp_processor_id();
-
- handler_data = irq_data_get_irq_handler_data(data);
- if (handler_data->mask) {
- unsigned long flags;
-
- local_irq_save(flags);
- if (handler_data->percpu) {
- sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
- } else {
- sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
- }
- local_irq_restore(flags);
- }
-}
-
-static unsigned int sun4m_startup_irq(struct irq_data *data)
-{
- irq_link(data->irq);
- sun4m_unmask_irq(data);
- return 0;
-}
-
-static void sun4m_shutdown_irq(struct irq_data *data)
-{
- sun4m_mask_irq(data);
- irq_unlink(data->irq);
-}
-
-static struct irq_chip sun4m_irq = {
- .name = "sun4m",
- .irq_startup = sun4m_startup_irq,
- .irq_shutdown = sun4m_shutdown_irq,
- .irq_mask = sun4m_mask_irq,
- .irq_unmask = sun4m_unmask_irq,
-};
-
-
-static unsigned int sun4m_build_device_irq(struct platform_device *op,
- unsigned int real_irq)
-{
- struct sun4m_handler_data *handler_data;
- unsigned int irq;
- unsigned int pil;
-
- if (real_irq >= OBP_INT_LEVEL_VME) {
- prom_printf("Bogus sun4m IRQ %u\n", real_irq);
- prom_halt();
- }
- pil = (real_irq & 0xf);
- irq = irq_alloc(real_irq, pil);
-
- if (irq == 0)
- goto out;
-
- handler_data = irq_get_handler_data(irq);
- if (unlikely(handler_data))
- goto out;
-
- handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
- if (unlikely(!handler_data)) {
- prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
- prom_halt();
- }
-
- handler_data->mask = sun4m_imask[real_irq];
- handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
- irq_set_chip_and_handler_name(irq, &sun4m_irq,
- handle_level_irq, "level");
- irq_set_handler_data(irq, handler_data);
-
-out:
- return irq;
-}
-
struct sun4m_timer_percpu {
u32 l14_limit;
u32 l14_count;
@@ -293,21 +196,6 @@ struct sun4m_timer_percpu {
static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
-struct sun4m_timer_global {
- u32 l10_limit;
- u32 l10_count;
- u32 l10_limit_noclear;
- u32 reserved;
- u32 timer_config;
-};
-
-static struct sun4m_timer_global __iomem *timers_global;
-
-static void sun4m_clear_clock_irq(void)
-{
- sbus_readl(&timers_global->l10_limit);
-}
-
void sun4m_nmi(struct pt_regs *regs)
{
unsigned long afsr, afar, si;
@@ -348,131 +236,3 @@ void sun4m_clear_profile_irq(int cpu)
{
sbus_readl(&timers_percpu[cpu]->l14_limit);
}
-
-static void sun4m_load_profile_irq(int cpu, unsigned int limit)
-{
- unsigned int value = limit ? timer_value(limit) : 0;
- sbus_writel(value, &timers_percpu[cpu]->l14_limit);
-}
-
-static void __init sun4m_init_timers(void)
-{
- struct device_node *dp = of_find_node_by_name(NULL, "counter");
- int i, err, len, num_cpu_timers;
- unsigned int irq;
- const u32 *addr;
-
- if (!dp) {
- printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
- return;
- }
-
- addr = of_get_property(dp, "address", &len);
- of_node_put(dp);
- if (!addr) {
- printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
- return;
- }
-
- num_cpu_timers = (len / sizeof(u32)) - 1;
- for (i = 0; i < num_cpu_timers; i++) {
- timers_percpu[i] = (void __iomem *)
- (unsigned long) addr[i];
- }
- timers_global = (void __iomem *)
- (unsigned long) addr[num_cpu_timers];
-
- /* Every per-cpu timer works in timer mode */
- sbus_writel(0x00000000, &timers_global->timer_config);
-
-#ifdef CONFIG_SMP
- sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
- sparc_config.features |= FEAT_L14_ONESHOT;
-#else
- sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
- sparc_config.features |= FEAT_L10_CLOCKEVENT;
-#endif
- sparc_config.features |= FEAT_L10_CLOCKSOURCE;
- sbus_writel(timer_value(sparc_config.cs_period),
- &timers_global->l10_limit);
-
- master_l10_counter = &timers_global->l10_count;
-
- irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
-
- err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
- if (err) {
- printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
- err);
- return;
- }
-
- for (i = 0; i < num_cpu_timers; i++)
- sbus_writel(0, &timers_percpu[i]->l14_limit);
- if (num_cpu_timers == 4)
- sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
-
-#ifdef CONFIG_SMP
- {
- unsigned long flags;
- struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
-
- /* For SMP we use the level 14 ticker, however the bootup code
- * has copied the firmware's level 14 vector into the boot cpu's
- * trap table, we must fix this now or we get squashed.
- */
- local_irq_save(flags);
- trap_table->inst_one = lvl14_save[0];
- trap_table->inst_two = lvl14_save[1];
- trap_table->inst_three = lvl14_save[2];
- trap_table->inst_four = lvl14_save[3];
- local_ops->cache_all();
- local_irq_restore(flags);
- }
-#endif
-}
-
-void __init sun4m_init_IRQ(void)
-{
- struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
- int len, i, mid, num_cpu_iregs;
- const u32 *addr;
-
- if (!dp) {
- printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
- return;
- }
-
- addr = of_get_property(dp, "address", &len);
- of_node_put(dp);
- if (!addr) {
- printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
- return;
- }
-
- num_cpu_iregs = (len / sizeof(u32)) - 1;
- for (i = 0; i < num_cpu_iregs; i++) {
- sun4m_irq_percpu[i] = (void __iomem *)
- (unsigned long) addr[i];
- }
- sun4m_irq_global = (void __iomem *)
- (unsigned long) addr[num_cpu_iregs];
-
- local_irq_disable();
-
- sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
- for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
- sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
-
- if (num_cpu_iregs == 4)
- sbus_writel(0, &sun4m_irq_global->interrupt_target);
-
- sparc_config.init_timers = sun4m_init_timers;
- sparc_config.build_device_irq = sun4m_build_device_irq;
- sparc_config.clock_rate = SBUS_CLOCK_RATE;
- sparc_config.clear_clock_irq = sun4m_clear_clock_irq;
- sparc_config.load_profile_irq = sun4m_load_profile_irq;
-
-
- /* Cannot enable interrupts until OBP ticker is disabled. */
-}
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
index d8376f61b4d0..d94d7868feb9 100644
--- a/arch/sparc/mm/io-unit.c
+++ b/arch/sparc/mm/io-unit.c
@@ -86,8 +86,6 @@ static int __init iounit_init(void)
of_propagate_archdata(op);
}
- sun4d_init_sbi_irq();
-
return 0;
}
--
2.34.1
From: Sam Ravnborg <[email protected]>
sparc_config were used to handle the differences between the machines.
With only LEON supported sparc_config is no longer required.
Refactor the time code a litte as some parts are obsolete and other
parts are only used when SMP is not enabled.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/timer_32.h | 1 +
arch/sparc/kernel/irq.h | 37 +++-------------------
arch/sparc/kernel/irq_32.c | 3 --
arch/sparc/kernel/leon_kernel.c | 27 +++--------------
arch/sparc/kernel/of_device_32.c | 4 +--
arch/sparc/kernel/time_32.c | 64 +++++++++++++--------------------------
6 files changed, 33 insertions(+), 103 deletions(-)
diff --git a/arch/sparc/include/asm/timer_32.h b/arch/sparc/include/asm/timer_32.h
index eecd2696922d..1cd89a99966f 100644
--- a/arch/sparc/include/asm/timer_32.h
+++ b/arch/sparc/include/asm/timer_32.h
@@ -17,6 +17,7 @@
#include <asm/cpu_type.h> /* For SUN4M_NCPUS */
#define SBUS_CLOCK_RATE 2000000 /* 2MHz */
+#define LEON_CLOCK_RATE 1000000
#define TIMER_VALUE_SHIFT 9
#define TIMER_VALUE_MASK 0x3fffff
#define TIMER_LIMIT_BIT (1 << 31) /* Bit 31 in Counter-Timer register */
diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h
index 0d9b740725b4..8a0b314c8299 100644
--- a/arch/sparc/kernel/irq.h
+++ b/arch/sparc/kernel/irq.h
@@ -44,38 +44,6 @@ struct sun4m_irq_global {
extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
extern struct sun4m_irq_global __iomem *sun4m_irq_global;
-/* The following definitions describe the individual platform features: */
-#define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */
-#define FEAT_L10_CLOCKEVENT (1 << 1) /* L10 timer is used as a clockevent */
-#define FEAT_L14_ONESHOT (1 << 2) /* L14 timer clockevent can oneshot */
-
-/*
- * Platform specific configuration
- * The individual platforms assign their platform
- * specifics in their init functions.
- */
-struct sparc_config {
- void (*init_timers)(void);
- unsigned int (*build_device_irq)(struct platform_device *op,
- unsigned int real_irq);
-
- /* generic clockevent features - see FEAT_* above */
- int features;
-
- /* clock rate used for clock event timer */
- int clock_rate;
-
- /* one period for clock source timer */
- unsigned int cs_period;
-
- /* function to obtain offsett for cs period */
- unsigned int (*get_cycles_offset)(void);
-
- void (*clear_clock_irq)(void);
- void (*load_profile_irq)(int cpu, unsigned int limit);
-};
-extern struct sparc_config sparc_config;
-
unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
void irq_link(unsigned int irq);
void irq_unlink(unsigned int irq);
@@ -89,6 +57,11 @@ void sun4m_nmi(struct pt_regs *regs);
/* sun4d_irq.c */
void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs);
+/* leon_kernel.c */
+void leon_clear_clock_irq(void);
+void leon_load_profile_irq(int cpu, unsigned int limit);
+u32 leon_cycles_offset(void);
+
#ifdef CONFIG_SMP
/* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index a6af08fce796..f76f57073323 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -24,9 +24,6 @@
#include "kernel.h"
#include "irq.h"
-/* platform specific irq setup */
-struct sparc_config sparc_config;
-
unsigned long arch_local_irq_save(void)
{
unsigned long retval;
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index ea04bad6a118..fa9cdaffdc6b 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -237,12 +237,6 @@ unsigned int leon_build_device_irq(unsigned int real_irq,
return irq;
}
-static unsigned int _leon_build_device_irq(struct platform_device *op,
- unsigned int real_irq)
-{
- return leon_build_device_irq(real_irq, handle_simple_irq, "edge", 0);
-}
-
void leon_update_virq_handling(unsigned int virq,
irq_flow_handler_t flow_handler,
const char *name, int do_ack)
@@ -258,7 +252,7 @@ void leon_update_virq_handling(unsigned int virq,
irq_set_chip_data(virq, (void *)mask);
}
-static u32 leon_cycles_offset(void)
+u32 leon_cycles_offset(void)
{
u32 rld, val, ctrl, off;
@@ -312,14 +306,6 @@ void __init leon_init_timers(void)
u32 config;
u32 ctrl;
- sparc_config.get_cycles_offset = leon_cycles_offset;
- sparc_config.cs_period = 1000000 / HZ;
- sparc_config.features |= FEAT_L10_CLOCKSOURCE;
-
-#ifndef CONFIG_SMP
- sparc_config.features |= FEAT_L10_CLOCKEVENT;
-#endif
-
leondebug_irq_disable = 0;
leon_debug_irqout = 0;
master_l10_counter = (u32 __iomem *)&dummy_master_l10_counter;
@@ -434,7 +420,7 @@ void __init leon_init_timers(void)
err = request_irq(irq, leon_percpu_timer_ce_interrupt,
IRQF_PERCPU | IRQF_TIMER, "timer", NULL);
#else
- irq = _leon_build_device_irq(NULL, leon3_gptimer_irq);
+ irq = leon_build_device_irq(leon3_gptimer_irq, handle_simple_irq, "edge", 0);
err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
#endif
if (err) {
@@ -453,7 +439,7 @@ void __init leon_init_timers(void)
return;
}
-static void leon_clear_clock_irq(void)
+void leon_clear_clock_irq(void)
{
u32 ctrl;
@@ -462,7 +448,7 @@ static void leon_clear_clock_irq(void)
ctrl & leon3_gptimer_ackmask);
}
-static void leon_load_profile_irq(int cpu, unsigned int limit)
+void leon_load_profile_irq(int cpu, unsigned int limit)
{
}
@@ -485,9 +471,4 @@ void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu)
void __init leon_init_IRQ(void)
{
- sparc_config.init_timers = leon_init_timers;
- sparc_config.build_device_irq = _leon_build_device_irq;
- sparc_config.clock_rate = 1000000;
- sparc_config.clear_clock_irq = leon_clear_clock_irq;
- sparc_config.load_profile_irq = leon_load_profile_irq;
}
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index 06012e68bdca..ddb3b197d5e4 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -358,7 +358,7 @@ static struct platform_device * __init scan_one_device(struct device_node *dp,
op->archdata.num_irqs = len / sizeof(struct linux_prom_irqs);
for (i = 0; i < op->archdata.num_irqs; i++)
op->archdata.irqs[i] =
- sparc_config.build_device_irq(op, intr[i].pri);
+ leon_build_device_irq(intr[i].pri, handle_simple_irq, "edge", 0);
} else {
const unsigned int *irq =
of_get_property(dp, "interrupts", &len);
@@ -367,7 +367,7 @@ static struct platform_device * __init scan_one_device(struct device_node *dp,
op->archdata.num_irqs = len / sizeof(unsigned int);
for (i = 0; i < op->archdata.num_irqs; i++)
op->archdata.irqs[i] =
- sparc_config.build_device_irq(op, irq[i]);
+ leon_build_device_irq(irq[i], handle_simple_irq, "edge", 0);
} else {
op->archdata.num_irqs = 0;
}
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c
index 848404610b86..e6a2cb444777 100644
--- a/arch/sparc/kernel/time_32.c
+++ b/arch/sparc/kernel/time_32.c
@@ -44,6 +44,7 @@
#include <asm/idprom.h>
#include <asm/page.h>
#include <asm/irq_regs.h>
+#include <asm/leon.h>
#include <asm/setup.h>
#include "kernel.h"
@@ -88,10 +89,10 @@ irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
if (timer_cs_enabled) {
write_seqlock(&timer_cs_lock);
timer_cs_internal_counter++;
- sparc_config.clear_clock_irq();
+ leon_clear_clock_irq();
write_sequnlock(&timer_cs_lock);
} else {
- sparc_config.clear_clock_irq();
+ leon_clear_clock_irq();
}
if (timer_ce_enabled)
@@ -100,6 +101,7 @@ irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
return IRQ_HANDLED;
}
+#ifndef CONFIG_SMP
static int timer_ce_shutdown(struct clock_event_device *evt)
{
timer_ce_enabled = 0;
@@ -128,24 +130,10 @@ static __init void setup_timer_ce(void)
ce->tick_resume = timer_ce_set_periodic;
ce->cpumask = cpu_possible_mask;
ce->shift = 32;
- ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
- ce->shift);
+ ce->mult = div_sc(LEON_CLOCK_RATE, NSEC_PER_SEC, ce->shift);
clockevents_register_device(ce);
}
-
-static unsigned int sbus_cycles_offset(void)
-{
- u32 val, offset;
-
- val = sbus_readl(master_l10_counter);
- offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
-
- /* Limit hit? */
- if (val & TIMER_LIMIT_BIT)
- offset += sparc_config.cs_period;
-
- return offset;
-}
+#endif
static u64 timer_cs_read(struct clocksource *cs)
{
@@ -156,11 +144,11 @@ static u64 timer_cs_read(struct clocksource *cs)
seq = read_seqbegin(&timer_cs_lock);
cycles = timer_cs_internal_counter;
- offset = sparc_config.get_cycles_offset();
+ offset = leon_cycles_offset();
} while (read_seqretry(&timer_cs_lock, seq));
/* Count absolute cycles */
- cycles *= sparc_config.cs_period;
+ cycles *= LEON_CLOCK_RATE / HZ;
cycles += offset;
return cycles;
@@ -177,7 +165,7 @@ static struct clocksource timer_cs = {
static __init int setup_timer_cs(void)
{
timer_cs_enabled = 1;
- return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
+ return clocksource_register_hz(&timer_cs, LEON_CLOCK_RATE);
}
#ifdef CONFIG_SMP
@@ -185,7 +173,7 @@ static int percpu_ce_shutdown(struct clock_event_device *evt)
{
int cpu = cpumask_first(evt->cpumask);
- sparc_config.load_profile_irq(cpu, 0);
+ leon_load_profile_irq(cpu, 0);
return 0;
}
@@ -193,7 +181,7 @@ static int percpu_ce_set_periodic(struct clock_event_device *evt)
{
int cpu = cpumask_first(evt->cpumask);
- sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
+ leon_load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
return 0;
}
@@ -203,7 +191,7 @@ static int percpu_ce_set_next_event(unsigned long delta,
int cpu = cpumask_first(evt->cpumask);
unsigned int next = (unsigned int)delta;
- sparc_config.load_profile_irq(cpu, next);
+ leon_load_profile_irq(cpu, next);
return 0;
}
@@ -212,9 +200,6 @@ void register_percpu_ce(int cpu)
struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
- if (sparc_config.features & FEAT_L14_ONESHOT)
- features |= CLOCK_EVT_FEAT_ONESHOT;
-
ce->name = "percpu_ce";
ce->rating = 200;
ce->features = features;
@@ -224,10 +209,9 @@ void register_percpu_ce(int cpu)
ce->set_next_event = percpu_ce_set_next_event;
ce->cpumask = cpumask_of(cpu);
ce->shift = 32;
- ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
- ce->shift);
- ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
- ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate;
+ ce->mult = div_sc(LEON_CLOCK_RATE, NSEC_PER_SEC, ce->shift);
+ ce->max_delta_ns = clockevent_delta2ns(LEON_CLOCK_RATE, ce);
+ ce->max_delta_ticks = (unsigned long)LEON_CLOCK_RATE;
ce->min_delta_ns = clockevent_delta2ns(100, ce);
ce->min_delta_ticks = 100;
@@ -326,26 +310,20 @@ fs_initcall(clock_init);
static void __init sparc32_late_time_init(void)
{
- if (sparc_config.features & FEAT_L10_CLOCKEVENT)
- setup_timer_ce();
- if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
- setup_timer_cs();
+#ifndef CONFIG_SMP
+ setup_timer_ce();
+#endif
+ setup_timer_cs();
+
#ifdef CONFIG_SMP
register_percpu_ce(smp_processor_id());
#endif
}
-static void __init sbus_time_init(void)
-{
- sparc_config.get_cycles_offset = sbus_cycles_offset;
- sparc_config.init_timers();
-}
-
void __init time_init(void)
{
- sparc_config.features = 0;
late_time_init = sparc32_late_time_init;
- sbus_time_init();
+ leon_init_timers();
}
--
2.34.1
From: Sam Ravnborg <[email protected]>
The CPU is always leon, so the run-time cpuid patching is no longer
required.
Signed-off-by: Sam Ravnborg <[email protected]>
Reported-by: Andreas Larsson <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/winmacro.h | 12 ------------
arch/sparc/kernel/entry.S | 13 -------------
arch/sparc/kernel/setup_32.c | 31 -------------------------------
3 files changed, 56 deletions(-)
diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h
index b6e911f5d93c..16144900bd6c 100644
--- a/arch/sparc/include/asm/winmacro.h
+++ b/arch/sparc/include/asm/winmacro.h
@@ -105,21 +105,9 @@
#ifdef CONFIG_SMP
#define LOAD_CURRENT(dest_reg, idreg) \
-661: rd %tbr, %idreg; \
- srl %idreg, 10, %idreg; \
- and %idreg, 0xc, %idreg; \
- .section .cpuid_patch, "ax"; \
- /* Instruction location. */ \
- .word 661b; \
- /* SUN4D implementation. */ \
- lda [%g0] ASI_M_VIKING_TMP1, %idreg; \
- sll %idreg, 2, %idreg; \
- nop; \
- /* LEON implementation. */ \
rd %asr17, %idreg; \
srl %idreg, 0x1c, %idreg; \
sll %idreg, 0x02, %idreg; \
- .previous; \
sethi %hi(current_set), %dest_reg; \
or %dest_reg, %lo(current_set), %dest_reg;\
ld [%idreg + %dest_reg], %dest_reg;
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 0f2417ee3f95..f158cbca3e62 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -984,21 +984,8 @@ flushw_all:
#ifdef CONFIG_SMP
ENTRY(hard_smp_processor_id)
-661: rd %tbr, %g1
- srl %g1, 12, %o0
- and %o0, 3, %o0
- .section .cpuid_patch, "ax"
- /* Instruction location. */
- .word 661b
- /* SUN4D implementation. */
- lda [%g0] ASI_M_VIKING_TMP1, %o0
- nop
- nop
- /* LEON implementation. */
rd %asr17, %o0
srl %o0, 0x1c, %o0
- nop
- .previous
retl
nop
ENDPROC(hard_smp_processor_id)
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 0f38d72aae2d..af5f143ed882 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -178,34 +178,6 @@ extern int root_mountflags;
char reboot_command[COMMAND_LINE_SIZE];
-struct cpuid_patch_entry {
- unsigned int addr;
- unsigned int sun4d[3];
- unsigned int leon[3];
-};
-extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
-
-static void __init per_cpu_patch(void)
-{
- struct cpuid_patch_entry *p;
-
- p = &__cpuid_patch;
- while (p < &__cpuid_patch_end) {
- unsigned long addr = p->addr;
- unsigned int *insns;
-
- insns = &p->leon[0];
- *(unsigned int *) (addr + 0) = insns[0];
- flushi(addr + 0);
- *(unsigned int *) (addr + 4) = insns[1];
- flushi(addr + 4);
- *(unsigned int *) (addr + 8) = insns[2];
- flushi(addr + 8);
-
- p++;
- }
-}
-
static __init void leon_patch(void)
{
/* Default instruction is leon - no patching */
@@ -271,9 +243,6 @@ void __init setup_arch(char **cmdline_p)
(*(linux_dbvec->teach_debugger))();
}
- /* Run-time patch instructions to match the cpu model */
- per_cpu_patch();
-
paging_init();
smp_setup_cpu_possible_map();
--
2.34.1
From: Sam Ravnborg <[email protected]>
pcic is only used by MicroSPARC-IIep and not relevant for LEON.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/Kconfig | 5 -
arch/sparc/include/asm/pcic.h | 130 -------
arch/sparc/kernel/Makefile | 1 -
arch/sparc/kernel/entry.S | 48 ---
arch/sparc/kernel/irq_32.c | 1 -
arch/sparc/kernel/kernel.h | 4 -
arch/sparc/kernel/pcic.c | 829 ------------------------------------------
arch/sparc/kernel/time_32.c | 6 +-
8 files changed, 1 insertion(+), 1023 deletions(-)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 23cdf1959991..19ee7bc0b2ea 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -410,11 +410,6 @@ config SUN_LDOMS
Say Y here is you want to support virtual devices via
Logical Domains.
-config PCIC_PCI
- bool
- depends on PCI && SPARC32 && !SPARC_LEON
- default y
-
config LEON_PCI
bool
depends on PCI && SPARC_LEON
diff --git a/arch/sparc/include/asm/pcic.h b/arch/sparc/include/asm/pcic.h
deleted file mode 100644
index 238376b1ffcc..000000000000
--- a/arch/sparc/include/asm/pcic.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * pcic.h: JavaEngine 1 specific PCI definitions.
- *
- * Copyright (C) 1998 V. Roganov and G. Raiko
- */
-
-#ifndef __SPARC_PCIC_H
-#define __SPARC_PCIC_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/smp.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <asm/pbm.h>
-
-struct linux_pcic {
- void __iomem *pcic_regs;
- unsigned long pcic_io;
- void __iomem *pcic_config_space_addr;
- void __iomem *pcic_config_space_data;
- struct resource pcic_res_regs;
- struct resource pcic_res_io;
- struct resource pcic_res_cfg_addr;
- struct resource pcic_res_cfg_data;
- struct linux_pbm_info pbm;
- struct pcic_ca2irq *pcic_imap;
- int pcic_imdim;
-};
-
-#ifdef CONFIG_PCIC_PCI
-int pcic_present(void);
-int pcic_probe(void);
-void pci_time_init(void);
-void sun4m_pci_init_IRQ(void);
-#else
-static inline int pcic_present(void) { return 0; }
-static inline int pcic_probe(void) { return 0; }
-static inline void pci_time_init(void) {}
-static inline void sun4m_pci_init_IRQ(void) {}
-#endif
-#endif
-
-/* Size of PCI I/O space which we relocate. */
-#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
-
-/* PCIC Register Set. */
-#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
-#define PCI_SIZE_0 0x44 /* 32 bits */
-#define PCI_SIZE_1 0x48 /* 32 bits */
-#define PCI_SIZE_2 0x4c /* 32 bits */
-#define PCI_SIZE_3 0x50 /* 32 bits */
-#define PCI_SIZE_4 0x54 /* 32 bits */
-#define PCI_SIZE_5 0x58 /* 32 bits */
-#define PCI_PIO_CONTROL 0x60 /* 8 bits */
-#define PCI_DVMA_CONTROL 0x62 /* 8 bits */
-#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
-#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
-#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
-#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
-#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
-#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
-#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
-#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
-#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
-#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
-#define PCI_SYS_INT_PENDING_PIO 0x40000000
-#define PCI_SYS_INT_PENDING_DMA 0x20000000
-#define PCI_SYS_INT_PENDING_PCI 0x10000000
-#define PCI_SYS_INT_PENDING_APSR 0x08000000
-#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
-#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
-#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
-#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
-#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
-#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
-#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
-#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
-#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
-#define PCI_INT_SELECT_LO 0x88 /* 16 bits */
-#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
-#define PCI_INT_SELECT_HI 0x8c /* 16 bits */
-#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
-#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
-#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
-#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
-#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
-#define PCI_SMBAR0 0xa0 /* 8 bits */
-#define PCI_MSIZE0 0xa1 /* 8 bits */
-#define PCI_PMBAR0 0xa2 /* 8 bits */
-#define PCI_SMBAR1 0xa4 /* 8 bits */
-#define PCI_MSIZE1 0xa5 /* 8 bits */
-#define PCI_PMBAR1 0xa6 /* 8 bits */
-#define PCI_SIBAR 0xa8 /* 8 bits */
-#define PCI_SIBAR_ADDRESS_MASK 0xf
-#define PCI_ISIZE 0xa9 /* 8 bits */
-#define PCI_ISIZE_16M 0xf
-#define PCI_ISIZE_32M 0xe
-#define PCI_ISIZE_64M 0xc
-#define PCI_ISIZE_128M 0x8
-#define PCI_ISIZE_256M 0x0
-#define PCI_PIBAR 0xaa /* 8 bits */
-#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
-#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
-#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
-#define PCI_SYS_LIMIT 0xb8 /* 32 bits */
-#define PCI_SYS_COUNTER 0xbc /* 32 bits */
-#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
-#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
-#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
-#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
-#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
-#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
- ((cpu_irq) & 0xf))
-#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
-#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
-#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
-#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
-#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
-#define PCI_SYS_STATUS 0xd0 /* 8 bits */
-#define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
-#define PCI_SYS_STATUS_RESET (1<<1)
-#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
-#define PCI_SYS_STATUS_PCI_RESET (1<<5)
-#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
-#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
-
-#endif /* !(__SPARC_PCIC_H) */
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index bd31bdd0b13e..50d696c8a9d2 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -73,7 +73,6 @@ obj-$(CONFIG_SPARC64) += pcr.o
obj-$(CONFIG_SPARC64) += nmi.o
obj-$(CONFIG_SPARC64_SMP) += cpumap.o
-obj-$(CONFIG_PCIC_PCI) += pcic.o
obj-$(CONFIG_LEON_PCI) += leon_pci.o
obj-$(CONFIG_SPARC_GRPCI2)+= leon_pci_grpci2.o
obj-$(CONFIG_SPARC_GRPCI1)+= leon_pci_grpci1.o
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 9bd3813b872d..13011969e7eb 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -965,54 +965,6 @@ restore_current:
retl
nop
-#ifdef CONFIG_PCIC_PCI
-#include <asm/pcic.h>
-
- .align 4
- .globl linux_trap_ipi15_pcic
-linux_trap_ipi15_pcic:
- rd %wim, %l3
- SAVE_ALL
-
- /*
- * First deactivate NMI
- * or we cannot drop ET, cannot get window spill traps.
- * The busy loop is necessary because the PIO error
- * sometimes does not go away quickly and we trap again.
- */
- sethi %hi(pcic_regs), %o1
- ld [%o1 + %lo(pcic_regs)], %o2
-
- ! Get pending status for printouts later.
- ld [%o2 + PCI_SYS_INT_PENDING], %o0
-
- mov PCI_SYS_INT_PENDING_CLEAR_ALL, %o1
- stb %o1, [%o2 + PCI_SYS_INT_PENDING_CLEAR]
-1:
- ld [%o2 + PCI_SYS_INT_PENDING], %o1
- andcc %o1, ((PCI_SYS_INT_PENDING_PIO|PCI_SYS_INT_PENDING_PCI)>>24), %g0
- bne 1b
- nop
-
- or %l0, PSR_PIL, %l4
- wr %l4, 0x0, %psr
- WRITE_PAUSE
- wr %l4, PSR_ET, %psr
- WRITE_PAUSE
-
- call pcic_nmi
- add %sp, STACKFRAME_SZ, %o1 ! struct pt_regs *regs
- RESTORE_ALL
-
- .globl pcic_nmi_trap_patch
-pcic_nmi_trap_patch:
- sethi %hi(linux_trap_ipi15_pcic), %l3
- jmpl %l3 + %lo(linux_trap_ipi15_pcic), %g0
- rd %psr, %l0
- .word 0
-
-#endif /* CONFIG_PCIC_PCI */
-
.globl flushw_all
flushw_all:
save %sp, -0x40, %sp
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index 135170f362c1..a6af08fce796 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -19,7 +19,6 @@
#include <asm/cacheflush.h>
#include <asm/cpudata.h>
#include <asm/setup.h>
-#include <asm/pcic.h>
#include <asm/leon.h>
#include "kernel.h"
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 621fb7b6ec64..4fcd782f16a7 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -138,10 +138,6 @@ asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn);
/* windows.c */
void try_to_clear_window_buffer(struct pt_regs *regs, int who);
-/* pcic.c */
-extern void __iomem *pcic_regs;
-void pcic_nmi(unsigned int pend, struct pt_regs *regs);
-
/* time_32.c */
void __init time_init(void);
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
deleted file mode 100644
index d952bcbbc395..000000000000
--- a/arch/sparc/kernel/pcic.c
+++ /dev/null
@@ -1,829 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * pcic.c: MicroSPARC-IIep PCI controller support
- *
- * Copyright (C) 1998 V. Roganov and G. Raiko
- *
- * Code is derived from Ultra/PCI PSYCHO controller support, see that
- * for author info.
- *
- * Support for diverse IIep based platforms by Pete Zaitcev.
- * CP-1200 by Eric Brower.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/jiffies.h>
-
-#include <asm/swift.h> /* for cache flushing. */
-#include <asm/io.h>
-
-#include <linux/ctype.h>
-#include <linux/pci.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/interrupt.h>
-#include <linux/export.h>
-
-#include <asm/irq.h>
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/pcic.h>
-#include <asm/timex.h>
-#include <asm/timer.h>
-#include <linux/uaccess.h>
-#include <asm/irq_regs.h>
-
-#include "kernel.h"
-#include "irq.h"
-
-/*
- * I studied different documents and many live PROMs both from 2.30
- * family and 3.xx versions. I came to the amazing conclusion: there is
- * absolutely no way to route interrupts in IIep systems relying on
- * information which PROM presents. We must hardcode interrupt routing
- * schematics. And this actually sucks. -- zaitcev 1999/05/12
- *
- * To find irq for a device we determine which routing map
- * is in effect or, in other words, on which machine we are running.
- * We use PROM name for this although other techniques may be used
- * in special cases (Gleb reports a PROMless IIep based system).
- * Once we know the map we take device configuration address and
- * find PCIC pin number where INT line goes. Then we may either program
- * preferred irq into the PCIC or supply the preexisting irq to the device.
- */
-struct pcic_ca2irq {
- unsigned char busno; /* PCI bus number */
- unsigned char devfn; /* Configuration address */
- unsigned char pin; /* PCIC external interrupt pin */
- unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
- unsigned int force; /* Enforce preferred IRQ */
-};
-
-struct pcic_sn2list {
- char *sysname;
- struct pcic_ca2irq *intmap;
- int mapdim;
-};
-
-/*
- * JavaEngine-1 apparently has different versions.
- *
- * According to communications with Sun folks, for P2 build 501-4628-03:
- * pin 0 - parallel, audio;
- * pin 1 - Ethernet;
- * pin 2 - su;
- * pin 3 - PS/2 kbd and mouse.
- *
- * OEM manual (805-1486):
- * pin 0: Ethernet
- * pin 1: All EBus
- * pin 2: IGA (unused)
- * pin 3: Not connected
- * OEM manual says that 501-4628 & 501-4811 are the same thing,
- * only the latter has NAND flash in place.
- *
- * So far unofficial Sun wins over the OEM manual. Poor OEMs...
- */
-static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
- { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
- { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
- { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
-};
-
-/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
-static struct pcic_ca2irq pcic_i_jse[] = {
- { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
- { 0, 0x01, 1, 6, 0 }, /* hme */
- { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
- { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
- { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
- { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
- { 0, 0x80, 5, 11, 0 }, /* EIDE */
- /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
- { 0, 0xA0, 4, 9, 0 }, /* USB */
- /*
- * Some pins belong to non-PCI devices, we hardcode them in drivers.
- * sun4m timers - irq 10, 14
- * PC style RTC - pin 7, irq 4 ?
- * Smart card, Parallel - pin 4 shared with USB, ISA
- * audio - pin 3, irq 5 ?
- */
-};
-
-/* SPARCengine-6 was the original release name of CP1200.
- * The documentation differs between the two versions
- */
-static struct pcic_ca2irq pcic_i_se6[] = {
- { 0, 0x08, 0, 2, 0 }, /* SCSI */
- { 0, 0x01, 1, 6, 0 }, /* HME */
- { 0, 0x00, 3, 13, 0 }, /* EBus */
-};
-
-/*
- * Krups (courtesy of Varol Kaptan)
- * No documentation available, but it was easy to guess
- * because it was very similar to Espresso.
- *
- * pin 0 - kbd, mouse, serial;
- * pin 1 - Ethernet;
- * pin 2 - igs (we do not use it);
- * pin 3 - audio;
- * pin 4,5,6 - unused;
- * pin 7 - RTC (from P2 onwards as David B. says).
- */
-static struct pcic_ca2irq pcic_i_jk[] = {
- { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
- { 0, 0x01, 1, 6, 0 }, /* hme */
-};
-
-/*
- * Several entries in this list may point to the same routing map
- * as several PROMs may be installed on the same physical board.
- */
-#define SN2L_INIT(name, map) \
- { name, map, ARRAY_SIZE(map) }
-
-static struct pcic_sn2list pcic_known_sysnames[] = {
- SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
- SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
- SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
- SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
- SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
- { NULL, NULL, 0 }
-};
-
-/*
- * Only one PCIC per IIep,
- * and since we have no SMP IIep, only one per system.
- */
-static int pcic0_up;
-static struct linux_pcic pcic0;
-
-void __iomem *pcic_regs;
-static volatile int pcic_speculative;
-static volatile int pcic_trapped;
-
-/* forward */
-unsigned int pcic_build_device_irq(struct platform_device *op,
- unsigned int real_irq);
-
-#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
-
-static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
- int where, u32 *value)
-{
- struct linux_pcic *pcic;
- unsigned long flags;
-
- pcic = &pcic0;
-
- local_irq_save(flags);
-#if 0 /* does not fail here */
- pcic_speculative = 1;
- pcic_trapped = 0;
-#endif
- writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
-#if 0 /* does not fail here */
- nop();
- if (pcic_trapped) {
- local_irq_restore(flags);
- *value = ~0;
- return 0;
- }
-#endif
- pcic_speculative = 2;
- pcic_trapped = 0;
- *value = readl(pcic->pcic_config_space_data + (where&4));
- nop();
- if (pcic_trapped) {
- pcic_speculative = 0;
- local_irq_restore(flags);
- *value = ~0;
- return 0;
- }
- pcic_speculative = 0;
- local_irq_restore(flags);
- return 0;
-}
-
-static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- unsigned int v;
-
- if (bus->number != 0) return -EINVAL;
- switch (size) {
- case 1:
- pcic_read_config_dword(bus->number, devfn, where&~3, &v);
- *val = 0xff & (v >> (8*(where & 3)));
- return 0;
- case 2:
- if (where&1) return -EINVAL;
- pcic_read_config_dword(bus->number, devfn, where&~3, &v);
- *val = 0xffff & (v >> (8*(where & 3)));
- return 0;
- case 4:
- if (where&3) return -EINVAL;
- pcic_read_config_dword(bus->number, devfn, where&~3, val);
- return 0;
- }
- return -EINVAL;
-}
-
-static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
- int where, u32 value)
-{
- struct linux_pcic *pcic;
- unsigned long flags;
-
- pcic = &pcic0;
-
- local_irq_save(flags);
- writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
- writel(value, pcic->pcic_config_space_data + (where&4));
- local_irq_restore(flags);
- return 0;
-}
-
-static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- unsigned int v;
-
- if (bus->number != 0) return -EINVAL;
- switch (size) {
- case 1:
- pcic_read_config_dword(bus->number, devfn, where&~3, &v);
- v = (v & ~(0xff << (8*(where&3)))) |
- ((0xff&val) << (8*(where&3)));
- return pcic_write_config_dword(bus->number, devfn, where&~3, v);
- case 2:
- if (where&1) return -EINVAL;
- pcic_read_config_dword(bus->number, devfn, where&~3, &v);
- v = (v & ~(0xffff << (8*(where&3)))) |
- ((0xffff&val) << (8*(where&3)));
- return pcic_write_config_dword(bus->number, devfn, where&~3, v);
- case 4:
- if (where&3) return -EINVAL;
- return pcic_write_config_dword(bus->number, devfn, where, val);
- }
- return -EINVAL;
-}
-
-static struct pci_ops pcic_ops = {
- .read = pcic_read_config,
- .write = pcic_write_config,
-};
-
-/*
- * On sparc64 pcibios_init() calls pci_controller_probe().
- * We want PCIC probed little ahead so that interrupt controller
- * would be operational.
- */
-int __init pcic_probe(void)
-{
- struct linux_pcic *pcic;
- struct linux_prom_registers regs[PROMREG_MAX];
- struct linux_pbm_info* pbm;
- char namebuf[64];
- phandle node;
- int err;
-
- if (pcic0_up) {
- prom_printf("PCIC: called twice!\n");
- prom_halt();
- }
- pcic = &pcic0;
-
- node = prom_getchild (prom_root_node);
- node = prom_searchsiblings (node, "pci");
- if (node == 0)
- return -ENODEV;
- /*
- * Map in PCIC register set, config space, and IO base
- */
- err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
- if (err == 0 || err == -1) {
- prom_printf("PCIC: Error, cannot get PCIC registers "
- "from PROM.\n");
- prom_halt();
- }
-
- pcic0_up = 1;
-
- pcic->pcic_res_regs.name = "pcic_registers";
- pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
- if (!pcic->pcic_regs) {
- prom_printf("PCIC: Error, cannot map PCIC registers.\n");
- prom_halt();
- }
-
- pcic->pcic_res_io.name = "pcic_io";
- if ((pcic->pcic_io = (unsigned long)
- ioremap(regs[1].phys_addr, 0x10000)) == 0) {
- prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
- prom_halt();
- }
-
- pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
- if ((pcic->pcic_config_space_addr =
- ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
- prom_printf("PCIC: Error, cannot map "
- "PCI Configuration Space Address.\n");
- prom_halt();
- }
-
- /*
- * Docs say three least significant bits in address and data
- * must be the same. Thus, we need adjust size of data.
- */
- pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
- if ((pcic->pcic_config_space_data =
- ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
- prom_printf("PCIC: Error, cannot map "
- "PCI Configuration Space Data.\n");
- prom_halt();
- }
-
- pbm = &pcic->pbm;
- pbm->prom_node = node;
- prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
- strcpy(pbm->prom_name, namebuf);
-
- prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
- {
- struct pcic_sn2list *p;
-
- for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
- if (strcmp(namebuf, p->sysname) == 0)
- break;
- }
- pcic->pcic_imap = p->intmap;
- pcic->pcic_imdim = p->mapdim;
- }
- if (pcic->pcic_imap == NULL) {
- /*
- * We do not panic here for the sake of embedded systems.
- */
- printk("PCIC: System %s is unknown, cannot route interrupts\n",
- namebuf);
- }
-
- return 0;
-}
-
-static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
-{
- struct linux_pbm_info *pbm = &pcic->pbm;
-
- pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
- if (!pbm->pci_bus)
- return;
-
-#if 0 /* deadwood transplanted from sparc64 */
- pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, pbm->pci_bus);
- pci_assign_unassigned(pbm, pbm->pci_bus);
- pci_fixup_irq(pbm, pbm->pci_bus);
-#endif
- pci_bus_add_devices(pbm->pci_bus);
-}
-
-/*
- * Main entry point from the PCI subsystem.
- */
-static int __init pcic_init(void)
-{
- struct linux_pcic *pcic;
-
- /*
- * PCIC should be initialized at start of the timer.
- * So, here we report the presence of PCIC and do some magic passes.
- */
- if(!pcic0_up)
- return 0;
- pcic = &pcic0;
-
- /*
- * Switch off IOTLB translation.
- */
- writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
- pcic->pcic_regs+PCI_DVMA_CONTROL);
-
- /*
- * Increase mapped size for PCI memory space (DMA access).
- * Should be done in that order (size first, address second).
- * Why we couldn't set up 4GB and forget about it? XXX
- */
- writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
- writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
- pcic->pcic_regs+PCI_BASE_ADDRESS_0);
-
- pcic_pbm_scan_bus(pcic);
-
- return 0;
-}
-
-int pcic_present(void)
-{
- return pcic0_up;
-}
-
-static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
-{
- struct linux_prom_pci_registers regs[PROMREG_MAX];
- int err;
- phandle node = prom_getchild(pbm->prom_node);
-
- while(node) {
- err = prom_getproperty(node, "reg",
- (char *)®s[0], sizeof(regs));
- if(err != 0 && err != -1) {
- unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
- if(devfn == pdev->devfn)
- return node;
- }
- node = prom_getsibling(node);
- }
- return 0;
-}
-
-static inline struct pcidev_cookie *pci_devcookie_alloc(void)
-{
- return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
-}
-
-static void pcic_map_pci_device(struct linux_pcic *pcic,
- struct pci_dev *dev, int node)
-{
- char namebuf[64];
- unsigned long address;
- unsigned long flags;
- int j;
-
- if (node == 0 || node == -1) {
- strcpy(namebuf, "???");
- } else {
- prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
- }
-
- for (j = 0; j < 6; j++) {
- address = dev->resource[j].start;
- if (address == 0) break; /* are sequential */
- flags = dev->resource[j].flags;
- if ((flags & IORESOURCE_IO) != 0) {
- if (address < 0x10000) {
- /*
- * A device responds to I/O cycles on PCI.
- * We generate these cycles with memory
- * access into the fixed map (phys 0x30000000).
- *
- * Since a device driver does not want to
- * do ioremap() before accessing PC-style I/O,
- * we supply virtual, ready to access address.
- *
- * Note that request_region()
- * works for these devices.
- *
- * XXX Neat trick, but it's a *bad* idea
- * to shit into regions like that.
- * What if we want to allocate one more
- * PCI base address...
- */
- dev->resource[j].start =
- pcic->pcic_io + address;
- dev->resource[j].end = 1; /* XXX */
- dev->resource[j].flags =
- (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
- } else {
- /*
- * OOPS... PCI Spec allows this. Sun does
- * not have any devices getting above 64K
- * so it must be user with a weird I/O
- * board in a PCI slot. We must remap it
- * under 64K but it is not done yet. XXX
- */
- pci_info(dev, "PCIC: Skipping I/O space at "
- "0x%lx, this will Oops if a driver "
- "attaches device '%s'\n", address,
- namebuf);
- }
- }
- }
-}
-
-static void
-pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
-{
- struct pcic_ca2irq *p;
- unsigned int real_irq;
- int i, ivec;
- char namebuf[64];
-
- if (node == 0 || node == -1) {
- strcpy(namebuf, "???");
- } else {
- prom_getstring(node, "name", namebuf, sizeof(namebuf));
- }
-
- if ((p = pcic->pcic_imap) == NULL) {
- dev->irq = 0;
- return;
- }
- for (i = 0; i < pcic->pcic_imdim; i++) {
- if (p->busno == dev->bus->number && p->devfn == dev->devfn)
- break;
- p++;
- }
- if (i >= pcic->pcic_imdim) {
- pci_info(dev, "PCIC: device %s not found in %d\n", namebuf,
- pcic->pcic_imdim);
- dev->irq = 0;
- return;
- }
-
- i = p->pin;
- if (i >= 0 && i < 4) {
- ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
- real_irq = ivec >> (i << 2) & 0xF;
- } else if (i >= 4 && i < 8) {
- ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
- real_irq = ivec >> ((i-4) << 2) & 0xF;
- } else { /* Corrupted map */
- pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {}
- }
-/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
-
- /* real_irq means PROM did not bother to program the upper
- * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
- */
- if (real_irq == 0 || p->force) {
- if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
- pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
- }
- pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq,
- p->pin);
- real_irq = p->irq;
-
- i = p->pin;
- if (i >= 4) {
- ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
- ivec &= ~(0xF << ((i - 4) << 2));
- ivec |= p->irq << ((i - 4) << 2);
- writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
- } else {
- ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
- ivec &= ~(0xF << (i << 2));
- ivec |= p->irq << (i << 2);
- writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
- }
- }
- dev->irq = pcic_build_device_irq(NULL, real_irq);
-}
-
-/*
- * Normally called from {do_}pci_scan_bus...
- */
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_dev *dev;
- struct linux_pcic *pcic;
- /* struct linux_pbm_info* pbm = &pcic->pbm; */
- int node;
- struct pcidev_cookie *pcp;
-
- if (!pcic0_up) {
- pci_info(bus, "pcibios_fixup_bus: no PCIC\n");
- return;
- }
- pcic = &pcic0;
-
- /*
- * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
- */
- if (bus->number != 0) {
- pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n",
- bus->number);
- return;
- }
-
- list_for_each_entry(dev, &bus->devices, bus_list) {
- node = pdev_to_pnode(&pcic->pbm, dev);
- if(node == 0)
- node = -1;
-
- /* cookies */
- pcp = pci_devcookie_alloc();
- pcp->pbm = &pcic->pbm;
- pcp->prom_node = of_find_node_by_phandle(node);
- dev->sysdata = pcp;
-
- /* fixing I/O to look like memory */
- if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
- pcic_map_pci_device(pcic, dev, node);
-
- pcic_fill_irq(pcic, dev, node);
- }
-}
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- struct resource *res;
- u16 cmd, oldcmd;
- int i;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- oldcmd = cmd;
-
- pci_dev_for_each_resource(dev, res, i) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<i)))
- continue;
-
- if (res->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (res->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- if (cmd != oldcmd) {
- pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
-/* Makes compiler happy */
-static volatile int pcic_timer_dummy;
-
-static void pcic_clear_clock_irq(void)
-{
- pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
-}
-
-/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
-#define USECS_PER_JIFFY (1000000 / HZ)
-#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
-
-static unsigned int pcic_cycles_offset(void)
-{
- u32 value, count;
-
- value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
- count = value & ~PCI_SYS_COUNTER_OVERFLOW;
-
- if (value & PCI_SYS_COUNTER_OVERFLOW)
- count += TICK_TIMER_LIMIT;
- /*
- * We divide all by HZ
- * to have microsecond resolution and to avoid overflow
- */
- count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
-
- /* Coordinate with the sparc_config.clock_rate setting */
- return count * 2;
-}
-
-void __init pci_time_init(void)
-{
- struct linux_pcic *pcic = &pcic0;
- unsigned long v;
- int timer_irq, irq;
- int err;
-
-#ifndef CONFIG_SMP
- /*
- * The clock_rate is in SBUS dimension.
- * We take into account this in pcic_cycles_offset()
- */
- sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
- sparc_config.features |= FEAT_L10_CLOCKEVENT;
-#endif
- sparc_config.features |= FEAT_L10_CLOCKSOURCE;
- sparc_config.get_cycles_offset = pcic_cycles_offset;
-
- writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
- /* PROM should set appropriate irq */
- v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
- timer_irq = PCI_COUNTER_IRQ_SYS(v);
- writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
- pcic->pcic_regs+PCI_COUNTER_IRQ);
- irq = pcic_build_device_irq(NULL, timer_irq);
- err = request_irq(irq, timer_interrupt,
- IRQF_TIMER, "timer", NULL);
- if (err) {
- prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
- prom_halt();
- }
- local_irq_enable();
-}
-
-
-#if 0
-static void watchdog_reset() {
- writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
-}
-#endif
-
-/*
- * NMI
- */
-void pcic_nmi(unsigned int pend, struct pt_regs *regs)
-{
- pend = swab32(pend);
-
- if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
- /*
- * XXX On CP-1200 PCI #SERR may happen, we do not know
- * what to do about it yet.
- */
- printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
- pend, (int)regs->pc, pcic_speculative);
- for (;;) { }
- }
- pcic_speculative = 0;
- pcic_trapped = 1;
- regs->pc = regs->npc;
- regs->npc += 4;
-}
-
-static inline unsigned long get_irqmask(int irq_nr)
-{
- return 1 << irq_nr;
-}
-
-static void pcic_mask_irq(struct irq_data *data)
-{
- unsigned long mask, flags;
-
- mask = (unsigned long)data->chip_data;
- local_irq_save(flags);
- writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
- local_irq_restore(flags);
-}
-
-static void pcic_unmask_irq(struct irq_data *data)
-{
- unsigned long mask, flags;
-
- mask = (unsigned long)data->chip_data;
- local_irq_save(flags);
- writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
- local_irq_restore(flags);
-}
-
-static unsigned int pcic_startup_irq(struct irq_data *data)
-{
- irq_link(data->irq);
- pcic_unmask_irq(data);
- return 0;
-}
-
-static struct irq_chip pcic_irq = {
- .name = "pcic",
- .irq_startup = pcic_startup_irq,
- .irq_mask = pcic_mask_irq,
- .irq_unmask = pcic_unmask_irq,
-};
-
-unsigned int pcic_build_device_irq(struct platform_device *op,
- unsigned int real_irq)
-{
- unsigned int irq;
- unsigned long mask;
-
- irq = 0;
- mask = get_irqmask(real_irq);
- if (mask == 0)
- goto out;
-
- irq = irq_alloc(real_irq, real_irq);
- if (irq == 0)
- goto out;
-
- irq_set_chip_and_handler_name(irq, &pcic_irq,
- handle_level_irq, "PCIC");
- irq_set_chip_data(irq, (void *)mask);
-
-out:
- return irq;
-}
-
-
-static void pcic_load_profile_irq(int cpu, unsigned int limit)
-{
- printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
-}
-
-void __init sun4m_pci_init_IRQ(void)
-{
- sparc_config.build_device_irq = pcic_build_device_irq;
- sparc_config.clear_clock_irq = pcic_clear_clock_irq;
- sparc_config.load_profile_irq = pcic_load_profile_irq;
-}
-
-subsys_initcall(pcic_init);
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c
index 08bbdc458596..848404610b86 100644
--- a/arch/sparc/kernel/time_32.c
+++ b/arch/sparc/kernel/time_32.c
@@ -43,7 +43,6 @@
#include <asm/io.h>
#include <asm/idprom.h>
#include <asm/page.h>
-#include <asm/pcic.h>
#include <asm/irq_regs.h>
#include <asm/setup.h>
@@ -347,9 +346,6 @@ void __init time_init(void)
sparc_config.features = 0;
late_time_init = sparc32_late_time_init;
- if (pcic_present())
- pci_time_init();
- else
- sbus_time_init();
+ sbus_time_init();
}
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop support for prom ranges - not used anymore.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/oplib_32.h | 11 ----
arch/sparc/prom/Makefile | 1 -
arch/sparc/prom/init_32.c | 2 -
arch/sparc/prom/ranges.c | 114 --------------------------------------
4 files changed, 128 deletions(-)
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index d1cf3a27a40d..4ef7f05978d3 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -163,17 +163,6 @@ int prom_setprop(phandle node, const char *prop_name, char *prop_value,
phandle prom_inst2pkg(int);
-/* Dorking with Bus ranges... */
-
-/* Apply promlib probes OBIO ranges to registers. */
-void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
-
-/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
-void prom_apply_generic_ranges(phandle node, phandle parent,
- struct linux_prom_registers *sbusregs, int nregs);
-
-void prom_ranges_init(void);
-
/* CPU probing helpers. */
int cpu_find_by_instance(int instance, phandle *prom_node, int *mid);
int cpu_find_by_mid(int mid, phandle *prom_node);
diff --git a/arch/sparc/prom/Makefile b/arch/sparc/prom/Makefile
index a1adc75d8055..0be170eeb57a 100644
--- a/arch/sparc/prom/Makefile
+++ b/arch/sparc/prom/Makefile
@@ -9,7 +9,6 @@ lib-y += init_$(BITS).o
lib-$(CONFIG_SPARC32) += memory.o
lib-y += misc_$(BITS).o
lib-$(CONFIG_SPARC32) += mp.o
-lib-$(CONFIG_SPARC32) += ranges.o
lib-y += console_$(BITS).o
lib-y += printf.o
lib-y += tree_$(BITS).o
diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c
index d20470166cb1..1681f1f980d4 100644
--- a/arch/sparc/prom/init_32.c
+++ b/arch/sparc/prom/init_32.c
@@ -67,8 +67,6 @@ void __init prom_init(struct linux_romvec *rp)
prom_meminit();
- prom_ranges_init();
-
printk("PROMLIB: Sun Boot Prom Version %d Revision %d\n",
romvec->pv_romvers, prom_rev);
diff --git a/arch/sparc/prom/ranges.c b/arch/sparc/prom/ranges.c
deleted file mode 100644
index 20cb828bc5f4..000000000000
--- a/arch/sparc/prom/ranges.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * ranges.c: Handle ranges in newer proms for obio/sbus.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- * Copyright (C) 1997 Jakub Jelinek ([email protected])
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-#include <asm/types.h>
-
-static struct linux_prom_ranges promlib_obio_ranges[PROMREG_MAX];
-static int num_obio_ranges;
-
-/* Adjust register values based upon the ranges parameters. */
-static void prom_adjust_regs(struct linux_prom_registers *regp, int nregs,
- struct linux_prom_ranges *rangep, int nranges)
-{
- int regc, rngc;
-
- for (regc = 0; regc < nregs; regc++) {
- for (rngc = 0; rngc < nranges; rngc++)
- if (regp[regc].which_io == rangep[rngc].ot_child_space)
- break; /* Fount it */
- if (rngc == nranges) /* oops */
- prom_printf("adjust_regs: Could not find range with matching bus type...\n");
- regp[regc].which_io = rangep[rngc].ot_parent_space;
- regp[regc].phys_addr -= rangep[rngc].ot_child_base;
- regp[regc].phys_addr += rangep[rngc].ot_parent_base;
- }
-}
-
-static void prom_adjust_ranges(struct linux_prom_ranges *ranges1, int nranges1,
- struct linux_prom_ranges *ranges2, int nranges2)
-{
- int rng1c, rng2c;
-
- for (rng1c = 0; rng1c < nranges1; rng1c++) {
- for (rng2c = 0; rng2c < nranges2; rng2c++)
- if (ranges1[rng1c].ot_parent_space == ranges2[rng2c].ot_child_space &&
- ranges1[rng1c].ot_parent_base >= ranges2[rng2c].ot_child_base &&
- ranges2[rng2c].ot_child_base + ranges2[rng2c].or_size - ranges1[rng1c].ot_parent_base > 0U)
- break;
- if (rng2c == nranges2) /* oops */
- prom_printf("adjust_ranges: Could not find matching bus type...\n");
- else if (ranges1[rng1c].ot_parent_base + ranges1[rng1c].or_size > ranges2[rng2c].ot_child_base + ranges2[rng2c].or_size)
- ranges1[rng1c].or_size = ranges2[rng2c].ot_child_base + ranges2[rng2c].or_size - ranges1[rng1c].ot_parent_base;
- ranges1[rng1c].ot_parent_space = ranges2[rng2c].ot_parent_space;
- ranges1[rng1c].ot_parent_base += ranges2[rng2c].ot_parent_base;
- }
-}
-
-/* Apply probed obio ranges to registers passed, if no ranges return. */
-void prom_apply_obio_ranges(struct linux_prom_registers *regs, int nregs)
-{
- if (num_obio_ranges)
- prom_adjust_regs(regs, nregs, promlib_obio_ranges, num_obio_ranges);
-}
-EXPORT_SYMBOL(prom_apply_obio_ranges);
-
-void __init prom_ranges_init(void)
-{
- phandle node, obio_node;
- int success;
-
- num_obio_ranges = 0;
-
- /* Check for obio and sbus ranges. */
- node = prom_getchild(prom_root_node);
- obio_node = prom_searchsiblings(node, "obio");
-
- if (obio_node) {
- success = prom_getproperty(obio_node, "ranges",
- (char *) promlib_obio_ranges,
- sizeof(promlib_obio_ranges));
- if (success != -1)
- num_obio_ranges = (success / sizeof(struct linux_prom_ranges));
- }
-
- if (num_obio_ranges)
- prom_printf("PROMLIB: obio_ranges %d\n", num_obio_ranges);
-}
-
-void prom_apply_generic_ranges(phandle node, phandle parent,
- struct linux_prom_registers *regs, int nregs)
-{
- int success;
- int num_ranges;
- struct linux_prom_ranges ranges[PROMREG_MAX];
-
- success = prom_getproperty(node, "ranges",
- (char *) ranges,
- sizeof(ranges));
- if (success != -1) {
- num_ranges = (success / sizeof(struct linux_prom_ranges));
- if (parent) {
- struct linux_prom_ranges parent_ranges[PROMREG_MAX];
- int num_parent_ranges;
-
- success = prom_getproperty(parent, "ranges",
- (char *) parent_ranges,
- sizeof(parent_ranges));
- if (success != -1) {
- num_parent_ranges = (success / sizeof(struct linux_prom_ranges));
- prom_adjust_ranges(ranges, num_ranges, parent_ranges, num_parent_ranges);
- }
- }
- prom_adjust_regs(regs, nregs, ranges, num_ranges);
- }
-}
--
2.34.1
From: Sam Ravnborg <[email protected]>
Some older SPARC CPUs had support for only 7 register windows.
To support this run-time patching was used.
LEON demand 8 register windows for use with Linux so
there is no need to support the 7 window configuration.
The complexity of the assembler code is reduced
when dropping the run-time patching, thus increasing
the maintainability.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/switch_to_32.h | 1 -
arch/sparc/kernel/entry.S | 28 ++++-----------
arch/sparc/kernel/etrap_32.S | 35 +++++--------------
arch/sparc/kernel/head_32.S | 65 -----------------------------------
arch/sparc/kernel/rtrap_32.S | 55 +++++++++++++----------------
arch/sparc/kernel/wof.S | 43 ++++++++---------------
arch/sparc/kernel/wuf.S | 20 +++--------
7 files changed, 57 insertions(+), 190 deletions(-)
diff --git a/arch/sparc/include/asm/switch_to_32.h b/arch/sparc/include/asm/switch_to_32.h
index 42eeafcb8a41..7aaaf31c09b4 100644
--- a/arch/sparc/include/asm/switch_to_32.h
+++ b/arch/sparc/include/asm/switch_to_32.h
@@ -37,7 +37,6 @@ extern struct thread_info *current_set[NR_CPUS];
#define prepare_arch_switch(next) do { \
__asm__ __volatile__( \
- ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
"save %sp, -0x40, %sp\n\t" \
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 18c67b4fb017..ea51a17ac3fc 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -384,11 +384,8 @@ do_flush_windows:
RESTORE_ALL
- .globl flush_patch_one
-
/* We get these for debugging routines using __builtin_return_address() */
dfw_kernel:
-flush_patch_one:
FLUSH_ALL_KERNEL_WINDOWS
/* Advance over the trap instruction. */
@@ -558,10 +555,9 @@ sys_rt_sigreturn:
* XXX code just like on sparc64... -DaveM
*/
.align 4
- .globl sys_fork, flush_patch_two
+ .globl sys_fork
sys_fork:
mov %o7, %l5
-flush_patch_two:
FLUSH_ALL_KERNEL_WINDOWS;
ld [%curptr + TI_TASK], %o4
rd %psr, %g4
@@ -574,10 +570,9 @@ flush_patch_two:
mov %l5, %o7
/* Whee, kernel threads! */
- .globl sys_clone, flush_patch_three
+ .globl sys_clone
sys_clone:
mov %o7, %l5
-flush_patch_three:
FLUSH_ALL_KERNEL_WINDOWS;
ld [%curptr + TI_TASK], %o4
rd %psr, %g4
@@ -590,9 +585,8 @@ flush_patch_three:
mov %l5, %o7
/* Whee, real vfork! */
- .globl sys_vfork, flush_patch_four
+ .globl sys_vfork
sys_vfork:
-flush_patch_four:
FLUSH_ALL_KERNEL_WINDOWS;
ld [%curptr + TI_TASK], %o4
rd %psr, %g4
@@ -909,17 +903,7 @@ breakpoint_trap:
#endif
.align 4
- .globl flush_patch_exception
-flush_patch_exception:
- FLUSH_ALL_KERNEL_WINDOWS;
- ldd [%o0], %o6
- jmpl %o7 + 0xc, %g0 ! see asm-sparc/processor.h
- mov 1, %g1 ! signal EFAULT condition
-
- .align 4
- .globl kill_user_windows, kuw_patch1_7win
- .globl kuw_patch1
-kuw_patch1_7win: sll %o3, 6, %o3
+ .globl kill_user_windows
/* No matter how much overhead this routine has in the worst
* case scenario, it is several times better than taking the
@@ -939,11 +923,11 @@ kill_user_windows:
be 4f ! yep, we are done
rd %wim, %o3 ! get current wim
srl %o3, 1, %o4 ! simulate a save
-kuw_patch1:
+kuw_next:
sll %o3, 7, %o3 ! compute next wim
or %o4, %o3, %o3 ! result
andncc %o0, %o3, %o0 ! clean this bit in umask
- bne kuw_patch1 ! not done yet
+ bne kuw_next ! not done yet
srl %o3, 1, %o4 ! begin another save simulation
wr %o3, 0x0, %wim ! set the new wim
st %g0, [%g6 + TI_UWINMASK] ! clear uwinmask
diff --git a/arch/sparc/kernel/etrap_32.S b/arch/sparc/kernel/etrap_32.S
index bb222459f097..95dfdea1f36c 100644
--- a/arch/sparc/kernel/etrap_32.S
+++ b/arch/sparc/kernel/etrap_32.S
@@ -30,18 +30,6 @@
.text
.align 4
- /* SEVEN WINDOW PATCH INSTRUCTIONS */
- .globl tsetup_7win_patch1, tsetup_7win_patch2
- .globl tsetup_7win_patch3, tsetup_7win_patch4
- .globl tsetup_7win_patch5, tsetup_7win_patch6
-tsetup_7win_patch1: sll %t_wim, 0x6, %t_wim
-tsetup_7win_patch2: and %g2, 0x7f, %g2
-tsetup_7win_patch3: and %g2, 0x7f, %g2
-tsetup_7win_patch4: and %g1, 0x7f, %g1
-tsetup_7win_patch5: sll %t_wim, 0x6, %t_wim
-tsetup_7win_patch6: and %g2, 0x7f, %g2
- /* END OF PATCH INSTRUCTIONS */
-
/* At trap time, interrupts and all generic traps do the
* following:
*
@@ -72,9 +60,7 @@ tsetup_7win_patch6: and %g2, 0x7f, %g2
* trap pc and npc, and %l3 contains the trap time %wim.
*/
- .globl trap_setup, tsetup_patch1, tsetup_patch2
- .globl tsetup_patch3, tsetup_patch4
- .globl tsetup_patch5, tsetup_patch6
+ .globl trap_setup
trap_setup:
/* Calculate mask of trap window. See if from user
* or kernel and branch conditionally.
@@ -109,11 +95,10 @@ trap_setup_kernel_spill:
* %wim and go.
*/
srl %t_wim, 0x1, %g2 ! begin computation of new %wim
-tsetup_patch1:
- sll %t_wim, 0x7, %t_wim ! patched on 7 window Sparcs
+
+ sll %t_wim, 0x7, %t_wim
or %t_wim, %g2, %g2
-tsetup_patch2:
- and %g2, 0xff, %g2 ! patched on 7 window Sparcs
+ and %g2, 0xff, %g2
save %g0, %g0, %g0
@@ -185,8 +170,7 @@ trap_setup_from_user:
sub %g2, 0x1, %g2
1:
andn %g2, %t_twinmask, %g2
-tsetup_patch3:
- and %g2, 0xff, %g2 ! patched on 7win Sparcs
+ and %g2, 0xff, %g2
st %g2, [%curptr + TI_UWINMASK] ! store new umask
jmpl %t_retpc + 0x8, %g0 ! return to caller
@@ -199,14 +183,11 @@ trap_setup_user_spill:
* is in %g1 upon entry to here.
*/
-tsetup_patch4:
- and %g1, 0xff, %g1 ! patched on 7win Sparcs, mask
+ and %g1, 0xff, %g1
srl %t_wim, 0x1, %g2 ! compute new %wim
-tsetup_patch5:
- sll %t_wim, 0x7, %t_wim ! patched on 7win Sparcs
+ sll %t_wim, 0x7, %t_wim
or %t_wim, %g2, %g2 ! %g2 is new %wim
-tsetup_patch6:
- and %g2, 0xff, %g2 ! patched on 7win Sparcs
+ and %g2, 0xff, %g2
andn %g1, %g2, %g1 ! clear this bit in %g1
st %g1, [%curptr + TI_UWINMASK]
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S
index 03dc232dd235..908c77cb456e 100644
--- a/arch/sparc/kernel/head_32.S
+++ b/arch/sparc/kernel/head_32.S
@@ -404,71 +404,6 @@ leon_init:
wr %g1, 0x0, %wim ! make window 1 invalid
WRITE_PAUSE
- cmp %g3, 0x7
- bne 2f
- nop
-
- /* Adjust our window handling routines to
- * do things correctly on 7 window Sparcs.
- */
-
-#define PATCH_INSN(src, dest) \
- set src, %g5; \
- set dest, %g2; \
- ld [%g5], %g4; \
- st %g4, [%g2];
-
- /* Patch for window spills... */
- PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
- PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
- PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
-
- /* Patch for window fills... */
- PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
- PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
-
- /* Patch for trap entry setup... */
- PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
- PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
- PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
- PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
- PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
- PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
-
- /* Patch for returning from traps... */
- PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
- PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
- PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
- PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
- PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
-
- /* Patch for killing user windows from the register file. */
- PATCH_INSN(kuw_patch1_7win, kuw_patch1)
-
- /* Now patch the kernel window flush sequences.
- * This saves 2 traps on every switch and fork.
- */
- set 0x01000000, %g4
- set flush_patch_one, %g5
- st %g4, [%g5 + 0x18]
- st %g4, [%g5 + 0x1c]
- set flush_patch_two, %g5
- st %g4, [%g5 + 0x18]
- st %g4, [%g5 + 0x1c]
- set flush_patch_three, %g5
- st %g4, [%g5 + 0x18]
- st %g4, [%g5 + 0x1c]
- set flush_patch_four, %g5
- st %g4, [%g5 + 0x18]
- st %g4, [%g5 + 0x1c]
- set flush_patch_exception, %g5
- st %g4, [%g5 + 0x18]
- st %g4, [%g5 + 0x1c]
- set flush_patch_switch, %g5
- st %g4, [%g5 + 0x18]
- st %g4, [%g5 + 0x1c]
-
-2:
sethi %hi(nwindows), %g4
st %g3, [%g4 + %lo(nwindows)] ! store final value
sub %g3, 0x1, %g3
diff --git a/arch/sparc/kernel/rtrap_32.S b/arch/sparc/kernel/rtrap_32.S
index a232b367c219..8383048c3b5e 100644
--- a/arch/sparc/kernel/rtrap_32.S
+++ b/arch/sparc/kernel/rtrap_32.S
@@ -23,15 +23,6 @@
#define glob_tmp g4
#define curptr g6
- /* 7 WINDOW SPARC PATCH INSTRUCTIONS */
- .globl rtrap_7win_patch1, rtrap_7win_patch2, rtrap_7win_patch3
- .globl rtrap_7win_patch4, rtrap_7win_patch5
-rtrap_7win_patch1: srl %t_wim, 0x6, %glob_tmp
-rtrap_7win_patch2: and %glob_tmp, 0x7f, %glob_tmp
-rtrap_7win_patch3: srl %g1, 7, %g2
-rtrap_7win_patch4: srl %g2, 6, %g2
-rtrap_7win_patch5: and %g1, 0x7f, %g1
- /* END OF PATCH INSTRUCTIONS */
/* We need to check for a few things which are:
* 1) The need to call schedule() because this
@@ -117,17 +108,17 @@ ret_trap_nobufwins:
bne ret_trap_userwins_ok
nop
- /* Calculate new %wim, we have to pull a register
- * window from the users stack.
- */
+ /* Calculate new %wim, we have to pull a register
+ * window from the users stack.
+ */
ret_trap_pull_one_window:
- rd %wim, %t_wim
- sll %t_wim, 0x1, %twin_tmp1
-rtrap_patch1: srl %t_wim, 0x7, %glob_tmp
- or %glob_tmp, %twin_tmp1, %glob_tmp
-rtrap_patch2: and %glob_tmp, 0xff, %glob_tmp
+ rd %wim, %t_wim
+ sll %t_wim, 0x1, %twin_tmp1
+ srl %t_wim, 0x7, %glob_tmp
+ or %glob_tmp, %twin_tmp1, %glob_tmp
+ and %glob_tmp, 0xff, %glob_tmp
- wr %glob_tmp, 0x0, %wim
+ wr %glob_tmp, 0x0, %wim
/* Here comes the architecture specific
* branch to the user stack checking routine
@@ -174,20 +165,20 @@ ret_trap_unaligned_pc:
ld [%curptr + TI_FLAGS], %g2
ret_trap_kernel:
- /* Will the rett land us in the invalid window? */
- mov 2, %g1
- sll %g1, %t_psr, %g1
-rtrap_patch3: srl %g1, 8, %g2
- or %g1, %g2, %g1
- rd %wim, %g2
- andcc %g2, %g1, %g0
- be 1f ! Nope, just return from the trap
- sll %g2, 0x1, %g1
-
- /* We have to grab a window before returning. */
-rtrap_patch4: srl %g2, 7, %g2
- or %g1, %g2, %g1
-rtrap_patch5: and %g1, 0xff, %g1
+ /* Will the rett land us in the invalid window? */
+ mov 2, %g1
+ sll %g1, %t_psr, %g1
+ srl %g1, 8, %g2
+ or %g1, %g2, %g1
+ rd %wim, %g2
+ andcc %g2, %g1, %g0
+ be 1f ! Nope, just return from the trap
+ sll %g2, 0x1, %g1
+
+ /* We have to grab a window before returning. */
+ srl %g2, 7, %g2
+ or %g1, %g2, %g1
+ and %g1, 0xff, %g1
wr %g1, 0x0, %wim
diff --git a/arch/sparc/kernel/wof.S b/arch/sparc/kernel/wof.S
index fe4cfd4abcd2..30c5ebdd035c 100644
--- a/arch/sparc/kernel/wof.S
+++ b/arch/sparc/kernel/wof.S
@@ -43,18 +43,6 @@
#define twin_tmp l4 /* Temp reg, only usable in trap window T */
#define glob_tmp g5 /* Global temporary reg, usable anywhere G */
- .text
- .align 4
- /* BEGINNING OF PATCH INSTRUCTIONS */
- /* On a 7-window Sparc the boot code patches spnwin_*
- * instructions with the following ones.
- */
- .globl spnwin_patch1_7win, spnwin_patch2_7win, spnwin_patch3_7win
-spnwin_patch1_7win: sll %t_wim, 6, %glob_tmp
-spnwin_patch2_7win: and %glob_tmp, 0x7f, %glob_tmp
-spnwin_patch3_7win: and %twin_tmp, 0x7f, %twin_tmp
- /* END OF PATCH INSTRUCTIONS */
-
/* The trap entry point has done the following:
*
* rd %psr, %l0
@@ -69,7 +57,6 @@ spnwin_patch3_7win: and %twin_tmp, 0x7f, %twin_tmp
* will be all zeroes.
*/
.globl spill_window_entry
- .globl spnwin_patch1, spnwin_patch2, spnwin_patch3
spill_window_entry:
/* LOCATION: Trap Window */
@@ -81,10 +68,10 @@ spill_window_entry:
*
* newwim = ((%wim>>1) | (%wim<<(nwindows - 1)));
*/
- srl %t_wim, 0x1, %twin_tmp
-spnwin_patch1: sll %t_wim, 7, %glob_tmp
- or %glob_tmp, %twin_tmp, %glob_tmp
-spnwin_patch2: and %glob_tmp, 0xff, %glob_tmp
+ srl %t_wim, 0x1, %twin_tmp
+ sll %t_wim, 7, %glob_tmp
+ or %glob_tmp, %twin_tmp, %glob_tmp
+ and %glob_tmp, 0xff, %glob_tmp
/* The trap entry point has set the condition codes
* up for us to see if this is from user or kernel.
@@ -222,17 +209,17 @@ spwin_user_stack_is_bolixed:
mov 1, %twin_tmp
st %twin_tmp, [%curptr + TI_W_SAVED]
- /* Compute new user window mask. What we are basically
- * doing is taking two windows, the invalid one at trap
- * time and the one we attempted to throw onto the users
- * stack, and saying that everything else is an ok user
- * window. umask = ((~(%t_wim | %wim)) & valid_wim_bits)
- */
- rd %wim, %twin_tmp
- or %twin_tmp, %t_wim, %twin_tmp
- not %twin_tmp
-spnwin_patch3: and %twin_tmp, 0xff, %twin_tmp ! patched on 7win Sparcs
- st %twin_tmp, [%curptr + TI_UWINMASK]
+ /* Compute new user window mask. What we are basically
+ * doing is taking two windows, the invalid one at trap
+ * time and the one we attempted to throw onto the users
+ * stack, and saying that everything else is an ok user
+ * window. umask = ((~(%t_wim | %wim)) & valid_wim_bits)
+ */
+ rd %wim, %twin_tmp
+ or %twin_tmp, %t_wim, %twin_tmp
+ not %twin_tmp
+ and %twin_tmp, 0xff, %twin_tmp
+ st %twin_tmp, [%curptr + TI_UWINMASK]
#define STACK_OFFSET (THREAD_SIZE - TRACEREG_SZ - STACKFRAME_SZ)
diff --git a/arch/sparc/kernel/wuf.S b/arch/sparc/kernel/wuf.S
index 4c52b69d4b7a..dd2a539f92ff 100644
--- a/arch/sparc/kernel/wuf.S
+++ b/arch/sparc/kernel/wuf.S
@@ -68,27 +68,17 @@
* are done and return from trap if successful
*/
- /* BEGINNING OF PATCH INSTRUCTIONS */
-
- /* On 7-window Sparc the boot code patches fnwin_patch1
- * with the following instruction.
- */
- .globl fnwin_patch1_7win, fnwin_patch2_7win
-fnwin_patch1_7win: srl %t_wim, 6, %twin_tmp2
-fnwin_patch2_7win: and %twin_tmp1, 0x7f, %twin_tmp1
- /* END OF PATCH INSTRUCTIONS */
-
- .globl fill_window_entry, fnwin_patch1, fnwin_patch2
+ .globl fill_window_entry
fill_window_entry:
/* LOCATION: Window 'T' */
/* Compute what the new %wim is going to be if we retrieve
* the proper window off of the stack.
*/
- sll %t_wim, 1, %twin_tmp1
-fnwin_patch1: srl %t_wim, 7, %twin_tmp2
- or %twin_tmp1, %twin_tmp2, %twin_tmp1
-fnwin_patch2: and %twin_tmp1, 0xff, %twin_tmp1
+ sll %t_wim, 1, %twin_tmp1
+ srl %t_wim, 7, %twin_tmp2
+ or %twin_tmp1, %twin_tmp2, %twin_tmp1
+ and %twin_tmp1, 0xff, %twin_tmp1
wr %twin_tmp1, 0x0, %wim /* Make window 'I' invalid */
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop the sun4m and sun4d code from trampoline_32
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/kernel/kernel.h | 3 +-
arch/sparc/kernel/trampoline_32.S | 127 +-------------------------------------
2 files changed, 3 insertions(+), 127 deletions(-)
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index c2aaddedf097..2c57677770ff 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -112,8 +112,7 @@ extern unsigned int real_irq_entry[];
extern unsigned int smp4d_ticker[];
/* trampoline_32.S */
-extern unsigned long sun4m_cpu_startup;
-extern unsigned long sun4d_cpu_startup;
+void leon_smp_cpu_startup(int boot_cpu);
/* signal_32.c */
asmlinkage void do_sigreturn(struct pt_regs *regs);
diff --git a/arch/sparc/kernel/trampoline_32.S b/arch/sparc/kernel/trampoline_32.S
index 82fafeeb3a62..685b20923f6b 100644
--- a/arch/sparc/kernel/trampoline_32.S
+++ b/arch/sparc/kernel/trampoline_32.S
@@ -15,136 +15,12 @@
#include <asm/contregs.h>
#include <asm/thread_info.h>
- .globl sun4m_cpu_startup
- .globl sun4d_cpu_startup
-
- .align 4
-
/* When we start up a cpu for the first time it enters this routine.
* This initializes the chip from whatever state the prom left it
* in and sets PIL in %psr to 15, no irqs.
*/
-
-sun4m_cpu_startup:
-cpu1_startup:
- sethi %hi(trapbase_cpu1), %g3
- b 1f
- or %g3, %lo(trapbase_cpu1), %g3
-
-cpu2_startup:
- sethi %hi(trapbase_cpu2), %g3
- b 1f
- or %g3, %lo(trapbase_cpu2), %g3
-
-cpu3_startup:
- sethi %hi(trapbase_cpu3), %g3
- b 1f
- or %g3, %lo(trapbase_cpu3), %g3
-
-1:
- /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
- set (PSR_PIL | PSR_S | PSR_PS), %g1
- wr %g1, 0x0, %psr ! traps off though
- WRITE_PAUSE
-
- /* Our %wim is one behind CWP */
- mov 2, %g1
- wr %g1, 0x0, %wim
- WRITE_PAUSE
-
- /* This identifies "this cpu". */
- wr %g3, 0x0, %tbr
- WRITE_PAUSE
-
- /* Give ourselves a stack and curptr. */
- set current_set, %g5
- srl %g3, 10, %g4
- and %g4, 0xc, %g4
- ld [%g5 + %g4], %g6
-
- sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
- or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
- add %g6, %sp, %sp
-
- /* Turn on traps (PSR_ET). */
- rd %psr, %g1
- wr %g1, PSR_ET, %psr ! traps on
- WRITE_PAUSE
-
- /* Init our caches, etc. */
- set poke_srmmu, %g5
- ld [%g5], %g5
- call %g5
- nop
-
- /* Start this processor. */
- call smp_callin
- nop
-
- b,a smp_panic
-
.text
.align 4
-
-smp_panic:
- call cpu_panic
- nop
-
-/* CPUID in bootbus can be found at PA 0xff0140000 */
-#define SUN4D_BOOTBUS_CPUID 0xf0140000
-
- .align 4
-
-sun4d_cpu_startup:
- /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
- set (PSR_PIL | PSR_S | PSR_PS), %g1
- wr %g1, 0x0, %psr ! traps off though
- WRITE_PAUSE
-
- /* Our %wim is one behind CWP */
- mov 2, %g1
- wr %g1, 0x0, %wim
- WRITE_PAUSE
-
- /* Set tbr - we use just one trap table. */
- set trapbase, %g1
- wr %g1, 0x0, %tbr
- WRITE_PAUSE
-
- /* Get our CPU id out of bootbus */
- set SUN4D_BOOTBUS_CPUID, %g3
- lduba [%g3] ASI_M_CTL, %g3
- and %g3, 0xf8, %g3
- srl %g3, 3, %g1
- sta %g1, [%g0] ASI_M_VIKING_TMP1
-
- /* Give ourselves a stack and curptr. */
- set current_set, %g5
- srl %g3, 1, %g4
- ld [%g5 + %g4], %g6
-
- sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
- or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
- add %g6, %sp, %sp
-
- /* Turn on traps (PSR_ET). */
- rd %psr, %g1
- wr %g1, PSR_ET, %psr ! traps on
- WRITE_PAUSE
-
- /* Init our caches, etc. */
- set poke_srmmu, %g5
- ld [%g5], %g5
- call %g5
- nop
-
- /* Start this processor. */
- call smp_callin
- nop
-
- b,a smp_panic
-
- .align 4
.global leon_smp_cpu_startup, smp_penguin_ctable
leon_smp_cpu_startup:
@@ -198,4 +74,5 @@ leon_smp_cpu_startup:
call smp_callin
nop
- b,a smp_panic
+ b,a cpu_panic
+ nop
--
2.34.1
From: Sam Ravnborg <[email protected]>
sparc32 is always LEON, so no need to check for the model.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/cpu_type.h | 18 ---------
arch/sparc/include/asm/io_32.h | 4 +-
arch/sparc/kernel/devices.c | 7 +---
arch/sparc/kernel/ioport.c | 4 +-
arch/sparc/kernel/leon_pmc.c | 16 ++++----
arch/sparc/kernel/setup_32.c | 79 +--------------------------------------
6 files changed, 12 insertions(+), 116 deletions(-)
diff --git a/arch/sparc/include/asm/cpu_type.h b/arch/sparc/include/asm/cpu_type.h
index 2b59799859d1..3e0154c3f41d 100644
--- a/arch/sparc/include/asm/cpu_type.h
+++ b/arch/sparc/include/asm/cpu_type.h
@@ -2,28 +2,10 @@
#ifndef __ASM_CPU_TYPE_H
#define __ASM_CPU_TYPE_H
-/*
- * Sparc (general) CPU types
- */
-enum sparc_cpu {
- sun4m = 0x00,
- sun4d = 0x01,
- sun4e = 0x02,
- sun4u = 0x03, /* V8 ploos ploos */
- sun_unknown = 0x04,
- ap1000 = 0x05, /* almost a sun4m */
- sparc_leon = 0x06, /* Leon SoC */
-};
-
#ifdef CONFIG_SPARC32
-extern enum sparc_cpu sparc_cpu_model;
#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
-#else
-
-#define sparc_cpu_model sun4u
-
#endif
#endif /* __ASM_CPU_TYPE_H */
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 549f0a72280d..83abe709d120 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -138,11 +138,11 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *);
static inline int sbus_can_dma_64bit(void)
{
- return 0; /* actually, sparc_cpu_model==sun4d */
+ return 0;
}
static inline int sbus_can_burst64(void)
{
- return 0; /* actually, sparc_cpu_model==sun4d */
+ return 0;
}
struct device;
void sbus_set_sbus64(struct device *, int);
diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c
index b3c2d51b22c4..2963e89611a3 100644
--- a/arch/sparc/kernel/devices.c
+++ b/arch/sparc/kernel/devices.c
@@ -26,8 +26,6 @@
static char *cpu_mid_prop(void)
{
- if (sparc_cpu_model == sun4d)
- return "cpu-id";
return "mid";
}
@@ -40,8 +38,6 @@ static int check_cpu_node(phandle nd, int *cur_inst,
*prom_node = nd;
if (mid) {
*mid = prom_getintdefault(nd, cpu_mid_prop(), 0);
- if (sparc_cpu_model == sun4m)
- *mid &= 3;
}
return 0;
}
@@ -92,8 +88,7 @@ static int cpu_mid_compare(phandle nd, int instance, void *_arg)
int this_mid;
this_mid = prom_getintdefault(nd, cpu_mid_prop(), 0);
- if (this_mid == desired_mid
- || (sparc_cpu_model == sun4m && (this_mid & 3) == desired_mid))
+ if (this_mid == desired_mid)
return 0;
return -ENODEV;
}
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 5ebca5c7af1e..cf0ace29704a 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -309,9 +309,7 @@ arch_initcall(sparc_register_ioport);
void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
{
- if (dir != DMA_TO_DEVICE &&
- sparc_cpu_model == sparc_leon &&
- !sparc_leon3_snooping_enabled())
+ if (dir != DMA_TO_DEVICE && !sparc_leon3_snooping_enabled())
leon_flush_dcache_all();
}
diff --git a/arch/sparc/kernel/leon_pmc.c b/arch/sparc/kernel/leon_pmc.c
index 6c00cbad7fb5..d4a2d49f941c 100644
--- a/arch/sparc/kernel/leon_pmc.c
+++ b/arch/sparc/kernel/leon_pmc.c
@@ -79,15 +79,13 @@ static void pmc_leon_idle(void)
/* Install LEON Power Down function */
static int __init leon_pmc_install(void)
{
- if (sparc_cpu_model == sparc_leon) {
- /* Assign power management IDLE handler */
- if (pmc_leon_need_fixup())
- sparc_idle = pmc_leon_idle_fixup;
- else
- sparc_idle = pmc_leon_idle;
-
- printk(KERN_INFO "leon: power management initialized\n");
- }
+ /* Assign power management IDLE handler */
+ if (pmc_leon_need_fixup())
+ sparc_idle = pmc_leon_idle_fixup;
+ else
+ sparc_idle = pmc_leon_idle;
+
+ printk(KERN_INFO "leon: power management initialized\n");
return 0;
}
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 3c6c16fde8c3..0f38d72aae2d 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -189,30 +189,12 @@ static void __init per_cpu_patch(void)
{
struct cpuid_patch_entry *p;
- if (sparc_cpu_model == sun4m) {
- /* Nothing to do, this is what the unpatched code
- * targets.
- */
- return;
- }
-
p = &__cpuid_patch;
while (p < &__cpuid_patch_end) {
unsigned long addr = p->addr;
unsigned int *insns;
- switch (sparc_cpu_model) {
- case sun4d:
- insns = &p->sun4d[0];
- break;
-
- case sparc_leon:
- insns = &p->leon[0];
- break;
- default:
- prom_printf("Unknown cpu type, halting.\n");
- prom_halt();
- }
+ insns = &p->leon[0];
*(unsigned int *) (addr + 0) = insns[0];
flushi(addr + 0);
*(unsigned int *) (addr + 4) = insns[1];
@@ -224,31 +206,9 @@ static void __init per_cpu_patch(void)
}
}
-struct leon_1insn_patch_entry {
- unsigned int addr;
- unsigned int insn;
-};
-
-enum sparc_cpu sparc_cpu_model;
-EXPORT_SYMBOL(sparc_cpu_model);
-
static __init void leon_patch(void)
{
- struct leon_1insn_patch_entry *start = (void *)__leon_1insn_patch;
- struct leon_1insn_patch_entry *end = (void *)__leon_1insn_patch_end;
-
/* Default instruction is leon - no patching */
- if (sparc_cpu_model == sparc_leon)
- return;
-
- while (start < end) {
- unsigned long addr = start->addr;
-
- *(unsigned int *)(addr) = start->insn;
- flushi(addr);
-
- start++;
- }
}
struct tt_entry *sparc_ttable;
@@ -259,22 +219,6 @@ struct tt_entry *sparc_ttable;
void __init sparc32_start_kernel(struct linux_romvec *rp)
{
prom_init(rp);
-
- /* Set sparc_cpu_model */
- sparc_cpu_model = sun_unknown;
- if (!strcmp(&cputypval[0], "sun4m"))
- sparc_cpu_model = sun4m;
- if (!strcmp(&cputypval[0], "sun4s"))
- sparc_cpu_model = sun4m; /* CP-1200 with PROM 2.30 -E */
- if (!strcmp(&cputypval[0], "sun4d"))
- sparc_cpu_model = sun4d;
- if (!strcmp(&cputypval[0], "sun4e"))
- sparc_cpu_model = sun4e;
- if (!strcmp(&cputypval[0], "sun4u"))
- sparc_cpu_model = sun4u;
- if (!strncmp(&cputypval[0], "leon" , 4))
- sparc_cpu_model = sparc_leon;
-
leon_patch();
start_kernel();
}
@@ -295,27 +239,6 @@ void __init setup_arch(char **cmdline_p)
register_console(&prom_early_console);
- switch(sparc_cpu_model) {
- case sun4m:
- pr_info("ARCH: SUN4M\n");
- break;
- case sun4d:
- pr_info("ARCH: SUN4D\n");
- break;
- case sun4e:
- pr_info("ARCH: SUN4E\n");
- break;
- case sun4u:
- pr_info("ARCH: SUN4U\n");
- break;
- case sparc_leon:
- pr_info("ARCH: LEON\n");
- break;
- default:
- pr_info("ARCH: UNKNOWN!\n");
- break;
- }
-
idprom_init();
load_mmu();
--
2.34.1
From: Sam Ravnborg <[email protected]>
The only supported sparc32 CPU is LEON, so there is no need for a
config option to select it.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Greg Kroah-Hartman <[email protected]> #For the USB stuff
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/Kconfig | 27 +++++++++------------------
arch/sparc/configs/sparc32_defconfig | 1 -
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-hcd.c | 4 ++--
drivers/usb/host/uhci-hcd.c | 2 +-
5 files changed, 13 insertions(+), 23 deletions(-)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 19ee7bc0b2ea..e4e2548c1f1f 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -9,6 +9,10 @@ config 64BIT
Say yes to build a 64-bit kernel - formerly known as sparc64
Say no to build a 32-bit kernel - formerly known as sparc
+ The 32-bit kernel target the synthesizable LEON SPARC processor.
+ LEON is a part of the GRLIB collection of IP cores that are
+ distributed under GPL. GRLIB can be downloaded from http://www.gaisler.com.
+ You can download a sparc-linux cross-compilation toolchain at http://www.gaisler.com.
config SPARC
bool
@@ -62,6 +66,10 @@ config SPARC32
select HAVE_UID16
select LOCK_MM_AND_FIND_VMA
select OLD_SIGACTION
+ select USB_EHCI_BIG_ENDIAN_MMIO
+ select USB_EHCI_BIG_ENDIAN_DESC
+ select USB_UHCI_BIG_ENDIAN_MMIO
+ select USB_UHCI_BIG_ENDIAN_DESC
select ZONE_DMA
config SPARC64
@@ -344,22 +352,6 @@ config SERIAL_CONSOLE
If unsure, say N.
-config SPARC_LEON
- bool "Sparc Leon processor family"
- depends on SPARC32
- select USB_EHCI_BIG_ENDIAN_MMIO
- select USB_EHCI_BIG_ENDIAN_DESC
- select USB_UHCI_BIG_ENDIAN_MMIO
- select USB_UHCI_BIG_ENDIAN_DESC
- help
- If you say Y here if you are running on a SPARC-LEON processor.
- The LEON processor is a synthesizable VHDL model of the
- SPARC-v8 standard. LEON is part of the GRLIB collection of
- IP cores that are distributed under GPL. GRLIB can be downloaded
- from http://www.gaisler.com. You can download a sparc-linux cross-compilation
- toolchain at http://www.gaisler.com.
-
-if SPARC_LEON
menu "U-Boot options"
config UBOOT_LOAD_ADDR
@@ -390,7 +382,6 @@ config UBOOT_ENTRY_ADDR
Kernel.
endmenu
-endif
endmenu
@@ -412,7 +403,7 @@ config SUN_LDOMS
config LEON_PCI
bool
- depends on PCI && SPARC_LEON
+ depends on PCI && SPARC32
default y
config SPARC_GRPCI1
diff --git a/arch/sparc/configs/sparc32_defconfig b/arch/sparc/configs/sparc32_defconfig
index 71273fc578bf..dfd326f20876 100644
--- a/arch/sparc/configs/sparc32_defconfig
+++ b/arch/sparc/configs/sparc32_defconfig
@@ -10,7 +10,6 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_ZSTD is not set
CONFIG_SMP=y
CONFIG_HZ_100=y
-CONFIG_SPARC_LEON=y
CONFIG_SUN_OPENPROMFS=y
CONFIG_SUN_OPENPROMIO=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 4448d0ab06f0..c5f94c70482f 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -595,7 +595,7 @@ config USB_UHCI_HCD
config USB_UHCI_SUPPORT_NON_PCI_HC
bool
- default y if (SPARC_LEON || USB_UHCI_PLATFORM)
+ default y if (SPARC32 || USB_UHCI_PLATFORM)
config USB_UHCI_PLATFORM
bool
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 802bfafb1012..5011bc8348bb 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1329,7 +1329,7 @@ MODULE_LICENSE ("GPL");
#include "ehci-xilinx-of.c"
#endif
-#ifdef CONFIG_SPARC_LEON
+#ifdef CONFIG_SPARC32
#include "ehci-grlib.c"
#endif
@@ -1343,7 +1343,7 @@ static struct platform_driver * const platform_drivers[] = {
#ifdef CONFIG_XPS_USB_HCD_XILINX
&ehci_hcd_xilinx_of_driver,
#endif
-#ifdef CONFIG_SPARC_LEON
+#ifdef CONFIG_SPARC32
&ehci_grlib_driver,
#endif
};
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index fd2408b553cf..7cb820963988 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -846,7 +846,7 @@ static const char hcd_name[] = "uhci_hcd";
#define PCI_DRIVER uhci_pci_driver
#endif
-#ifdef CONFIG_SPARC_LEON
+#ifdef CONFIG_SPARC32
#include "uhci-grlib.c"
#define PLATFORM_DRIVER uhci_grlib_driver
#endif
--
2.34.1
From: Sam Ravnborg <[email protected]>
LEON do not have an sbus - so drop support for that for sparc32.
Fix a few Kconfig expressions to use CONFIG_SBUS rather than SPARC
as only SPARC64 has an sbus now.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/Kconfig | 4 +-
arch/sparc/include/asm/fb.h | 8 ++--
arch/sparc/include/asm/io_32.h | 83 ----------------------------------------
arch/sparc/kernel/ioport.c | 49 ------------------------
arch/sparc/kernel/of_device_32.c | 14 -------
drivers/video/fbdev/Kconfig | 2 +-
sound/sparc/Kconfig | 1 +
7 files changed, 9 insertions(+), 152 deletions(-)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index e4e2548c1f1f..e7a62cc06c51 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -388,11 +388,11 @@ endmenu
menu "Bus options (PCI etc.)"
config SBUS
bool
- default y
+ default y if SPARC64
config SBUSCHAR
bool
- default y
+ default y if SPARC64
config SUN_LDOMS
bool "Sun Logical Domains support"
diff --git a/arch/sparc/include/asm/fb.h b/arch/sparc/include/asm/fb.h
index 24440c0fda49..15b007875457 100644
--- a/arch/sparc/include/asm/fb.h
+++ b/arch/sparc/include/asm/fb.h
@@ -8,6 +8,9 @@
struct fb_info;
+int fb_is_primary_device(struct fb_info *info);
+#define fb_is_primary_device fb_is_primary_device
+
#ifdef CONFIG_SPARC32
static inline pgprot_t pgprot_framebuffer(pgprot_t prot,
unsigned long vm_start, unsigned long vm_end,
@@ -18,9 +21,7 @@ static inline pgprot_t pgprot_framebuffer(pgprot_t prot,
#define pgprot_framebuffer pgprot_framebuffer
#endif
-int fb_is_primary_device(struct fb_info *info);
-#define fb_is_primary_device fb_is_primary_device
-
+#ifdef CONFIG_SPARC64
static inline void fb_memcpy_fromio(void *to, const volatile void __iomem *from, size_t n)
{
sbus_memcpy_fromio(to, from, n);
@@ -38,6 +39,7 @@ static inline void fb_memset_io(volatile void __iomem *addr, int c, size_t n)
sbus_memset_io(addr, c, n);
}
#define fb_memset fb_memset_io
+#endif
#include <asm-generic/fb.h>
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 83abe709d120..b9f280ee1b11 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -56,78 +56,6 @@ static inline void _memcpy_toio(volatile void __iomem *dst, const void *src,
}
}
-/*
- * SBus accessors.
- *
- * SBus has only one, memory mapped, I/O space.
- * We do not need to flip bytes for SBus of course.
- */
-static inline u8 sbus_readb(const volatile void __iomem *addr)
-{
- return *(__force volatile u8 *)addr;
-}
-
-static inline u16 sbus_readw(const volatile void __iomem *addr)
-{
- return *(__force volatile u16 *)addr;
-}
-
-static inline u32 sbus_readl(const volatile void __iomem *addr)
-{
- return *(__force volatile u32 *)addr;
-}
-
-static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
-{
- *(__force volatile u8 *)addr = b;
-}
-
-static inline void sbus_writew(u16 w, volatile void __iomem *addr)
-{
- *(__force volatile u16 *)addr = w;
-}
-
-static inline void sbus_writel(u32 l, volatile void __iomem *addr)
-{
- *(__force volatile u32 *)addr = l;
-}
-
-static inline void sbus_memset_io(volatile void __iomem *__dst, int c,
- __kernel_size_t n)
-{
- while(n--) {
- sbus_writeb(c, __dst);
- __dst++;
- }
-}
-
-static inline void sbus_memcpy_fromio(void *dst,
- const volatile void __iomem *src,
- __kernel_size_t n)
-{
- char *d = dst;
-
- while (n--) {
- char tmp = sbus_readb(src);
- *d++ = tmp;
- src++;
- }
-}
-
-static inline void sbus_memcpy_toio(volatile void __iomem *dst,
- const void *src,
- __kernel_size_t n)
-{
- const char *s = src;
- volatile void __iomem *d = dst;
-
- while (n--) {
- char tmp = *s++;
- sbus_writeb(tmp, d);
- d++;
- }
-}
-
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr);
void ioport_unmap(void __iomem *);
@@ -136,17 +64,6 @@ void ioport_unmap(void __iomem *);
struct pci_dev;
void pci_iounmap(struct pci_dev *dev, void __iomem *);
-static inline int sbus_can_dma_64bit(void)
-{
- return 0;
-}
-static inline int sbus_can_burst64(void)
-{
- return 0;
-}
-struct device;
-void sbus_set_sbus64(struct device *, int);
-
#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 9c4c72775274..97b836f3be25 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -55,8 +55,6 @@ static void __iomem *_sparc_alloc_io(unsigned int busno, unsigned long phys,
unsigned long size, char *name);
static void _sparc_free_io(struct resource *res);
-static void register_proc_sparc_ioport(void);
-
/* This points to the next to use virtual memory for DVMA mappings */
static struct resource _sparc_dvma = {
.name = "sparc_dvma", .start = DVMA_VADDR, .end = DVMA_END - 1
@@ -279,25 +277,6 @@ bool sparc_dma_free_resource(void *cpu_addr, size_t size)
return true;
}
-#ifdef CONFIG_SBUS
-
-void sbus_set_sbus64(struct device *dev, int x)
-{
- printk("sbus_set_sbus64: unsupported\n");
-}
-EXPORT_SYMBOL(sbus_set_sbus64);
-
-static int __init sparc_register_ioport(void)
-{
- register_proc_sparc_ioport();
-
- return 0;
-}
-
-arch_initcall(sparc_register_ioport);
-
-#endif /* CONFIG_SBUS */
-
/*
* IIep is write-through, not flushing on cpu to device transfer.
*
@@ -310,31 +289,3 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
if (dir != DMA_TO_DEVICE && !sparc_leon3_snooping_enabled())
leon_flush_dcache_all();
}
-
-#ifdef CONFIG_PROC_FS
-
-static int sparc_io_proc_show(struct seq_file *m, void *v)
-{
- struct resource *root = m->private, *r;
- const char *nm;
-
- for (r = root->child; r != NULL; r = r->sibling) {
- if ((nm = r->name) == NULL) nm = "???";
- seq_printf(m, "%016llx-%016llx: %s\n",
- (unsigned long long)r->start,
- (unsigned long long)r->end, nm);
- }
-
- return 0;
-}
-#endif /* CONFIG_PROC_FS */
-
-static void register_proc_sparc_ioport(void)
-{
-#ifdef CONFIG_PROC_FS
- proc_create_single_data("io_map", 0, NULL, sparc_io_proc_show,
- &sparc_iomap);
- proc_create_single_data("dvma_map", 0, NULL, sparc_io_proc_show,
- &_sparc_dvma);
-#endif
-}
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index ddb3b197d5e4..99ec26782bcc 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -96,11 +96,6 @@ static unsigned long of_bus_pci_get_flags(const u32 *addr, unsigned long flags)
return flags;
}
-static unsigned long of_bus_sbus_get_flags(const u32 *addr, unsigned long flags)
-{
- return IORESOURCE_MEM;
-}
-
/*
* AMBAPP bus specific translator
*/
@@ -145,15 +140,6 @@ static struct of_bus of_busses[] = {
.map = of_bus_pci_map,
.get_flags = of_bus_pci_get_flags,
},
- /* SBUS */
- {
- .name = "sbus",
- .addr_prop_name = "reg",
- .match = of_bus_sbus_match,
- .count_cells = of_bus_sbus_count_cells,
- .map = of_bus_default_map,
- .get_flags = of_bus_sbus_get_flags,
- },
/* AMBA */
{
.name = "ambapp",
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index 2d0bcc1d786e..a74f7fd3ba0c 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -492,7 +492,7 @@ config FB_GBE_MEM
config FB_SBUS
bool "SBUS and UPA framebuffers"
- depends on (FB = y) && SPARC
+ depends on (FB = y) && SBUS
help
Say Y if you want support for SBUS or UPA based frame buffer device.
diff --git a/sound/sparc/Kconfig b/sound/sparc/Kconfig
index 59b9f16e8dea..af2fb963a455 100644
--- a/sound/sparc/Kconfig
+++ b/sound/sparc/Kconfig
@@ -4,6 +4,7 @@
menuconfig SND_SPARC
bool "Sparc sound devices"
depends on SPARC
+ depends on SBUS
default y
help
Support for sound devices specific to Sun SPARC architectures.
--
2.34.1
From: Sam Ravnborg <[email protected]>
LEON do not have sbus iommu support - drop it.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/iommu.h | 2 -
arch/sparc/include/asm/iommu_32.h | 122 -----------
arch/sparc/kernel/ioport.c | 1 -
arch/sparc/mm/Makefile | 2 +-
arch/sparc/mm/iommu.c | 420 --------------------------------------
arch/sparc/mm/mm_32.h | 3 -
arch/sparc/mm/srmmu.c | 3 -
7 files changed, 1 insertion(+), 552 deletions(-)
diff --git a/arch/sparc/include/asm/iommu.h b/arch/sparc/include/asm/iommu.h
index 37935cb34865..ea07526ff476 100644
--- a/arch/sparc/include/asm/iommu.h
+++ b/arch/sparc/include/asm/iommu.h
@@ -3,7 +3,5 @@
#define ___ASM_SPARC_IOMMU_H
#if defined(__sparc__) && defined(__arch64__)
#include <asm/iommu_64.h>
-#else
-#include <asm/iommu_32.h>
#endif
#endif
diff --git a/arch/sparc/include/asm/iommu_32.h b/arch/sparc/include/asm/iommu_32.h
deleted file mode 100644
index af51cd5ea3c1..000000000000
--- a/arch/sparc/include/asm/iommu_32.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* iommu.h: Definitions for the sun4m IOMMU.
- *
- * Copyright (C) 1996 David S. Miller ([email protected])
- */
-#ifndef _SPARC_IOMMU_H
-#define _SPARC_IOMMU_H
-
-#include <asm/page.h>
-#include <asm/bitext.h>
-
-/* The iommu handles all virtual to physical address translations
- * that occur between the SBUS and physical memory. Access by
- * the cpu to IO registers and similar go over the mbus so are
- * translated by the on chip SRMMU. The iommu and the srmmu do
- * not need to have the same translations at all, in fact most
- * of the time the translations they handle are a disjunct set.
- * Basically the iommu handles all dvma sbus activity.
- */
-
-/* The IOMMU registers occupy three pages in IO space. */
-struct iommu_regs {
- /* First page */
- volatile unsigned long control; /* IOMMU control */
- volatile unsigned long base; /* Physical base of iopte page table */
- volatile unsigned long _unused1[3];
- volatile unsigned long tlbflush; /* write only */
- volatile unsigned long pageflush; /* write only */
- volatile unsigned long _unused2[1017];
- /* Second page */
- volatile unsigned long afsr; /* Async-fault status register */
- volatile unsigned long afar; /* Async-fault physical address */
- volatile unsigned long _unused3[2];
- volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
- volatile unsigned long sbuscfg1;
- volatile unsigned long sbuscfg2;
- volatile unsigned long sbuscfg3;
- volatile unsigned long mfsr; /* Memory-fault status register */
- volatile unsigned long mfar; /* Memory-fault physical address */
- volatile unsigned long _unused4[1014];
- /* Third page */
- volatile unsigned long mid; /* IOMMU module-id */
-};
-
-#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
-#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
-#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
-#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
-#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
-#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
-#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
-#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
-#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
-#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
-#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
-#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
-
-#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
-#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
-#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
-#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
-#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
-#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
-#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
-#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
-#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
-#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
-
-#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
-#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
-#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
-#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
- produced by this device as pure
- physical. */
-
-#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
-#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
-#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
-#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
-#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
- on the even word of the access, low bit
- indicated odd word caused the parity error */
-#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
-#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
-#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
-
-#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
-#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
-#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
-#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
-#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
-#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
-#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
-
-/* The format of an iopte in the page tables */
-#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
-#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
-#define IOPTE_WRITE 0x00000004 /* Writeable */
-#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
-#define IOPTE_WAZ 0x00000001 /* Write as zeros */
-
-struct iommu_struct {
- struct iommu_regs __iomem *regs;
- iopte_t *page_table;
- /* For convenience */
- unsigned long start; /* First managed virtual address */
- unsigned long end; /* Last managed virtual address */
-
- struct bit_map usemap;
-};
-
-static inline void iommu_invalidate(struct iommu_regs __iomem *regs)
-{
- sbus_writel(0, ®s->tlbflush);
-}
-
-static inline void iommu_invalidate_page(struct iommu_regs __iomem *regs, unsigned long ba)
-{
- sbus_writel(ba & PAGE_MASK, ®s->pageflush);
-}
-
-#endif /* !(_SPARC_IOMMU_H) */
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 745579a40785..9c4c72775274 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -48,7 +48,6 @@
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/dma.h>
-#include <asm/iommu.h>
#include <asm/leon.h>
static void __iomem *_sparc_ioremap(struct resource *res, u32 bus, u32 pa, int sz);
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index f8a897e24438..ad5c50aee517 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -7,7 +7,7 @@ asflags-y := -ansi
obj-$(CONFIG_SPARC64) += ultra.o tlb.o tsb.o
obj-y += fault_$(BITS).o
obj-y += init_$(BITS).o
-obj-$(CONFIG_SPARC32) += srmmu.o iommu.o
+obj-$(CONFIG_SPARC32) += srmmu.o
obj-$(CONFIG_SPARC32) += leon_mm.o
# Only used by sparc64
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
deleted file mode 100644
index 482e08df7bad..000000000000
--- a/arch/sparc/mm/iommu.c
+++ /dev/null
@@ -1,420 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * iommu.c: IOMMU specific routines for memory management.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- * Copyright (C) 1995,2002 Pete Zaitcev ([email protected])
- * Copyright (C) 1996 Eddie C. Dost ([email protected])
- * Copyright (C) 1997,1998 Jakub Jelinek ([email protected])
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/dma-map-ops.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-
-#include <asm/io.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <asm/bitext.h>
-#include <asm/iommu.h>
-#include <asm/dma.h>
-
-#include "mm_32.h"
-
-/*
- * This can be sized dynamically, but we will do this
- * only when we have a guidance about actual I/O pressures.
- */
-#define IOMMU_RNGE IOMMU_RNGE_256MB
-#define IOMMU_START 0xF0000000
-#define IOMMU_WINSIZE (256*1024*1024U)
-#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
-#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
-
-/*
- * Values precomputed according to CPU type.
- */
-static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
-static pgprot_t dvma_prot; /* Consistent mapping pte flags */
-
-#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
-#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
-
-static const struct dma_map_ops sbus_iommu_dma_gflush_ops;
-static const struct dma_map_ops sbus_iommu_dma_pflush_ops;
-
-static void __init sbus_iommu_init(struct platform_device *op)
-{
- struct iommu_struct *iommu;
- unsigned int impl, vers;
- unsigned long *bitmap;
- unsigned long control;
- unsigned long base;
- unsigned long tmp;
-
- iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
- if (!iommu) {
- prom_printf("Unable to allocate iommu structure\n");
- prom_halt();
- }
-
- iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
- "iommu_regs");
- if (!iommu->regs) {
- prom_printf("Cannot map IOMMU registers\n");
- prom_halt();
- }
-
- control = sbus_readl(&iommu->regs->control);
- impl = (control & IOMMU_CTRL_IMPL) >> 28;
- vers = (control & IOMMU_CTRL_VERS) >> 24;
- control &= ~(IOMMU_CTRL_RNGE);
- control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
- sbus_writel(control, &iommu->regs->control);
-
- iommu_invalidate(iommu->regs);
- iommu->start = IOMMU_START;
- iommu->end = 0xffffffff;
-
- /* Allocate IOMMU page table */
- /* Stupid alignment constraints give me a headache.
- We need 256K or 512K or 1M or 2M area aligned to
- its size and current gfp will fortunately give
- it to us. */
- tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
- if (!tmp) {
- prom_printf("Unable to allocate iommu table [0x%lx]\n",
- IOMMU_NPTES * sizeof(iopte_t));
- prom_halt();
- }
- iommu->page_table = (iopte_t *)tmp;
-
- /* Initialize new table. */
- memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
- flush_cache_all();
- flush_tlb_all();
-
- base = __pa((unsigned long)iommu->page_table) >> 4;
- sbus_writel(base, &iommu->regs->base);
- iommu_invalidate(iommu->regs);
-
- bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
- if (!bitmap) {
- prom_printf("Unable to allocate iommu bitmap [%d]\n",
- (int)(IOMMU_NPTES>>3));
- prom_halt();
- }
- bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
- iommu->usemap.num_colors = 1;
-
- printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
- impl, vers, iommu->page_table,
- (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
-
- op->dev.archdata.iommu = iommu;
-
- if (flush_page_for_dma_global)
- op->dev.dma_ops = &sbus_iommu_dma_gflush_ops;
- else
- op->dev.dma_ops = &sbus_iommu_dma_pflush_ops;
-}
-
-static int __init iommu_init(void)
-{
- struct device_node *dp;
-
- for_each_node_by_name(dp, "iommu") {
- struct platform_device *op = of_find_device_by_node(dp);
-
- sbus_iommu_init(op);
- of_propagate_archdata(op);
- }
-
- return 0;
-}
-
-subsys_initcall(iommu_init);
-
-/* Flush the iotlb entries to ram. */
-/* This could be better if we didn't have to flush whole pages. */
-static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
-{
- unsigned long start;
- unsigned long end;
-
- start = (unsigned long)iopte;
- end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
- start &= PAGE_MASK;
- while(start < end) {
- __flush_page_to_ram(start);
- start += PAGE_SIZE;
- }
-}
-
-static dma_addr_t __sbus_iommu_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t len, bool per_page_flush)
-{
- struct iommu_struct *iommu = dev->archdata.iommu;
- phys_addr_t paddr = page_to_phys(page) + offset;
- unsigned long off = paddr & ~PAGE_MASK;
- unsigned long npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
- unsigned long pfn = __phys_to_pfn(paddr);
- unsigned int busa, busa0;
- iopte_t *iopte, *iopte0;
- int ioptex, i;
-
- /* XXX So what is maxphys for us and how do drivers know it? */
- if (!len || len > 256 * 1024)
- return DMA_MAPPING_ERROR;
-
- /*
- * We expect unmapped highmem pages to be not in the cache.
- * XXX Is this a good assumption?
- * XXX What if someone else unmaps it here and races us?
- */
- if (per_page_flush && !PageHighMem(page)) {
- unsigned long vaddr, p;
-
- vaddr = (unsigned long)page_address(page) + offset;
- for (p = vaddr & PAGE_MASK; p < vaddr + len; p += PAGE_SIZE)
- flush_page_for_dma(p);
- }
-
- /* page color = pfn of page */
- ioptex = bit_map_string_get(&iommu->usemap, npages, pfn);
- if (ioptex < 0)
- panic("iommu out");
- busa0 = iommu->start + (ioptex << PAGE_SHIFT);
- iopte0 = &iommu->page_table[ioptex];
-
- busa = busa0;
- iopte = iopte0;
- for (i = 0; i < npages; i++) {
- iopte_val(*iopte) = MKIOPTE(pfn, IOPERM);
- iommu_invalidate_page(iommu->regs, busa);
- busa += PAGE_SIZE;
- iopte++;
- pfn++;
- }
-
- iommu_flush_iotlb(iopte0, npages);
- return busa0 + off;
-}
-
-static dma_addr_t sbus_iommu_map_page_gflush(struct device *dev,
- struct page *page, unsigned long offset, size_t len,
- enum dma_data_direction dir, unsigned long attrs)
-{
- flush_page_for_dma(0);
- return __sbus_iommu_map_page(dev, page, offset, len, false);
-}
-
-static dma_addr_t sbus_iommu_map_page_pflush(struct device *dev,
- struct page *page, unsigned long offset, size_t len,
- enum dma_data_direction dir, unsigned long attrs)
-{
- return __sbus_iommu_map_page(dev, page, offset, len, true);
-}
-
-static int __sbus_iommu_map_sg(struct device *dev, struct scatterlist *sgl,
- int nents, enum dma_data_direction dir, unsigned long attrs,
- bool per_page_flush)
-{
- struct scatterlist *sg;
- int j;
-
- for_each_sg(sgl, sg, nents, j) {
- sg->dma_address =__sbus_iommu_map_page(dev, sg_page(sg),
- sg->offset, sg->length, per_page_flush);
- if (sg->dma_address == DMA_MAPPING_ERROR)
- return -EIO;
- sg->dma_length = sg->length;
- }
-
- return nents;
-}
-
-static int sbus_iommu_map_sg_gflush(struct device *dev, struct scatterlist *sgl,
- int nents, enum dma_data_direction dir, unsigned long attrs)
-{
- flush_page_for_dma(0);
- return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, false);
-}
-
-static int sbus_iommu_map_sg_pflush(struct device *dev, struct scatterlist *sgl,
- int nents, enum dma_data_direction dir, unsigned long attrs)
-{
- return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, true);
-}
-
-static void sbus_iommu_unmap_page(struct device *dev, dma_addr_t dma_addr,
- size_t len, enum dma_data_direction dir, unsigned long attrs)
-{
- struct iommu_struct *iommu = dev->archdata.iommu;
- unsigned int busa = dma_addr & PAGE_MASK;
- unsigned long off = dma_addr & ~PAGE_MASK;
- unsigned int npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
- unsigned int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
- unsigned int i;
-
- BUG_ON(busa < iommu->start);
- for (i = 0; i < npages; i++) {
- iopte_val(iommu->page_table[ioptex + i]) = 0;
- iommu_invalidate_page(iommu->regs, busa);
- busa += PAGE_SIZE;
- }
- bit_map_clear(&iommu->usemap, ioptex, npages);
-}
-
-static void sbus_iommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
- int nents, enum dma_data_direction dir, unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sgl, sg, nents, i) {
- sbus_iommu_unmap_page(dev, sg->dma_address, sg->length, dir,
- attrs);
- sg->dma_address = 0x21212121;
- }
-}
-
-#ifdef CONFIG_SBUS
-static void *sbus_iommu_alloc(struct device *dev, size_t len,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- struct iommu_struct *iommu = dev->archdata.iommu;
- unsigned long va, addr, page, end, ret;
- iopte_t *iopte = iommu->page_table;
- iopte_t *first;
- int ioptex;
-
- /* XXX So what is maxphys for us and how do drivers know it? */
- if (!len || len > 256 * 1024)
- return NULL;
-
- len = PAGE_ALIGN(len);
- va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
- if (va == 0)
- return NULL;
-
- addr = ret = sparc_dma_alloc_resource(dev, len);
- if (!addr)
- goto out_free_pages;
-
- BUG_ON((va & ~PAGE_MASK) != 0);
- BUG_ON((addr & ~PAGE_MASK) != 0);
- BUG_ON((len & ~PAGE_MASK) != 0);
-
- /* page color = physical address */
- ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
- addr >> PAGE_SHIFT);
- if (ioptex < 0)
- panic("iommu out");
-
- iopte += ioptex;
- first = iopte;
- end = addr + len;
- while(addr < end) {
- page = va;
- {
- pmd_t *pmdp;
- pte_t *ptep;
-
- __flush_page_to_ram(page);
-
- pmdp = pmd_off_k(addr);
- ptep = pte_offset_kernel(pmdp, addr);
-
- set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
- }
- iopte_val(*iopte++) =
- MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
- addr += PAGE_SIZE;
- va += PAGE_SIZE;
- }
- /* P3: why do we need this?
- *
- * DAVEM: Because there are several aspects, none of which
- * are handled by a single interface. Some cpus are
- * completely not I/O DMA coherent, and some have
- * virtually indexed caches. The driver DMA flushing
- * methods handle the former case, but here during
- * IOMMU page table modifications, and usage of non-cacheable
- * cpu mappings of pages potentially in the cpu caches, we have
- * to handle the latter case as well.
- */
- flush_cache_all();
- iommu_flush_iotlb(first, len >> PAGE_SHIFT);
- flush_tlb_all();
- iommu_invalidate(iommu->regs);
-
- *dma_handle = iommu->start + (ioptex << PAGE_SHIFT);
- return (void *)ret;
-
-out_free_pages:
- free_pages(va, get_order(len));
- return NULL;
-}
-
-static void sbus_iommu_free(struct device *dev, size_t len, void *cpu_addr,
- dma_addr_t busa, unsigned long attrs)
-{
- struct iommu_struct *iommu = dev->archdata.iommu;
- iopte_t *iopte = iommu->page_table;
- struct page *page = virt_to_page(cpu_addr);
- int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
- unsigned long end;
-
- if (!sparc_dma_free_resource(cpu_addr, len))
- return;
-
- BUG_ON((busa & ~PAGE_MASK) != 0);
- BUG_ON((len & ~PAGE_MASK) != 0);
-
- iopte += ioptex;
- end = busa + len;
- while (busa < end) {
- iopte_val(*iopte++) = 0;
- busa += PAGE_SIZE;
- }
- flush_tlb_all();
- iommu_invalidate(iommu->regs);
- bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
-
- __free_pages(page, get_order(len));
-}
-#endif
-
-static const struct dma_map_ops sbus_iommu_dma_gflush_ops = {
-#ifdef CONFIG_SBUS
- .alloc = sbus_iommu_alloc,
- .free = sbus_iommu_free,
-#endif
- .map_page = sbus_iommu_map_page_gflush,
- .unmap_page = sbus_iommu_unmap_page,
- .map_sg = sbus_iommu_map_sg_gflush,
- .unmap_sg = sbus_iommu_unmap_sg,
-};
-
-static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
-#ifdef CONFIG_SBUS
- .alloc = sbus_iommu_alloc,
- .free = sbus_iommu_free,
-#endif
- .map_page = sbus_iommu_map_page_pflush,
- .unmap_page = sbus_iommu_unmap_page,
- .map_sg = sbus_iommu_map_sg_pflush,
- .unmap_sg = sbus_iommu_unmap_sg,
-};
-
-void __init ld_mmu_iommu(void)
-{
- dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
- ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
-}
diff --git a/arch/sparc/mm/mm_32.h b/arch/sparc/mm/mm_32.h
index 2c83b8ce742d..102e6a5162b0 100644
--- a/arch/sparc/mm/mm_32.h
+++ b/arch/sparc/mm/mm_32.h
@@ -14,6 +14,3 @@ extern int flush_page_for_dma_global;
extern void (*poke_srmmu)(void);
void __init srmmu_paging_init(void);
-
-/* iommu.c */
-void ld_mmu_iommu(void);
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 949247a6896b..dab71cd3fdb2 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -1023,10 +1023,7 @@ void __init load_mmu(void)
/* It really is const after this point. */
sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
&smp_cachetlb_ops;
-#endif
- ld_mmu_iommu();
-#ifdef CONFIG_SMP
leon_init_smp();
#endif
}
--
2.34.1
From: Sam Ravnborg <[email protected]>
With only LEON supported there is no need to run-time patch
the instructions to match ASI.
Move a few functions back to C with inline asm, now that
run-time patching is not needed.
Deleted a few functions that turns out not to be used rather
than re-implement them in C.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/asmmacro.h | 22 -----------
arch/sparc/include/asm/pgtsrmmu.h | 28 ++++++-------
arch/sparc/include/asm/sections.h | 3 --
arch/sparc/kernel/entry.S | 7 +---
arch/sparc/kernel/etrap_32.S | 15 +++----
arch/sparc/kernel/rtrap_32.S | 18 +++------
arch/sparc/kernel/vmlinux.lds.S | 5 ---
arch/sparc/kernel/wof.S | 18 +++------
arch/sparc/kernel/wuf.S | 21 ++++------
arch/sparc/mm/Makefile | 1 -
arch/sparc/mm/srmmu_access.S | 83 ---------------------------------------
11 files changed, 40 insertions(+), 181 deletions(-)
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
index 49aaf6f3bc55..d5782dbc7810 100644
--- a/arch/sparc/include/asm/asmmacro.h
+++ b/arch/sparc/include/asm/asmmacro.h
@@ -21,26 +21,4 @@
/* All traps low-level code here must end with this macro. */
#define RESTORE_ALL b ret_trap_entry; clr %l6;
-/* Support for run-time patching of single instructions.
- * This is used to handle the differences in the ASI for
- * MMUREGS for LEON and SUN.
- *
- * Sample:
- * LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %o0
- * SUN_PI_(lda [%g0] ASI_M_MMUREGS, %o0
- * PI == Patch Instruction
- *
- * For LEON we will use the first variant,
- * and for all other we will use the SUN variant.
- * The order is important.
- */
-#define LEON_PI(...) \
-662: __VA_ARGS__
-
-#define SUN_PI_(...) \
- .section .leon_1insn_patch, "ax"; \
- .word 662b; \
- __VA_ARGS__; \
- .previous
-
#endif /* !(_SPARC_ASMMACRO_H) */
diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h
index 7cb5cbc83211..69c28ff3c4c4 100644
--- a/arch/sparc/include/asm/pgtsrmmu.h
+++ b/arch/sparc/include/asm/pgtsrmmu.h
@@ -107,22 +107,22 @@ extern void *srmmu_nocache_pool;
#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
#define __nocache_fix(VADDR) ((__typeof__(VADDR))__va(__nocache_pa(VADDR)))
-/* Accessing the MMU control register. */
-unsigned int srmmu_get_mmureg(void);
-void srmmu_set_mmureg(unsigned long regval);
-void srmmu_set_ctable_ptr(unsigned long paddr);
-void srmmu_set_context(int context);
-int srmmu_get_context(void);
-unsigned int srmmu_get_fstatus(void);
-unsigned int srmmu_get_faddr(void);
-
-/* This is guaranteed on all SRMMU's. */
-static inline void srmmu_flush_whole_tlb(void)
+static inline void srmmu_set_ctable_ptr(unsigned long paddr)
{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
- "r" (0x400), /* Flush entire TLB!! */
- "i" (ASI_M_FLUSH_PROBE) : "memory");
+ paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
+ asm volatile("sta %0, [%1] %2\n\t" : : "r" (paddr), "r" (SRMMU_CTXTBL_PTR), "i" (ASI_LEON_MMUREGS) : "memory");
+}
+static inline void srmmu_set_context(int context)
+{
+ asm volatile("sta %0, [%1] %2\n\t" : : "r" (context), "r" (SRMMU_CTX_REG), "i" (ASI_LEON_MMUREGS) : "memory");
+}
+
+static inline int srmmu_get_context(void)
+{
+ register int retval;
+ asm volatile("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (SRMMU_CTX_REG), "i" (ASI_LEON_MMUREGS));
+ return retval;
}
#endif /* !(__ASSEMBLY__) */
diff --git a/arch/sparc/include/asm/sections.h b/arch/sparc/include/asm/sections.h
index 08f833453ab3..e9d28148850b 100644
--- a/arch/sparc/include/asm/sections.h
+++ b/arch/sparc/include/asm/sections.h
@@ -8,7 +8,4 @@
/* sparc entry point */
extern char _start[];
-extern char __leon_1insn_patch[];
-extern char __leon_1insn_patch_end[];
-
#endif
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index f158cbca3e62..18c67b4fb017 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -469,11 +469,8 @@ srmmu_fault:
mov 0x400, %l5
mov 0x300, %l4
-LEON_PI(lda [%l5] ASI_LEON_MMUREGS, %l6) ! read sfar first
-SUN_PI_(lda [%l5] ASI_M_MMUREGS, %l6) ! read sfar first
-
-LEON_PI(lda [%l4] ASI_LEON_MMUREGS, %l5) ! read sfsr last
-SUN_PI_(lda [%l4] ASI_M_MMUREGS, %l5) ! read sfsr last
+ lda [%l5] ASI_LEON_MMUREGS, %l6 ! read sfar first
+ lda [%l4] ASI_LEON_MMUREGS, %l5 ! read sfsr last
andn %l6, 0xfff, %l6
srl %l5, 6, %l5 ! and encode all info into l7
diff --git a/arch/sparc/kernel/etrap_32.S b/arch/sparc/kernel/etrap_32.S
index 9f243f918619..bb222459f097 100644
--- a/arch/sparc/kernel/etrap_32.S
+++ b/arch/sparc/kernel/etrap_32.S
@@ -235,8 +235,7 @@ tsetup_srmmu_stackchk:
cmp %glob_tmp, %sp
bleu,a 1f
-LEON_PI( lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
-SUN_PI_( lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
+ lda [%g0] ASI_LEON_MMUREGS, %glob_tmp ! read MMU control
trap_setup_user_stack_is_bolixed:
/* From user/kernel into invalid window w/bad user
@@ -251,24 +250,20 @@ trap_setup_user_stack_is_bolixed:
1:
/* Clear the fault status and turn on the no_fault bit. */
or %glob_tmp, 0x2, %glob_tmp ! or in no_fault bit
-LEON_PI(sta %glob_tmp, [%g0] ASI_LEON_MMUREGS) ! set it
-SUN_PI_(sta %glob_tmp, [%g0] ASI_M_MMUREGS) ! set it
+ sta %glob_tmp, [%g0] ASI_LEON_MMUREGS ! set it
/* Dump the registers and cross fingers. */
STORE_WINDOW(sp)
/* Clear the no_fault bit and check the status. */
andn %glob_tmp, 0x2, %glob_tmp
-LEON_PI(sta %glob_tmp, [%g0] ASI_LEON_MMUREGS)
-SUN_PI_(sta %glob_tmp, [%g0] ASI_M_MMUREGS)
+ sta %glob_tmp, [%g0] ASI_LEON_MMUREGS
mov AC_M_SFAR, %glob_tmp
-LEON_PI(lda [%glob_tmp] ASI_LEON_MMUREGS, %g0)
-SUN_PI_(lda [%glob_tmp] ASI_M_MMUREGS, %g0)
+ lda [%glob_tmp] ASI_LEON_MMUREGS, %g0
mov AC_M_SFSR, %glob_tmp
-LEON_PI(lda [%glob_tmp] ASI_LEON_MMUREGS, %glob_tmp)! save away status of winstore
-SUN_PI_(lda [%glob_tmp] ASI_M_MMUREGS, %glob_tmp) ! save away status of winstore
+ lda [%glob_tmp] ASI_LEON_MMUREGS, %glob_tmp ! save away status of winstore
andcc %glob_tmp, 0x2, %g0 ! did we fault?
bne trap_setup_user_stack_is_bolixed ! failure
diff --git a/arch/sparc/kernel/rtrap_32.S b/arch/sparc/kernel/rtrap_32.S
index 8931fe266346..a232b367c219 100644
--- a/arch/sparc/kernel/rtrap_32.S
+++ b/arch/sparc/kernel/rtrap_32.S
@@ -232,14 +232,11 @@ srmmu_rett_stackchk:
cmp %g1, %fp
bleu ret_trap_user_stack_is_bolixed
mov AC_M_SFSR, %g1
-LEON_PI(lda [%g1] ASI_LEON_MMUREGS, %g0)
-SUN_PI_(lda [%g1] ASI_M_MMUREGS, %g0)
+ lda [%g1] ASI_LEON_MMUREGS, %g0
-LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %g1)
-SUN_PI_(lda [%g0] ASI_M_MMUREGS, %g1)
+ lda [%g0] ASI_LEON_MMUREGS, %g1
or %g1, 0x2, %g1
-LEON_PI(sta %g1, [%g0] ASI_LEON_MMUREGS)
-SUN_PI_(sta %g1, [%g0] ASI_M_MMUREGS)
+ sta %g1, [%g0] ASI_LEON_MMUREGS
restore %g0, %g0, %g0
@@ -248,16 +245,13 @@ SUN_PI_(sta %g1, [%g0] ASI_M_MMUREGS)
save %g0, %g0, %g0
andn %g1, 0x2, %g1
-LEON_PI(sta %g1, [%g0] ASI_LEON_MMUREGS)
-SUN_PI_(sta %g1, [%g0] ASI_M_MMUREGS)
+ sta %g1, [%g0] ASI_LEON_MMUREGS
mov AC_M_SFAR, %g2
-LEON_PI(lda [%g2] ASI_LEON_MMUREGS, %g2)
-SUN_PI_(lda [%g2] ASI_M_MMUREGS, %g2)
+ lda [%g2] ASI_LEON_MMUREGS, %g2
mov AC_M_SFSR, %g1
-LEON_PI(lda [%g1] ASI_LEON_MMUREGS, %g1)
-SUN_PI_(lda [%g1] ASI_M_MMUREGS, %g1)
+ lda [%g1] ASI_LEON_MMUREGS, %g1
andcc %g1, 0x2, %g0
be ret_trap_userwins_ok
nop
diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S
index d317a843f7ea..1cc4d3e79321 100644
--- a/arch/sparc/kernel/vmlinux.lds.S
+++ b/arch/sparc/kernel/vmlinux.lds.S
@@ -113,11 +113,6 @@ SECTIONS
*(.sun4v_2insn_patch)
__sun4v_2insn_patch_end = .;
}
- .leon_1insn_patch : {
- __leon_1insn_patch = .;
- *(.leon_1insn_patch)
- __leon_1insn_patch_end = .;
- }
.swapper_tsb_phys_patch : {
__swapper_tsb_phys_patch = .;
*(.swapper_tsb_phys_patch)
diff --git a/arch/sparc/kernel/wof.S b/arch/sparc/kernel/wof.S
index 96a3a112423a..fe4cfd4abcd2 100644
--- a/arch/sparc/kernel/wof.S
+++ b/arch/sparc/kernel/wof.S
@@ -333,30 +333,24 @@ spwin_srmmu_stackchk:
mov AC_M_SFSR, %glob_tmp
/* Clear the fault status and turn on the no_fault bit. */
-LEON_PI(lda [%glob_tmp] ASI_LEON_MMUREGS, %g0) ! eat SFSR
-SUN_PI_(lda [%glob_tmp] ASI_M_MMUREGS, %g0) ! eat SFSR
+ lda [%glob_tmp] ASI_LEON_MMUREGS, %g0 ! eat SFSR
-LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
-SUN_PI_(lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
+ lda [%g0] ASI_LEON_MMUREGS, %glob_tmp ! read MMU control
or %glob_tmp, 0x2, %glob_tmp ! or in no_fault bit
-LEON_PI(sta %glob_tmp, [%g0] ASI_LEON_MMUREGS) ! set it
-SUN_PI_(sta %glob_tmp, [%g0] ASI_M_MMUREGS) ! set it
+ sta %glob_tmp, [%g0] ASI_LEON_MMUREGS ! set it
/* Dump the registers and cross fingers. */
STORE_WINDOW(sp)
/* Clear the no_fault bit and check the status. */
andn %glob_tmp, 0x2, %glob_tmp
-LEON_PI(sta %glob_tmp, [%g0] ASI_LEON_MMUREGS)
-SUN_PI_(sta %glob_tmp, [%g0] ASI_M_MMUREGS)
+ sta %glob_tmp, [%g0] ASI_LEON_MMUREGS
mov AC_M_SFAR, %glob_tmp
-LEON_PI(lda [%glob_tmp] ASI_LEON_MMUREGS, %g0)
-SUN_PI_(lda [%glob_tmp] ASI_M_MMUREGS, %g0)
+ lda [%glob_tmp] ASI_LEON_MMUREGS, %g0
mov AC_M_SFSR, %glob_tmp
-LEON_PI(lda [%glob_tmp] ASI_LEON_MMUREGS, %glob_tmp)
-SUN_PI_(lda [%glob_tmp] ASI_M_MMUREGS, %glob_tmp)
+ lda [%glob_tmp] ASI_LEON_MMUREGS, %glob_tmp
andcc %glob_tmp, 0x2, %g0 ! did we fault?
be,a spwin_finish_up + 0x4 ! cool beans, success
restore %g0, %g0, %g0
diff --git a/arch/sparc/kernel/wuf.S b/arch/sparc/kernel/wuf.S
index 1a4ca490e9c2..4c52b69d4b7a 100644
--- a/arch/sparc/kernel/wuf.S
+++ b/arch/sparc/kernel/wuf.S
@@ -255,19 +255,16 @@ srmmu_fwin_stackchk:
mov AC_M_SFSR, %l4
cmp %l5, %sp
bleu fwin_user_stack_is_bolixed
-LEON_PI( lda [%l4] ASI_LEON_MMUREGS, %g0) ! clear fault status
-SUN_PI_( lda [%l4] ASI_M_MMUREGS, %g0) ! clear fault status
+ lda [%l4] ASI_LEON_MMUREGS, %g0 ! clear fault status
/* The technique is, turn off faults on this processor,
* just let the load rip, then check the sfsr to see if
* a fault did occur. Then we turn on fault traps again
* and branch conditionally based upon what happened.
*/
-LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %l5) ! read mmu-ctrl reg
-SUN_PI_(lda [%g0] ASI_M_MMUREGS, %l5) ! read mmu-ctrl reg
+ lda [%g0] ASI_LEON_MMUREGS, %l5 ! read mmu-ctrl reg
or %l5, 0x2, %l5 ! turn on no-fault bit
-LEON_PI(sta %l5, [%g0] ASI_LEON_MMUREGS) ! store it
-SUN_PI_(sta %l5, [%g0] ASI_M_MMUREGS) ! store it
+ sta %l5, [%g0] ASI_LEON_MMUREGS ! store it
/* Cross fingers and go for it. */
LOAD_WINDOW(sp)
@@ -279,19 +276,15 @@ SUN_PI_(sta %l5, [%g0] ASI_M_MMUREGS) ! store it
/* LOCATION: Window 'T' */
-LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %twin_tmp1) ! load mmu-ctrl again
-SUN_PI_(lda [%g0] ASI_M_MMUREGS, %twin_tmp1) ! load mmu-ctrl again
+ lda [%g0] ASI_LEON_MMUREGS, %twin_tmp1 ! load mmu-ctrl again
andn %twin_tmp1, 0x2, %twin_tmp1 ! clear no-fault bit
-LEON_PI(sta %twin_tmp1, [%g0] ASI_LEON_MMUREGS) ! store it
-SUN_PI_(sta %twin_tmp1, [%g0] ASI_M_MMUREGS) ! store it
+ sta %twin_tmp1, [%g0] ASI_LEON_MMUREGS ! store it
mov AC_M_SFAR, %twin_tmp2
-LEON_PI(lda [%twin_tmp2] ASI_LEON_MMUREGS, %g0) ! read fault address
-SUN_PI_(lda [%twin_tmp2] ASI_M_MMUREGS, %g0) ! read fault address
+ lda [%twin_tmp2] ASI_LEON_MMUREGS, %g0 ! read fault address
mov AC_M_SFSR, %twin_tmp2
-LEON_PI(lda [%twin_tmp2] ASI_LEON_MMUREGS, %twin_tmp2) ! read fault status
-SUN_PI_(lda [%twin_tmp2] ASI_M_MMUREGS, %twin_tmp2) ! read fault status
+ lda [%twin_tmp2] ASI_LEON_MMUREGS, %twin_tmp2 ! read fault status
andcc %twin_tmp2, 0x2, %g0 ! did fault occur?
bne 1f ! yep, cleanup
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index 7b3ff6dd382e..f0560eea2958 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -8,7 +8,6 @@ obj-$(CONFIG_SPARC64) += ultra.o tlb.o tsb.o
obj-y += fault_$(BITS).o
obj-y += init_$(BITS).o
obj-$(CONFIG_SPARC32) += srmmu.o iommu.o io-unit.o
-obj-$(CONFIG_SPARC32) += srmmu_access.o
obj-$(CONFIG_SPARC32) += leon_mm.o
# Only used by sparc64
diff --git a/arch/sparc/mm/srmmu_access.S b/arch/sparc/mm/srmmu_access.S
deleted file mode 100644
index d8d2e644a5ca..000000000000
--- a/arch/sparc/mm/srmmu_access.S
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Assembler variants of srmmu access functions.
- * Implemented in assembler to allow run-time patching.
- * LEON uses a different ASI for MMUREGS than SUN.
- *
- * The leon_1insn_patch infrastructure is used
- * for the run-time patching.
- */
-
-#include <linux/linkage.h>
-
-#include <asm/asmmacro.h>
-#include <asm/pgtsrmmu.h>
-#include <asm/asi.h>
-
-/* unsigned int srmmu_get_mmureg(void) */
-ENTRY(srmmu_get_mmureg)
-LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %o0)
-SUN_PI_(lda [%g0] ASI_M_MMUREGS, %o0)
- retl
- nop
-ENDPROC(srmmu_get_mmureg)
-
-/* void srmmu_set_mmureg(unsigned long regval) */
-ENTRY(srmmu_set_mmureg)
-LEON_PI(sta %o0, [%g0] ASI_LEON_MMUREGS)
-SUN_PI_(sta %o0, [%g0] ASI_M_MMUREGS)
- retl
- nop
-ENDPROC(srmmu_set_mmureg)
-
-/* void srmmu_set_ctable_ptr(unsigned long paddr) */
-ENTRY(srmmu_set_ctable_ptr)
- /* paddr = ((paddr >> 4) & SRMMU_CTX_PMASK); */
- srl %o0, 4, %g1
- and %g1, SRMMU_CTX_PMASK, %g1
-
- mov SRMMU_CTXTBL_PTR, %g2
-LEON_PI(sta %g1, [%g2] ASI_LEON_MMUREGS)
-SUN_PI_(sta %g1, [%g2] ASI_M_MMUREGS)
- retl
- nop
-ENDPROC(srmmu_set_ctable_ptr)
-
-
-/* void srmmu_set_context(int context) */
-ENTRY(srmmu_set_context)
- mov SRMMU_CTX_REG, %g1
-LEON_PI(sta %o0, [%g1] ASI_LEON_MMUREGS)
-SUN_PI_(sta %o0, [%g1] ASI_M_MMUREGS)
- retl
- nop
-ENDPROC(srmmu_set_context)
-
-
-/* int srmmu_get_context(void) */
-ENTRY(srmmu_get_context)
- mov SRMMU_CTX_REG, %o0
-LEON_PI(lda [%o0] ASI_LEON_MMUREGS, %o0)
-SUN_PI_(lda [%o0] ASI_M_MMUREGS, %o0)
- retl
- nop
-ENDPROC(srmmu_get_context)
-
-
-/* unsigned int srmmu_get_fstatus(void) */
-ENTRY(srmmu_get_fstatus)
- mov SRMMU_FAULT_STATUS, %o0
-LEON_PI(lda [%o0] ASI_LEON_MMUREGS, %o0)
-SUN_PI_(lda [%o0] ASI_M_MMUREGS, %o0)
- retl
- nop
-ENDPROC(srmmu_get_fstatus)
-
-
-/* unsigned int srmmu_get_faddr(void) */
-ENTRY(srmmu_get_faddr)
- mov SRMMU_FAULT_ADDR, %o0
-LEON_PI(lda [%o0] ASI_LEON_MMUREGS, %o0)
-SUN_PI_(lda [%o0] ASI_M_MMUREGS, %o0)
- retl
- nop
-ENDPROC(srmmu_get_faddr)
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop sun4d specific support. Not used by LEON.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/io-unit.h | 59 --------
arch/sparc/include/asm/obio.h | 226 -------------------------------
arch/sparc/include/asm/sbi.h | 116 ----------------
arch/sparc/kernel/entry.S | 1 -
arch/sparc/kernel/ioport.c | 1 -
arch/sparc/mm/Makefile | 2 +-
arch/sparc/mm/io-unit.c | 283 ---------------------------------------
arch/sparc/mm/srmmu.c | 1 -
8 files changed, 1 insertion(+), 688 deletions(-)
diff --git a/arch/sparc/include/asm/io-unit.h b/arch/sparc/include/asm/io-unit.h
deleted file mode 100644
index 8c38f5b9f927..000000000000
--- a/arch/sparc/include/asm/io-unit.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* io-unit.h: Definitions for the sun4d IO-UNIT.
- *
- * Copyright (C) 1997,1998 Jakub Jelinek ([email protected])
- */
-#ifndef _SPARC_IO_UNIT_H
-#define _SPARC_IO_UNIT_H
-
-#include <linux/spinlock.h>
-#include <linux/pgtable.h>
-#include <asm/page.h>
-
-/* The io-unit handles all virtual to physical address translations
- * that occur between the SBUS and physical memory. Access by
- * the cpu to IO registers and similar go over the xdbus so are
- * translated by the on chip SRMMU. The io-unit and the srmmu do
- * not need to have the same translations at all, in fact most
- * of the time the translations they handle are a disjunct set.
- * Basically the io-unit handles all dvma sbus activity.
- */
-
-/* AIEEE, unlike the nice sun4m, these monsters have
- fixed DMA range 64M */
-
-#define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */
-#define IOUNIT_DMA_SIZE 0x04000000 /* 64M */
-/* We use last 1M for sparc_dvma_malloc */
-#define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */
-
-/* The format of an iopte in the external page tables */
-#define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
-#define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */
-/* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
- * XXX Actually, all you should need to do is find out where the registers
- * XXX are and copy over the sparc64 implementation I wrote. There may be
- * XXX some horrible hwbugs though, so be careful. -DaveM
- */
-#define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */
-#define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */
-#define IOUPTE_WRITE 0x00000004 /* Writeable */
-#define IOUPTE_VALID 0x00000002 /* IOPTE is valid */
-#define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */
-
-struct iounit_struct {
- unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
- spinlock_t lock;
- iopte_t __iomem *page_table;
- unsigned long rotor[3];
- unsigned long limit[4];
-};
-
-#define IOUNIT_BMAP1_START 0x00000000
-#define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
-#define IOUNIT_BMAP2_START IOUNIT_BMAP1_END
-#define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
-#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
-#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
-
-#endif /* !(_SPARC_IO_UNIT_H) */
diff --git a/arch/sparc/include/asm/obio.h b/arch/sparc/include/asm/obio.h
deleted file mode 100644
index 1b151f738b00..000000000000
--- a/arch/sparc/include/asm/obio.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
- *
- * Copyright (C) 1997 Jakub Jelinek <[email protected]>
- */
-
-#ifndef _SPARC_OBIO_H
-#define _SPARC_OBIO_H
-
-#include <asm/asi.h>
-
-/* This weird monster likes to use the very upper parts of
- 36bit PA for these things :) */
-
-/* CSR space (for each XDBUS)
- * ------------------------------------------------------------------------
- * | 0xFE | DEVID | | XDBUS ID | |
- * ------------------------------------------------------------------------
- * 35 28 27 20 19 10 9 8 7 0
- */
-
-#define CSR_BASE_ADDR 0xe0000000
-#define CSR_CPU_SHIFT (32 - 4 - 5)
-#define CSR_XDBUS_SHIFT 8
-
-#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
-
-/* ECSR space (not for each XDBUS)
- * ------------------------------------------------------------------------
- * | 0xF | DEVID[7:1] | |
- * ------------------------------------------------------------------------
- * 35 32 31 25 24 0
- */
-
-#define ECSR_BASE_ADDR 0x00000000
-#define ECSR_CPU_SHIFT (32 - 5)
-#define ECSR_DEV_SHIFT (32 - 8)
-
-#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
-#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
-
-/* Bus Watcher */
-#define BW_LOCAL_BASE 0xfff00000
-
-#define BW_CID 0x00000000
-#define BW_DBUS_CTRL 0x00000008
-#define BW_DBUS_DATA 0x00000010
-#define BW_CTRL 0x00001000
-#define BW_INTR_TABLE 0x00001040
-#define BW_INTR_TABLE_CLEAR 0x00001080
-#define BW_PRESCALER 0x000010c0
-#define BW_PTIMER_LIMIT 0x00002000
-#define BW_PTIMER_COUNTER2 0x00002004
-#define BW_PTIMER_NDLIMIT 0x00002008
-#define BW_PTIMER_CTRL 0x0000200c
-#define BW_PTIMER_COUNTER 0x00002010
-#define BW_TIMER_LIMIT 0x00003000
-#define BW_TIMER_COUNTER2 0x00003004
-#define BW_TIMER_NDLIMIT 0x00003008
-#define BW_TIMER_CTRL 0x0000300c
-#define BW_TIMER_COUNTER 0x00003010
-
-/* BW Control */
-#define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
-
-/* Boot Bus */
-#define BB_LOCAL_BASE 0xf0000000
-
-#define BB_STAT1 0x00100000
-#define BB_STAT2 0x00120000
-#define BB_STAT3 0x00140000
-#define BB_LEDS 0x002e0000
-
-/* Bits in BB_STAT2 */
-#define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
-#define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
-#define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
-#define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
-#define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
-
-/* Cache Controller */
-#define CC_BASE 0x1F00000
-#define CC_DATSTREAM 0x1F00000 /* Data stream register */
-#define CC_DATSIZE 0x1F0003F /* Size */
-#define CC_SRCSTREAM 0x1F00100 /* Source stream register */
-#define CC_DESSTREAM 0x1F00200 /* Destination stream register */
-#define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
-#define CC_IPEN 0x1F00406 /* Pending Interrupts */
-#define CC_IMSK 0x1F00506 /* Interrupt Mask */
-#define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
-#define CC_IGEN 0x1F00704 /* Generate Interrupt register */
-#define CC_STEST 0x1F00804 /* Internal self-test */
-#define CC_CREG 0x1F00A04 /* Control register */
-#define CC_SREG 0x1F00B00 /* Status register */
-#define CC_RREG 0x1F00C04 /* Reset register */
-#define CC_EREG 0x1F00E00 /* Error code register */
-#define CC_CID 0x1F00F04 /* Component ID */
-
-#ifndef __ASSEMBLY__
-
-static inline int bw_get_intr_mask(int sbus_level)
-{
- int mask;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (mask) :
- "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
- "i" (ASI_M_CTL));
- return mask;
-}
-
-static inline void bw_clear_intr_mask(int sbus_level, int mask)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (mask),
- "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
- "i" (ASI_M_CTL));
-}
-
-static inline unsigned int bw_get_prof_limit(int cpu)
-{
- unsigned int limit;
-
- __asm__ __volatile__ ("lda [%1] %2, %0" :
- "=r" (limit) :
- "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
- "i" (ASI_M_CTL));
- return limit;
-}
-
-static inline void bw_set_prof_limit(int cpu, unsigned int limit)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (limit),
- "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
- "i" (ASI_M_CTL));
-}
-
-static inline unsigned int bw_get_ctrl(int cpu)
-{
- unsigned int ctrl;
-
- __asm__ __volatile__ ("lda [%1] %2, %0" :
- "=r" (ctrl) :
- "r" (CSR_BASE(cpu) + BW_CTRL),
- "i" (ASI_M_CTL));
- return ctrl;
-}
-
-static inline void bw_set_ctrl(int cpu, unsigned int ctrl)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (ctrl),
- "r" (CSR_BASE(cpu) + BW_CTRL),
- "i" (ASI_M_CTL));
-}
-
-static inline unsigned int cc_get_ipen(void)
-{
- unsigned int pending;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (pending) :
- "r" (CC_IPEN),
- "i" (ASI_M_MXCC));
- return pending;
-}
-
-static inline void cc_set_iclr(unsigned int clear)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (clear),
- "r" (CC_ICLR),
- "i" (ASI_M_MXCC));
-}
-
-static inline unsigned int cc_get_imsk(void)
-{
- unsigned int mask;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (mask) :
- "r" (CC_IMSK),
- "i" (ASI_M_MXCC));
- return mask;
-}
-
-static inline void cc_set_imsk(unsigned int mask)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (mask),
- "r" (CC_IMSK),
- "i" (ASI_M_MXCC));
-}
-
-static inline unsigned int cc_get_imsk_other(int cpuid)
-{
- unsigned int mask;
-
- __asm__ __volatile__ ("lduha [%1] %2, %0" :
- "=r" (mask) :
- "r" (ECSR_BASE(cpuid) | CC_IMSK),
- "i" (ASI_M_CTL));
- return mask;
-}
-
-static inline void cc_set_imsk_other(int cpuid, unsigned int mask)
-{
- __asm__ __volatile__ ("stha %0, [%1] %2" : :
- "r" (mask),
- "r" (ECSR_BASE(cpuid) | CC_IMSK),
- "i" (ASI_M_CTL));
-}
-
-static inline void cc_set_igen(unsigned int gen)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (gen),
- "r" (CC_IGEN),
- "i" (ASI_M_MXCC));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_OBIO_H) */
diff --git a/arch/sparc/include/asm/sbi.h b/arch/sparc/include/asm/sbi.h
deleted file mode 100644
index 4d6026c1e446..000000000000
--- a/arch/sparc/include/asm/sbi.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * sbi.h: SBI (Sbus Interface on sun4d) definitions
- *
- * Copyright (C) 1997 Jakub Jelinek <[email protected]>
- */
-
-#ifndef _SPARC_SBI_H
-#define _SPARC_SBI_H
-
-#include <asm/obio.h>
-
-/* SBI */
-struct sbi_regs {
-/* 0x0000 */ u32 cid; /* Component ID */
-/* 0x0004 */ u32 ctl; /* Control */
-/* 0x0008 */ u32 status; /* Status */
- u32 _unused1;
-
-/* 0x0010 */ u32 cfg0; /* Slot0 config reg */
-/* 0x0014 */ u32 cfg1; /* Slot1 config reg */
-/* 0x0018 */ u32 cfg2; /* Slot2 config reg */
-/* 0x001c */ u32 cfg3; /* Slot3 config reg */
-
-/* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
-/* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
-/* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
-/* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
-
-/* 0x0030 */ u32 intr_state; /* Interrupt state */
-/* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
-/* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
-};
-
-#define SBI_CID 0x02800000
-#define SBI_CTL 0x02800004
-#define SBI_STATUS 0x02800008
-#define SBI_CFG0 0x02800010
-#define SBI_CFG1 0x02800014
-#define SBI_CFG2 0x02800018
-#define SBI_CFG3 0x0280001c
-#define SBI_STB0 0x02800020
-#define SBI_STB1 0x02800024
-#define SBI_STB2 0x02800028
-#define SBI_STB3 0x0280002c
-#define SBI_INTR_STATE 0x02800030
-#define SBI_INTR_TID 0x02800034
-#define SBI_INTR_DIAG 0x02800038
-
-/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
-#define SBI_CFG_BURST_MASK 0x0000001e
-
-/* How to make devid from sbi no */
-#define SBI2DEVID(sbino) ((sbino<<4)|2)
-
-/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
- *
- * +-------+-------+-------+-------+-------+-------+-------+-------+
- * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
- * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
- * Bits 31 27 23 19 15 11 7 3 0
- */
-
-
-#ifndef __ASSEMBLY__
-
-static inline int acquire_sbi(int devid, int mask)
-{
- __asm__ __volatile__ ("swapa [%2] %3, %0" :
- "=r" (mask) :
- "0" (mask),
- "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
- "i" (ASI_M_CTL));
- return mask;
-}
-
-static inline void release_sbi(int devid, int mask)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (mask),
- "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
- "i" (ASI_M_CTL));
-}
-
-static inline void set_sbi_tid(int devid, int targetid)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (targetid),
- "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
- "i" (ASI_M_CTL));
-}
-
-static inline int get_sbi_ctl(int devid, int cfgno)
-{
- int cfg;
-
- __asm__ __volatile__ ("lda [%1] %2, %0" :
- "=r" (cfg) :
- "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
- "i" (ASI_M_CTL));
- return cfg;
-}
-
-static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
-{
- __asm__ __volatile__ ("sta %0, [%1] %2" : :
- "r" (cfg),
- "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
- "i" (ASI_M_CTL));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_SBI_H) */
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index ea51a17ac3fc..bbbf30c60f1c 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -24,7 +24,6 @@
#include <asm/page.h>
#include <asm/winmacro.h>
#include <asm/signal.h>
-#include <asm/obio.h>
#include <asm/thread_info.h>
#include <asm/param.h>
#include <asm/unistd.h>
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index cf0ace29704a..745579a40785 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -49,7 +49,6 @@
#include <asm/pgalloc.h>
#include <asm/dma.h>
#include <asm/iommu.h>
-#include <asm/io-unit.h>
#include <asm/leon.h>
static void __iomem *_sparc_ioremap(struct resource *res, u32 bus, u32 pa, int sz);
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index f0560eea2958..f8a897e24438 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -7,7 +7,7 @@ asflags-y := -ansi
obj-$(CONFIG_SPARC64) += ultra.o tlb.o tsb.o
obj-y += fault_$(BITS).o
obj-y += init_$(BITS).o
-obj-$(CONFIG_SPARC32) += srmmu.o iommu.o io-unit.o
+obj-$(CONFIG_SPARC32) += srmmu.o iommu.o
obj-$(CONFIG_SPARC32) += leon_mm.o
# Only used by sparc64
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
deleted file mode 100644
index a2cfa8757795..000000000000
--- a/arch/sparc/mm/io-unit.c
+++ /dev/null
@@ -1,283 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * io-unit.c: IO-UNIT specific routines for memory management.
- *
- * Copyright (C) 1997,1998 Jakub Jelinek ([email protected])
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-#include <linux/bitops.h>
-#include <linux/dma-map-ops.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-
-#include <asm/io.h>
-#include <asm/io-unit.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <asm/dma.h>
-#include <asm/oplib.h>
-
-#include "mm_32.h"
-
-/* #define IOUNIT_DEBUG */
-#ifdef IOUNIT_DEBUG
-#define IOD(x) printk(x)
-#else
-#define IOD(x) do { } while (0)
-#endif
-
-#define IOPERM (IOUPTE_CACHE | IOUPTE_WRITE | IOUPTE_VALID)
-#define MKIOPTE(phys) __iopte((((phys)>>4) & IOUPTE_PAGE) | IOPERM)
-
-static const struct dma_map_ops iounit_dma_ops;
-
-static void __init iounit_iommu_init(struct platform_device *op)
-{
- struct iounit_struct *iounit;
- iopte_t __iomem *xpt;
- iopte_t __iomem *xptend;
-
- iounit = kzalloc(sizeof(struct iounit_struct), GFP_ATOMIC);
- if (!iounit) {
- prom_printf("SUN4D: Cannot alloc iounit, halting.\n");
- prom_halt();
- }
-
- iounit->limit[0] = IOUNIT_BMAP1_START;
- iounit->limit[1] = IOUNIT_BMAP2_START;
- iounit->limit[2] = IOUNIT_BMAPM_START;
- iounit->limit[3] = IOUNIT_BMAPM_END;
- iounit->rotor[1] = IOUNIT_BMAP2_START;
- iounit->rotor[2] = IOUNIT_BMAPM_START;
-
- xpt = of_ioremap(&op->resource[2], 0, PAGE_SIZE * 16, "XPT");
- if (!xpt) {
- prom_printf("SUN4D: Cannot map External Page Table.");
- prom_halt();
- }
-
- op->dev.archdata.iommu = iounit;
- iounit->page_table = xpt;
- spin_lock_init(&iounit->lock);
-
- xptend = iounit->page_table + (16 * PAGE_SIZE) / sizeof(iopte_t);
- for (; xpt < xptend; xpt++)
- sbus_writel(0, xpt);
-
- op->dev.dma_ops = &iounit_dma_ops;
-}
-
-static int __init iounit_init(void)
-{
- extern void sun4d_init_sbi_irq(void);
- struct device_node *dp;
-
- for_each_node_by_name(dp, "sbi") {
- struct platform_device *op = of_find_device_by_node(dp);
-
- iounit_iommu_init(op);
- of_propagate_archdata(op);
- }
-
- return 0;
-}
-
-subsys_initcall(iounit_init);
-
-/* One has to hold iounit->lock to call this */
-static unsigned long iounit_get_area(struct iounit_struct *iounit, unsigned long vaddr, int size)
-{
- int i, j, k, npages;
- unsigned long rotor, scan, limit;
- iopte_t iopte;
-
- npages = ((vaddr & ~PAGE_MASK) + size + (PAGE_SIZE-1)) >> PAGE_SHIFT;
-
- /* A tiny bit of magic ingredience :) */
- switch (npages) {
- case 1: i = 0x0231; break;
- case 2: i = 0x0132; break;
- default: i = 0x0213; break;
- }
-
- IOD(("iounit_get_area(%08lx,%d[%d])=", vaddr, size, npages));
-
-next: j = (i & 15);
- rotor = iounit->rotor[j - 1];
- limit = iounit->limit[j];
- scan = rotor;
-nexti: scan = find_next_zero_bit(iounit->bmap, limit, scan);
- if (scan + npages > limit) {
- if (limit != rotor) {
- limit = rotor;
- scan = iounit->limit[j - 1];
- goto nexti;
- }
- i >>= 4;
- if (!(i & 15))
- panic("iounit_get_area: Couldn't find free iopte slots for (%08lx,%d)\n", vaddr, size);
- goto next;
- }
- for (k = 1, scan++; k < npages; k++)
- if (test_bit(scan++, iounit->bmap))
- goto nexti;
- iounit->rotor[j - 1] = (scan < limit) ? scan : iounit->limit[j - 1];
- scan -= npages;
- iopte = MKIOPTE(__pa(vaddr & PAGE_MASK));
- vaddr = IOUNIT_DMA_BASE + (scan << PAGE_SHIFT) + (vaddr & ~PAGE_MASK);
- for (k = 0; k < npages; k++, iopte = __iopte(iopte_val(iopte) + 0x100), scan++) {
- set_bit(scan, iounit->bmap);
- sbus_writel(iopte_val(iopte), &iounit->page_table[scan]);
- }
- IOD(("%08lx\n", vaddr));
- return vaddr;
-}
-
-static dma_addr_t iounit_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t len, enum dma_data_direction dir,
- unsigned long attrs)
-{
- void *vaddr = page_address(page) + offset;
- struct iounit_struct *iounit = dev->archdata.iommu;
- unsigned long ret, flags;
-
- /* XXX So what is maxphys for us and how do drivers know it? */
- if (!len || len > 256 * 1024)
- return DMA_MAPPING_ERROR;
-
- spin_lock_irqsave(&iounit->lock, flags);
- ret = iounit_get_area(iounit, (unsigned long)vaddr, len);
- spin_unlock_irqrestore(&iounit->lock, flags);
- return ret;
-}
-
-static int iounit_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
- enum dma_data_direction dir, unsigned long attrs)
-{
- struct iounit_struct *iounit = dev->archdata.iommu;
- struct scatterlist *sg;
- unsigned long flags;
- int i;
-
- /* FIXME: Cache some resolved pages - often several sg entries are to the same page */
- spin_lock_irqsave(&iounit->lock, flags);
- for_each_sg(sgl, sg, nents, i) {
- sg->dma_address = iounit_get_area(iounit, (unsigned long) sg_virt(sg), sg->length);
- sg->dma_length = sg->length;
- }
- spin_unlock_irqrestore(&iounit->lock, flags);
- return nents;
-}
-
-static void iounit_unmap_page(struct device *dev, dma_addr_t vaddr, size_t len,
- enum dma_data_direction dir, unsigned long attrs)
-{
- struct iounit_struct *iounit = dev->archdata.iommu;
- unsigned long flags;
-
- spin_lock_irqsave(&iounit->lock, flags);
- len = ((vaddr & ~PAGE_MASK) + len + (PAGE_SIZE-1)) >> PAGE_SHIFT;
- vaddr = (vaddr - IOUNIT_DMA_BASE) >> PAGE_SHIFT;
- IOD(("iounit_release %08lx-%08lx\n", (long)vaddr, (long)len+vaddr));
- for (len += vaddr; vaddr < len; vaddr++)
- clear_bit(vaddr, iounit->bmap);
- spin_unlock_irqrestore(&iounit->lock, flags);
-}
-
-static void iounit_unmap_sg(struct device *dev, struct scatterlist *sgl,
- int nents, enum dma_data_direction dir, unsigned long attrs)
-{
- struct iounit_struct *iounit = dev->archdata.iommu;
- unsigned long flags, vaddr, len;
- struct scatterlist *sg;
- int i;
-
- spin_lock_irqsave(&iounit->lock, flags);
- for_each_sg(sgl, sg, nents, i) {
- len = ((sg->dma_address & ~PAGE_MASK) + sg->length + (PAGE_SIZE-1)) >> PAGE_SHIFT;
- vaddr = (sg->dma_address - IOUNIT_DMA_BASE) >> PAGE_SHIFT;
- IOD(("iounit_release %08lx-%08lx\n", (long)vaddr, (long)len+vaddr));
- for (len += vaddr; vaddr < len; vaddr++)
- clear_bit(vaddr, iounit->bmap);
- }
- spin_unlock_irqrestore(&iounit->lock, flags);
-}
-
-#ifdef CONFIG_SBUS
-static void *iounit_alloc(struct device *dev, size_t len,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- struct iounit_struct *iounit = dev->archdata.iommu;
- unsigned long va, addr, page, end, ret;
- pgprot_t dvma_prot;
- iopte_t __iomem *iopte;
-
- /* XXX So what is maxphys for us and how do drivers know it? */
- if (!len || len > 256 * 1024)
- return NULL;
-
- len = PAGE_ALIGN(len);
- va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
- if (!va)
- return NULL;
-
- addr = ret = sparc_dma_alloc_resource(dev, len);
- if (!addr)
- goto out_free_pages;
- *dma_handle = addr;
-
- dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
- end = PAGE_ALIGN((addr + len));
- while(addr < end) {
- page = va;
- {
- pmd_t *pmdp;
- pte_t *ptep;
- long i;
-
- pmdp = pmd_off_k(addr);
- ptep = pte_offset_kernel(pmdp, addr);
-
- set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
-
- i = ((addr - IOUNIT_DMA_BASE) >> PAGE_SHIFT);
-
- iopte = iounit->page_table + i;
- sbus_writel(iopte_val(MKIOPTE(__pa(page))), iopte);
- }
- addr += PAGE_SIZE;
- va += PAGE_SIZE;
- }
- flush_cache_all();
- flush_tlb_all();
-
- return (void *)ret;
-
-out_free_pages:
- free_pages(va, get_order(len));
- return NULL;
-}
-
-static void iounit_free(struct device *dev, size_t size, void *cpu_addr,
- dma_addr_t dma_addr, unsigned long attrs)
-{
- /* XXX Somebody please fill this in */
-}
-#endif
-
-static const struct dma_map_ops iounit_dma_ops = {
-#ifdef CONFIG_SBUS
- .alloc = iounit_alloc,
- .free = iounit_free,
-#endif
- .map_page = iounit_map_page,
- .unmap_page = iounit_unmap_page,
- .map_sg = iounit_map_sg,
- .unmap_sg = iounit_unmap_sg,
-};
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 4a3778549c6f..949247a6896b 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -26,7 +26,6 @@
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
-#include <asm/io-unit.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/bitext.h>
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop all code used to support sun4m irqs.
Update entry.S to call the leon_nmi function.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/kernel/Makefile | 1 -
arch/sparc/kernel/entry.S | 29 ++---
arch/sparc/kernel/irq.h | 46 +-------
arch/sparc/kernel/irq_32.c | 6 +-
arch/sparc/kernel/kernel.h | 4 -
arch/sparc/kernel/leon_kernel.c | 10 +-
arch/sparc/kernel/sun4m_irq.c | 238 ----------------------------------------
7 files changed, 23 insertions(+), 311 deletions(-)
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 50d696c8a9d2..fd3d1ebfb1ea 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -28,7 +28,6 @@ obj-y += traps_$(BITS).o
# IRQ
obj-y += irq_$(BITS).o
-obj-$(CONFIG_SPARC32) += sun4m_irq.o
obj-y += process_$(BITS).o
obj-y += process.o
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index bbbf30c60f1c..3de018a44915 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -427,36 +427,21 @@ setcc_trap_handler:
jmp %l2 ! advance over trap instruction
rett %l2 + 0x4 ! like this...
-sun4m_nmi_error:
+nmi_error:
/* NMI async memory error handling. */
- sethi %hi(0x80000000), %l4
- sethi %hi(sun4m_irq_global), %o5
- ld [%o5 + %lo(sun4m_irq_global)], %l5
- st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000
- WRITE_PAUSE
- ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
- WRITE_PAUSE
+#ifndef CONFIG_SMP
+ .align 4
+ .globl linux_trap_ipi15_leon
+linux_trap_ipi15_leon:
+ SAVE_ALL
or %l0, PSR_PIL, %l4
wr %l4, 0x0, %psr
WRITE_PAUSE
wr %l4, PSR_ET, %psr
WRITE_PAUSE
- call sun4m_nmi
+ call leon_nmi
nop
- st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000
- WRITE_PAUSE
- ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
- WRITE_PAUSE
RESTORE_ALL
-
-#ifndef CONFIG_SMP
- .align 4
- .globl linux_trap_ipi15_leon
-linux_trap_ipi15_leon:
- SAVE_ALL
-
- ba sun4m_nmi_error
- nop
#endif /* CONFIG_SMP */
.align 4
diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h
index 8a0b314c8299..f0aacc5c9ea6 100644
--- a/arch/sparc/kernel/irq.h
+++ b/arch/sparc/kernel/irq.h
@@ -10,39 +10,14 @@ struct irq_bucket {
unsigned int pil;
};
-#define SUN4M_HARD_INT(x) (0x000000001 << (x))
-#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
-
-#define SUN4D_MAX_BOARD 10
-#define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5)
+#define MAX_BOARD 10
+#define MAX_IRQ ((MAX_BOARD + 2) << 5)
/* Map between the irq identifier used in hw to the
* irq_bucket. The map is sufficient large to hold
* the sun4d hw identifiers.
*/
-extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
-
-
-/* sun4m specific type definitions */
-
-/* This maps direct to CPU specific interrupt registers */
-struct sun4m_irq_percpu {
- u32 pending;
- u32 clear;
- u32 set;
-};
-
-/* This maps direct to global interrupt registers */
-struct sun4m_irq_global {
- u32 pending;
- u32 mask;
- u32 mask_clear;
- u32 mask_set;
- u32 interrupt_target;
-};
-
-extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
-extern struct sun4m_irq_global __iomem *sun4m_irq_global;
+extern struct irq_bucket *irq_map[MAX_IRQ];
unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
void irq_link(unsigned int irq);
@@ -51,22 +26,9 @@ void handler_irq(unsigned int pil, struct pt_regs *regs);
unsigned long leon_get_irqmask(unsigned int irq);
-/* sun4m_irq.c */
-void sun4m_nmi(struct pt_regs *regs);
-
-/* sun4d_irq.c */
-void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs);
-
/* leon_kernel.c */
void leon_clear_clock_irq(void);
void leon_load_profile_irq(int cpu, unsigned int limit);
u32 leon_cycles_offset(void);
-#ifdef CONFIG_SMP
-
-/* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */
-#define SUN4D_IPI_IRQ 13
-
-void sun4d_ipi_interrupt(void);
-
-#endif
+void leon_nmi(struct pt_regs *regs);
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index f76f57073323..5bd64828e8a0 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -111,7 +111,7 @@ static struct irq_bucket irq_table[NR_IRQS];
static DEFINE_SPINLOCK(irq_table_lock);
/* Map between the irq identifier used in hw to the irq_bucket. */
-struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
+struct irq_bucket *irq_map[MAX_IRQ];
/* Protect access to irq_map */
static DEFINE_SPINLOCK(irq_map_lock);
@@ -162,7 +162,7 @@ void irq_link(unsigned int irq)
p = &irq_table[irq];
pil = p->pil;
- BUG_ON(pil >= SUN4D_MAX_IRQ);
+ BUG_ON(pil >= MAX_IRQ);
p->next = irq_map[pil];
irq_map[pil] = p;
@@ -179,7 +179,7 @@ void irq_unlink(unsigned int irq)
spin_lock_irqsave(&irq_map_lock, flags);
p = &irq_table[irq];
- BUG_ON(p->pil >= SUN4D_MAX_IRQ);
+ BUG_ON(p->pil >= MAX_IRQ);
pnext = &irq_map[p->pil];
while (*pnext != p)
pnext = &(*pnext)->next;
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 4fcd782f16a7..c2aaddedf097 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -92,10 +92,6 @@ extern spinlock_t irq_action_lock;
void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs);
-/* sun4m_irq.c */
-void sun4m_unmask_profile_irq(void);
-void sun4m_clear_profile_irq(int cpu);
-
/* leon_smp.c */
void leon_cpu_pre_starting(void *arg);
void leon_cpu_pre_online(void *arg);
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index fa9cdaffdc6b..1bdf08db3037 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -9,6 +9,7 @@
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/interrupt.h>
+#include <linux/sched/debug.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
@@ -269,8 +270,15 @@ u32 leon_cycles_offset(void)
return off;
}
-#ifdef CONFIG_SMP
+/* NMI interrupt (15) */
+void leon_nmi(struct pt_regs *regs)
+{
+ printk(KERN_ERR "Aieee: NMI received!\n");
+ show_regs(regs);
+ prom_halt();
+}
+#ifdef CONFIG_SMP
/* smp clockevent irq */
static irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused)
{
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
deleted file mode 100644
index 1a220a2b9ac3..000000000000
--- a/arch/sparc/kernel/sun4m_irq.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * sun4m irq support
- *
- * djhr: Hacked out of irq.c into a CPU dependent version.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- * Copyright (C) 1995 Miguel de Icaza ([email protected])
- * Copyright (C) 1995 Pete A. Zaitcev ([email protected])
- * Copyright (C) 1996 Dave Redman ([email protected])
- */
-
-#include <linux/slab.h>
-#include <linux/sched/debug.h>
-#include <linux/pgtable.h>
-
-#include <asm/timer.h>
-#include <asm/traps.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/cacheflush.h>
-
-#include "irq.h"
-#include "kernel.h"
-
-/* Sample sun4m IRQ layout:
- *
- * 0x22 - Power
- * 0x24 - ESP SCSI
- * 0x26 - Lance ethernet
- * 0x2b - Floppy
- * 0x2c - Zilog uart
- * 0x32 - SBUS level 0
- * 0x33 - Parallel port, SBUS level 1
- * 0x35 - SBUS level 2
- * 0x37 - SBUS level 3
- * 0x39 - Audio, Graphics card, SBUS level 4
- * 0x3b - SBUS level 5
- * 0x3d - SBUS level 6
- *
- * Each interrupt source has a mask bit in the interrupt registers.
- * When the mask bit is set, this blocks interrupt deliver. So you
- * clear the bit to enable the interrupt.
- *
- * Interrupts numbered less than 0x10 are software triggered interrupts
- * and unused by Linux.
- *
- * Interrupt level assignment on sun4m:
- *
- * level source
- * ------------------------------------------------------------
- * 1 softint-1
- * 2 softint-2, VME/SBUS level 1
- * 3 softint-3, VME/SBUS level 2
- * 4 softint-4, onboard SCSI
- * 5 softint-5, VME/SBUS level 3
- * 6 softint-6, onboard ETHERNET
- * 7 softint-7, VME/SBUS level 4
- * 8 softint-8, onboard VIDEO
- * 9 softint-9, VME/SBUS level 5, Module Interrupt
- * 10 softint-10, system counter/timer
- * 11 softint-11, VME/SBUS level 6, Floppy
- * 12 softint-12, Keyboard/Mouse, Serial
- * 13 softint-13, VME/SBUS level 7, ISDN Audio
- * 14 softint-14, per-processor counter/timer
- * 15 softint-15, Asynchronous Errors (broadcast)
- *
- * Each interrupt source is masked distinctly in the sun4m interrupt
- * registers. The PIL level alone is therefore ambiguous, since multiple
- * interrupt sources map to a single PIL.
- *
- * This ambiguity is resolved in the 'intr' property for device nodes
- * in the OF device tree. Each 'intr' property entry is composed of
- * two 32-bit words. The first word is the IRQ priority value, which
- * is what we're intersted in. The second word is the IRQ vector, which
- * is unused.
- *
- * The low 4 bits of the IRQ priority indicate the PIL, and the upper
- * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
- * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
- *
- * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
- * whereas a value of 0x33 is SBUS level 2. Here are some sample
- * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
- * Tadpole S3 GX systems.
- *
- * esp: 0x24 onboard ESP SCSI
- * le: 0x26 onboard Lance ETHERNET
- * p9100: 0x32 SBUS level 1 P9100 video
- * bpp: 0x33 SBUS level 2 BPP parallel port device
- * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
- * SUNW,leo: 0x39 SBUS level 5 LEO video
- * pcmcia: 0x3b SBUS level 6 PCMCIA controller
- * uctrl: 0x3b SBUS level 6 UCTRL device
- * modem: 0x3d SBUS level 7 MODEM
- * zs: 0x2c onboard keyboard/mouse/serial
- * floppy: 0x2b onboard Floppy
- * power: 0x22 onboard power device (XXX unknown mask bit XXX)
- */
-
-
-/* Code in entry.S needs to get at these register mappings. */
-struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
-struct sun4m_irq_global __iomem *sun4m_irq_global;
-
-struct sun4m_handler_data {
- bool percpu;
- long mask;
-};
-
-/* Dave Redman ([email protected])
- * The sun4m interrupt registers.
- */
-#define SUN4M_INT_ENABLE 0x80000000
-#define SUN4M_INT_E14 0x00000080
-#define SUN4M_INT_E10 0x00080000
-
-#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
-#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
-#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
-#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
-#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
-#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
-#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
-#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
-#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
-#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
-#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
-#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
-#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
-#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
-#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
-#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
-
-#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
- SUN4M_INT_M2S_WRITE_ERR | \
- SUN4M_INT_ECC_ERR | \
- SUN4M_INT_VME_ERR)
-
-#define SUN4M_INT_SBUS(x) (1 << (x+7))
-#define SUN4M_INT_VME(x) (1 << (x))
-
-/* Interrupt levels used by OBP */
-#define OBP_INT_LEVEL_SOFT 0x10
-#define OBP_INT_LEVEL_ONBOARD 0x20
-#define OBP_INT_LEVEL_SBUS 0x30
-#define OBP_INT_LEVEL_VME 0x40
-
-#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
-#define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
-
-static unsigned long sun4m_imask[0x50] = {
- /* 0x00 - SMP */
- 0, SUN4M_SOFT_INT(1),
- SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
- SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
- SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
- SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
- SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
- SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
- SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
- /* 0x10 - soft */
- 0, SUN4M_SOFT_INT(1),
- SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
- SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
- SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
- SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
- SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
- SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
- SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
- /* 0x20 - onboard */
- 0, 0, 0, 0,
- SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
- SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
- SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
- (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
- SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
- /* 0x30 - sbus */
- 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
- 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
- 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
- 0, SUN4M_INT_SBUS(6), 0, 0,
- /* 0x40 - vme */
- 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
- 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
- 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
- 0, SUN4M_INT_VME(6), 0, 0
-};
-
-struct sun4m_timer_percpu {
- u32 l14_limit;
- u32 l14_count;
- u32 l14_limit_noclear;
- u32 user_timer_start_stop;
-};
-
-static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
-
-void sun4m_nmi(struct pt_regs *regs)
-{
- unsigned long afsr, afar, si;
-
- printk(KERN_ERR "Aieee: sun4m NMI received!\n");
- /* XXX HyperSparc hack XXX */
- __asm__ __volatile__("mov 0x500, %%g1\n\t"
- "lda [%%g1] 0x4, %0\n\t"
- "mov 0x600, %%g1\n\t"
- "lda [%%g1] 0x4, %1\n\t" :
- "=r" (afsr), "=r" (afar));
- printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
- si = sbus_readl(&sun4m_irq_global->pending);
- printk(KERN_ERR "si=%08lx\n", si);
- if (si & SUN4M_INT_MODULE_ERR)
- printk(KERN_ERR "Module async error\n");
- if (si & SUN4M_INT_M2S_WRITE_ERR)
- printk(KERN_ERR "MBus/SBus async error\n");
- if (si & SUN4M_INT_ECC_ERR)
- printk(KERN_ERR "ECC memory error\n");
- if (si & SUN4M_INT_VME_ERR)
- printk(KERN_ERR "VME async error\n");
- printk(KERN_ERR "you lose buddy boy...\n");
- show_regs(regs);
- prom_halt();
-}
-
-void sun4m_unmask_profile_irq(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
- local_irq_restore(flags);
-}
-
-void sun4m_clear_profile_irq(int cpu)
-{
- sbus_readl(&timers_percpu[cpu]->l14_limit);
-}
--
2.34.1
From: Sam Ravnborg <[email protected]>
Drop mmu models not used by LEON, including their header files.
This includes removal of unused includes in various files to fix the
build.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
arch/sparc/include/asm/mxcc.h | 138 -------
arch/sparc/include/asm/ross.h | 192 ---------
arch/sparc/include/asm/swift.h | 107 -----
arch/sparc/include/asm/tsunami.h | 65 ---
arch/sparc/include/asm/turbosparc.h | 126 ------
arch/sparc/include/asm/viking.h | 255 ------------
arch/sparc/kernel/entry.S | 1 -
arch/sparc/mm/Makefile | 1 -
arch/sparc/mm/hypersparc.S | 414 -------------------
arch/sparc/mm/io-unit.c | 1 -
arch/sparc/mm/iommu.c | 31 +-
arch/sparc/mm/mm_32.h | 1 -
arch/sparc/mm/srmmu.c | 776 +-----------------------------------
arch/sparc/mm/swift.S | 256 ------------
arch/sparc/mm/tsunami.S | 132 ------
arch/sparc/mm/viking.S | 284 -------------
16 files changed, 21 insertions(+), 2759 deletions(-)
diff --git a/arch/sparc/include/asm/mxcc.h b/arch/sparc/include/asm/mxcc.h
deleted file mode 100644
index 3a2561bea4dd..000000000000
--- a/arch/sparc/include/asm/mxcc.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * mxcc.h: Definitions of the Viking MXCC registers
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_MXCC_H
-#define _SPARC_MXCC_H
-
-/* These registers are accessed through ASI 0x2. */
-#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
-#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
-#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
-#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
-#define MXCC_STEST 0x1C00804 /* Internal self-test */
-#define MXCC_CREG 0x1C00A04 /* Control register */
-#define MXCC_SREG 0x1C00B00 /* Status register */
-#define MXCC_RREG 0x1C00C04 /* Reset register */
-#define MXCC_EREG 0x1C00E00 /* Error code register */
-#define MXCC_PREG 0x1C00F04 /* Address port register */
-
-/* Some MXCC constants. */
-#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
-
-/* The MXCC Control Register:
- *
- * ----------------------------------------------------------------------
- * | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
- * ----------------------------------------------------------------------
- * 31 10 9 8-6 5 4 3 2 1-0
- *
- * RRC: Controls what you read from MXCC_RMCOUNT reg.
- * 0=Misses 1=References
- * PRE: Prefetch enable
- * MCE: Multiple Command Enable
- * PARE: Parity enable
- * ECE: External cache enable
- */
-
-#define MXCC_CTL_RRC 0x00000200
-#define MXCC_CTL_PRE 0x00000020
-#define MXCC_CTL_MCE 0x00000010
-#define MXCC_CTL_PARE 0x00000008
-#define MXCC_CTL_ECE 0x00000004
-
-/* The MXCC Error Register:
- *
- * --------------------------------------------------------
- * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
- * --------------------------------------------------------
- * 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
- *
- * ME: Multiple Errors have occurred
- * CE: Cache consistency Error
- * PEW: Parity Error during a Write operation
- * PEE: Parity Error involving the External cache
- * ASE: ASynchronous Error
- * EIV: This register is toast
- * MOPC: MXCC Operation Code for instance causing error
- * ECODE: The Error CODE
- * PRIV: A privileged mode error? 0=no 1=yes
- * HPADDR: High PhysicalADDRess bits (35-32)
- */
-
-#define MXCC_ERR_ME 0x80000000
-#define MXCC_ERR_CE 0x20000000
-#define MXCC_ERR_PEW 0x10000000
-#define MXCC_ERR_PEE 0x08000000
-#define MXCC_ERR_ASE 0x04000000
-#define MXCC_ERR_EIV 0x02000000
-#define MXCC_ERR_MOPC 0x01FF8000
-#define MXCC_ERR_ECODE 0x00007F80
-#define MXCC_ERR_PRIV 0x00000040
-#define MXCC_ERR_HPADDR 0x0000000f
-
-/* The MXCC Port register:
- *
- * -----------------------------------------------------
- * | | MID | |
- * -----------------------------------------------------
- * 31 21 20-18 17 0
- *
- * MID: The moduleID of the cpu your read this from.
- */
-
-#ifndef __ASSEMBLY__
-
-static inline void mxcc_set_stream_src(unsigned long *paddr)
-{
- unsigned long data0 = paddr[0];
- unsigned long data1 = paddr[1];
-
- __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (data0), "r" (data1),
- "r" (MXCC_SRCSTREAM),
- "i" (ASI_M_MXCC) : "g2", "g3");
-}
-
-static inline void mxcc_set_stream_dst(unsigned long *paddr)
-{
- unsigned long data0 = paddr[0];
- unsigned long data1 = paddr[1];
-
- __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (data0), "r" (data1),
- "r" (MXCC_DESSTREAM),
- "i" (ASI_M_MXCC) : "g2", "g3");
-}
-
-static inline unsigned long mxcc_get_creg(void)
-{
- unsigned long mxcc_control;
-
- __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
- "set 0xffffffff, %%g3\n\t"
- "stda %%g2, [%1] %2\n\t"
- "lda [%3] %2, %0\n\t" :
- "=r" (mxcc_control) :
- "r" (MXCC_EREG), "i" (ASI_M_MXCC),
- "r" (MXCC_CREG) : "g2", "g3");
- return mxcc_control;
-}
-
-static inline void mxcc_set_creg(unsigned long mxcc_control)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
- "r" (mxcc_control), "r" (MXCC_CREG),
- "i" (ASI_M_MXCC));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_MXCC_H) */
diff --git a/arch/sparc/include/asm/ross.h b/arch/sparc/include/asm/ross.h
deleted file mode 100644
index 79a54d66a2c0..000000000000
--- a/arch/sparc/include/asm/ross.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * ross.h: Ross module specific definitions and defines.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_ROSS_H
-#define _SPARC_ROSS_H
-
-#include <asm/asi.h>
-#include <asm/page.h>
-
-/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
- * field has '1111'.
- */
-
-/* The MMU control register fields on the HyperSparc.
- *
- * -----------------------------------------------------------------
- * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
- * -----------------------------------------------------------------
- * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
- *
- * Phew, lots of fields there ;-)
- *
- * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
- * SE: Snoop Enable, turns on bus snooping for cache activity if one.
- * WBE: Write Buffer Enable, one turns it on.
- * MID: The ModuleID of the chip for MBus transactions.
- * BM: Boot-Mode. One indicates the MMU is in boot mode.
- * C: Indicates whether accesses are cachable while the MMU is
- * disabled.
- * CS: Cache Size -- 0 = 128k, 1 = 256k
- * MR: Memory Reflection, one indicates that the memory bus connected
- * to the MBus supports memory reflection.
- * CM: Cache Mode -- 0 = write-through, 1 = copy-back
- * CE: Cache Enable -- 0 = no caching, 1 = cache is on
- * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
- * 1 = faults from supervisor mode do not generate traps
- * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
- */
-
-#define HYPERSPARC_CWENABLE 0x00200000
-#define HYPERSPARC_SBENABLE 0x00100000
-#define HYPERSPARC_WBENABLE 0x00080000
-#define HYPERSPARC_MIDMASK 0x00078000
-#define HYPERSPARC_BMODE 0x00004000
-#define HYPERSPARC_ACENABLE 0x00002000
-#define HYPERSPARC_CSIZE 0x00001000
-#define HYPERSPARC_MRFLCT 0x00000800
-#define HYPERSPARC_CMODE 0x00000400
-#define HYPERSPARC_CENABLE 0x00000100
-#define HYPERSPARC_NFAULT 0x00000002
-#define HYPERSPARC_MENABLE 0x00000001
-
-
-/* The ICCR instruction cache register on the HyperSparc.
- *
- * -----------------------------------------------
- * | | FTD | ICE |
- * -----------------------------------------------
- * 31 1 0
- *
- * This register is accessed using the V8 'wrasr' and 'rdasr'
- * opcodes, since not all assemblers understand them and those
- * that do use different semantics I will just hard code the
- * instruction with a '.word' statement.
- *
- * FTD: If set to one flush instructions executed during an
- * instruction cache hit occurs, the corresponding line
- * for said cache-hit is invalidated. If FTD is zero,
- * an unimplemented 'flush' trap will occur when any
- * flush is executed by the processor.
- *
- * ICE: If set to one, the instruction cache is enabled. If
- * zero, the cache will not be used for instruction fetches.
- *
- * All other bits are read as zeros, and writes to them have no
- * effect.
- *
- * Wheee, not many assemblers understand the %iccr register nor
- * the generic asr r/w instructions.
- *
- * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
- *
- * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
- *
- * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
- *
- * 0x b f 8 0 6 0 0 0 ! 0xbf806000
- *
- */
-
-#define HYPERSPARC_ICCR_FTD 0x00000002
-#define HYPERSPARC_ICCR_ICE 0x00000001
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned int get_ross_icr(void)
-{
- unsigned int icreg;
-
- __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
- "mov %%g1, %0\n\t"
- : "=r" (icreg)
- : /* no inputs */
- : "g1", "memory");
-
- return icreg;
-}
-
-static inline void put_ross_icr(unsigned int icreg)
-{
- __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
- ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : /* no outputs */
- : "r" (icreg)
- : "g1", "memory");
-
- return;
-}
-
-/* HyperSparc specific cache flushing. */
-
-/* This is for the on-chip instruction cache. */
-static inline void hyper_flush_whole_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_FLUSH_IWHOLE)
- : "memory");
- return;
-}
-
-extern int vac_cache_size;
-extern int vac_line_size;
-
-static inline void hyper_clear_all_tags(void)
-{
- unsigned long addr;
-
- for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void hyper_flush_unconditional_combined(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_CTX)
- : "memory");
-}
-
-static inline void hyper_flush_cache_user(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_USER)
- : "memory");
-}
-
-static inline void hyper_flush_cache_page(unsigned long page)
-{
- unsigned long end;
-
- page &= PAGE_MASK;
- end = page + PAGE_SIZE;
- while (page < end) {
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (page), "i" (ASI_M_FLUSH_PAGE)
- : "memory");
- page += vac_line_size;
- }
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_ROSS_H) */
diff --git a/arch/sparc/include/asm/swift.h b/arch/sparc/include/asm/swift.h
deleted file mode 100644
index 96f6526b964e..000000000000
--- a/arch/sparc/include/asm/swift.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* swift.h: Specific definitions for the _broken_ Swift SRMMU
- * MMU module.
- *
- * Copyright (C) 1996 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_SWIFT_H
-#define _SPARC_SWIFT_H
-
-/* Swift is so brain damaged, here is the mmu control register. */
-#define SWIFT_ST 0x00800000 /* SW tablewalk enable */
-#define SWIFT_WP 0x00400000 /* Watchpoint enable */
-
-/* Branch folding (buggy, disable on production systems!) */
-#define SWIFT_BF 0x00200000
-#define SWIFT_PMC 0x00180000 /* Page mode control */
-#define SWIFT_PE 0x00040000 /* Parity enable */
-#define SWIFT_PC 0x00020000 /* Parity control */
-#define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
-#define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
-#define SWIFT_BM 0x00004000 /* Boot mode */
-#define SWIFT_RC 0x00003c00 /* DRAM refresh control */
-#define SWIFT_IE 0x00000200 /* Instruction cache enable */
-#define SWIFT_DE 0x00000100 /* Data cache enable */
-#define SWIFT_SA 0x00000080 /* Store Allocate */
-#define SWIFT_NF 0x00000002 /* No fault mode */
-#define SWIFT_EN 0x00000001 /* MMU enable */
-
-/* Bits [13:5] select one of 512 instruction cache tags */
-static inline void swift_inv_insn_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_TXTC_TAG)
- : "memory");
-}
-
-/* Bits [12:4] select one of 512 data cache tags */
-static inline void swift_inv_data_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void swift_flush_dcache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x2000; addr += 0x10)
- swift_inv_data_tag(addr);
-}
-
-static inline void swift_flush_icache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- swift_inv_insn_tag(addr);
-}
-
-static inline void swift_idflash_clear(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x2000; addr += 0x10) {
- swift_inv_insn_tag(addr<<1);
- swift_inv_data_tag(addr);
- }
-}
-
-/* Swift is so broken, it isn't even safe to use the following. */
-static inline void swift_flush_page(unsigned long page)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (page), "i" (ASI_M_FLUSH_PAGE)
- : "memory");
-}
-
-static inline void swift_flush_segment(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_SEG)
- : "memory");
-}
-
-static inline void swift_flush_region(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_REGION)
- : "memory");
-}
-
-static inline void swift_flush_context(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_FLUSH_CTX)
- : "memory");
-}
-
-#endif /* !(_SPARC_SWIFT_H) */
diff --git a/arch/sparc/include/asm/tsunami.h b/arch/sparc/include/asm/tsunami.h
deleted file mode 100644
index acaf014eff46..000000000000
--- a/arch/sparc/include/asm/tsunami.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_TSUNAMI_H
-#define _SPARC_TSUNAMI_H
-
-#include <asm/asi.h>
-
-/* The MMU control register on the Tsunami:
- *
- * -----------------------------------------------------------------------
- * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
- * -----------------------------------------------------------------------
- * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
- *
- * SW: Enable Software Table Walks 0=off 1=on
- * AV: Address View bit
- * DV: Data View bit
- * MV: Memory View bit
- * PC: Parity Control
- * ITD: ITBR disable
- * ALC: Alternate Cacheable
- * PE: Parity Enable 0=off 1=on
- * RC: Refresh Control
- * IE: Instruction cache Enable 0=off 1=on
- * DE: Data cache Enable 0=off 1=on
- * NF: No Fault, same as all other SRMMUs
- * ME: MMU Enable, same as all other SRMMUs
- */
-
-#define TSUNAMI_SW 0x00800000
-#define TSUNAMI_AV 0x00400000
-#define TSUNAMI_DV 0x00200000
-#define TSUNAMI_MV 0x00100000
-#define TSUNAMI_PC 0x00020000
-#define TSUNAMI_ITD 0x00010000
-#define TSUNAMI_ALC 0x00008000
-#define TSUNAMI_PE 0x00001000
-#define TSUNAMI_RCMASK 0x00000C00
-#define TSUNAMI_IENAB 0x00000200
-#define TSUNAMI_DENAB 0x00000100
-#define TSUNAMI_NF 0x00000002
-#define TSUNAMI_ME 0x00000001
-
-static inline void tsunami_flush_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void tsunami_flush_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-#endif /* !(_SPARC_TSUNAMI_H) */
diff --git a/arch/sparc/include/asm/turbosparc.h b/arch/sparc/include/asm/turbosparc.h
deleted file mode 100644
index 23df777f9cea..000000000000
--- a/arch/sparc/include/asm/turbosparc.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * turbosparc.h: Defines specific to the TurboSparc module.
- * This is SRMMU stuff.
- *
- * Copyright (C) 1997 Jakub Jelinek ([email protected])
- */
-#ifndef _SPARC_TURBOSPARC_H
-#define _SPARC_TURBOSPARC_H
-
-#include <asm/asi.h>
-#include <asm/pgtsrmmu.h>
-
-/* Bits in the SRMMU control register for TurboSparc modules.
- *
- * -------------------------------------------------------------------
- * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
- * -------------------------------------------------------------------
- * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
- *
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- *
- * This indicates whether the TurboSparc is in boot-mode or not.
- *
- * IC: Instruction Cache -- 0 = off, 1 = on
- * DC: Data Cache -- 0 = off, 1 = 0n
- *
- * These bits enable the on-cpu TurboSparc split I/D caches.
- *
- * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
- * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
- * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
- *
- */
-
-#define TURBOSPARC_MMUENABLE 0x00000001
-#define TURBOSPARC_NOFAULT 0x00000002
-#define TURBOSPARC_ICSNOOP 0x00000004
-#define TURBOSPARC_PSO 0x00000080
-#define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
-#define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
-#define TURBOSPARC_BMODE 0x00004000
-#define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
-#define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
-
-/* Bits in the CPU configuration register for TurboSparc modules.
- *
- * -------------------------------------------------------
- * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
- * -------------------------------------------------------
- * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
- *
- */
-
-#define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
-#define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
-#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
-#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
-
-#ifndef __ASSEMBLY__
-
-/* Bits [13:5] select one of 512 instruction cache tags */
-static inline void turbosparc_inv_insn_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_TXTC_TAG)
- : "memory");
-}
-
-/* Bits [13:5] select one of 512 data cache tags */
-static inline void turbosparc_inv_data_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void turbosparc_flush_icache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- turbosparc_inv_insn_tag(addr);
-}
-
-static inline void turbosparc_flush_dcache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- turbosparc_inv_data_tag(addr);
-}
-
-static inline void turbosparc_idflash_clear(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20) {
- turbosparc_inv_insn_tag(addr);
- turbosparc_inv_data_tag(addr);
- }
-}
-
-static inline void turbosparc_set_ccreg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t"
- : /* no outputs */
- : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
- : "memory");
-}
-
-static inline unsigned long turbosparc_get_ccreg(void)
-{
- unsigned long regval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (regval)
- : "r" (0x600), "i" (ASI_M_MMUREGS));
- return regval;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_TURBOSPARC_H) */
diff --git a/arch/sparc/include/asm/viking.h b/arch/sparc/include/asm/viking.h
deleted file mode 100644
index 08ffc605035f..000000000000
--- a/arch/sparc/include/asm/viking.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * viking.h: Defines specific to the GNU/Viking MBUS module.
- * This is SRMMU stuff.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-#ifndef _SPARC_VIKING_H
-#define _SPARC_VIKING_H
-
-#include <asm/asi.h>
-#include <asm/mxcc.h>
-#include <asm/pgtable.h>
-#include <asm/pgtsrmmu.h>
-
-/* Bits in the SRMMU control register for GNU/Viking modules.
- *
- * -----------------------------------------------------------
- * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
- * -----------------------------------------------------------
- * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
- *
- * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
- * 1 = Twalks are cacheable in E-cache
- *
- * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
- * and never caches them internally (or so states the docs). Therefore
- * for machines lacking an E-cache (ie. in MBUS mode) this bit must
- * remain cleared.
- *
- * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
- * 1 = Passthru physical accesses cacheable
- *
- * This indicates whether accesses are cacheable when no cachable bit
- * is present in the pte when the processor is in boot-mode or the
- * access does not need pte's for translation (ie. pass-thru ASI's).
- * "Cachable" is only referring to E-cache (if present) and not the
- * on chip split I/D caches of the GNU/Viking.
- *
- * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
- *
- * This enables snooping on the GNU/Viking bus. This must be on
- * for the hardware cache consistency mechanisms of the GNU/Viking
- * to work at all. On non-mxcc GNU/Viking modules the split I/D
- * caches will snoop regardless of whether they are enabled, this
- * takes care of the case where the I or D or both caches are turned
- * off yet still contain valid data. Note also that this bit does
- * not affect GNU/Viking store-buffer snoops, those happen if the
- * store-buffer is enabled no matter what.
- *
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- *
- * This indicates whether the GNU/Viking is in boot-mode or not,
- * if it is then all instruction fetch physical addresses are
- * computed as 0xff0000000 + low 28 bits of requested address.
- * GNU/Viking boot-mode does not affect data accesses. Also,
- * in boot mode instruction accesses bypass the split on chip I/D
- * caches, they may be cached by the GNU/MXCC if present and enabled.
- *
- * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
- *
- * This indicated the GNU/Viking configuration present. If in
- * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
- * not then the GNU/Viking is on a module VBUS connected directly
- * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
- * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
- *
- * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
- *
- * The GNU/Viking store buffer allows the chip to continue execution
- * after a store even if the data cannot be placed in one of the
- * caches during that cycle. If disabled, all stores operations
- * occur synchronously.
- *
- * IC: Instruction Cache -- 0 = off, 1 = on
- * DC: Data Cache -- 0 = off, 1 = 0n
- *
- * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
- * as mentioned above, these caches will snoop the bus in GNU/MBUS
- * configurations even when disabled to avoid data corruption.
- *
- * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
- * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
- *
- */
-
-#define VIKING_MMUENABLE 0x00000001
-#define VIKING_NOFAULT 0x00000002
-#define VIKING_PSO 0x00000080
-#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
-#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
-#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
-#define VIKING_MMODE 0x00000800 /* MBUS mode */
-#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
-#define VIKING_BMODE 0x00002000
-#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
-#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
-#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
-#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
-
-/*
- * GNU/Viking Breakpoint Action Register fields.
- */
-#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
-
-/*
- * GNU/Viking Cache Tags.
- */
-#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
-#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
-#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
-
-#ifndef __ASSEMBLY__
-
-static inline void viking_flush_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_flush_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_unlock_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_unlock_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_set_bpreg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
- : /* no outputs */
- : "r" (regval), "i" (ASI_M_ACTION)
- : "memory");
-}
-
-static inline unsigned long viking_get_bpreg(void)
-{
- unsigned long regval;
-
- __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
- : "=r" (regval)
- : "i" (ASI_M_ACTION));
- return regval;
-}
-
-static inline void viking_get_dcache_ptag(int set, int block,
- unsigned long *data)
-{
- unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
- 0x80000000;
- unsigned long info, page;
-
- __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
- "or %%g0, %%g2, %0\n\t"
- "or %%g0, %%g3, %1\n\t"
- : "=r" (info), "=r" (page)
- : "r" (ptag), "i" (ASI_M_DATAC_TAG)
- : "g2", "g3");
- data[0] = info;
- data[1] = page;
-}
-
-static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
- unsigned long *mxcc_cregp)
-{
- unsigned long mreg = *mregp;
- unsigned long mxcc_creg = *mxcc_cregp;
-
- mreg &= ~(VIKING_PCENABLE);
- mxcc_creg &= ~(MXCC_CTL_PARE);
-
- __asm__ __volatile__ ("set 1f, %%g2\n\t"
- "andcc %%g2, 4, %%g0\n\t"
- "bne 2f\n\t"
- " nop\n"
- "1:\n\t"
- "sta %0, [%%g0] %3\n\t"
- "sta %1, [%2] %4\n\t"
- "b 1f\n\t"
- " nop\n\t"
- "nop\n"
- "2:\n\t"
- "sta %0, [%%g0] %3\n\t"
- "sta %1, [%2] %4\n"
- "1:\n\t"
- : /* no output */
- : "r" (mreg), "r" (mxcc_creg),
- "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
- "i" (ASI_M_MXCC)
- : "g2", "memory", "cc");
- *mregp = mreg;
- *mxcc_cregp = mxcc_creg;
-}
-
-static inline unsigned long viking_hwprobe(unsigned long vaddr)
-{
- unsigned long val;
-
- vaddr &= PAGE_MASK;
- /* Probe all MMU entries. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
- if (!val)
- return 0;
-
- /* Probe region. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
- if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
- vaddr &= ~PGDIR_MASK;
- vaddr >>= PAGE_SHIFT;
- return val | (vaddr << 8);
- }
-
- /* Probe segment. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
- if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
- vaddr &= ~PMD_MASK;
- vaddr >>= PAGE_SHIFT;
- return val | (vaddr << 8);
- }
-
- /* Probe page. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
- return val;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_VIKING_H) */
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 13011969e7eb..0f2417ee3f95 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -25,7 +25,6 @@
#include <asm/winmacro.h>
#include <asm/signal.h>
#include <asm/obio.h>
-#include <asm/mxcc.h>
#include <asm/thread_info.h>
#include <asm/param.h>
#include <asm/unistd.h>
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index 809d993f6d88..7b3ff6dd382e 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -9,7 +9,6 @@ obj-y += fault_$(BITS).o
obj-y += init_$(BITS).o
obj-$(CONFIG_SPARC32) += srmmu.o iommu.o io-unit.o
obj-$(CONFIG_SPARC32) += srmmu_access.o
-obj-$(CONFIG_SPARC32) += hypersparc.o viking.o tsunami.o swift.o
obj-$(CONFIG_SPARC32) += leon_mm.o
# Only used by sparc64
diff --git a/arch/sparc/mm/hypersparc.S b/arch/sparc/mm/hypersparc.S
deleted file mode 100644
index 6c2521e85a42..000000000000
--- a/arch/sparc/mm/hypersparc.S
+++ /dev/null
@@ -1,414 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * hypersparc.S: High speed Hypersparc mmu/cache operations.
- *
- * Copyright (C) 1997 David S. Miller ([email protected])
- */
-
-#include <asm/ptrace.h>
-#include <asm/psr.h>
-#include <asm/asm-offsets.h>
-#include <asm/asi.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pgtsrmmu.h>
-#include <linux/init.h>
-
- .text
- .align 4
-
- .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
- .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
- .globl hypersparc_flush_page_to_ram
- .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
- .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
- .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
-
-hypersparc_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
- sethi %hi(vac_cache_size), %g4
- ld [%g4 + %lo(vac_cache_size)], %g5
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %g2
-1:
- subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
- bne 1b
- sta %g0, [%g5] ASI_M_FLUSH_CTX
- retl
- sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
-
- /* We expand the window flush to get maximum performance. */
-hypersparc_flush_cache_mm:
-#ifndef CONFIG_SMP
- ld [%o0 + AOFF_mm_context], %g1
- cmp %g1, -1
- be hypersparc_flush_cache_mm_out
-#endif
- WINDOW_FLUSH(%g4, %g5)
-
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o1
- sethi %hi(vac_cache_size), %g2
- ld [%g2 + %lo(vac_cache_size)], %o0
- add %o1, %o1, %g1
- add %o1, %g1, %g2
- add %o1, %g2, %g3
- add %o1, %g3, %g4
- add %o1, %g4, %g5
- add %o1, %g5, %o4
- add %o1, %o4, %o5
-
- /* BLAMMO! */
-1:
- subcc %o0, %o5, %o0 ! hyper_flush_cache_user
- sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
- bne 1b
- sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
-hypersparc_flush_cache_mm_out:
- retl
- nop
-
- /* The things we do for performance... */
-hypersparc_flush_cache_range:
- ld [%o0 + VMA_VM_MM], %o0
-#ifndef CONFIG_SMP
- ld [%o0 + AOFF_mm_context], %g1
- cmp %g1, -1
- be hypersparc_flush_cache_range_out
-#endif
- WINDOW_FLUSH(%g4, %g5)
-
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o4
- sethi %hi(vac_cache_size), %g2
- ld [%g2 + %lo(vac_cache_size)], %o3
-
- /* Here comes the fun part... */
- add %o2, (PAGE_SIZE - 1), %o2
- andn %o1, (PAGE_SIZE - 1), %o1
- add %o4, %o4, %o5
- andn %o2, (PAGE_SIZE - 1), %o2
- add %o4, %o5, %g1
- sub %o2, %o1, %g4
- add %o4, %g1, %g2
- sll %o3, 2, %g5
- add %o4, %g2, %g3
- cmp %g4, %g5
- add %o4, %g3, %g4
- blu 0f
- add %o4, %g4, %g5
- add %o4, %g5, %g7
-
- /* Flush entire user space, believe it or not this is quicker
- * than page at a time flushings for range > (cache_size<<2).
- */
-1:
- subcc %o3, %g7, %o3
- sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
- bne 1b
- sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
- retl
- nop
-
- /* Below our threshold, flush one page at a time. */
-0:
- ld [%o0 + AOFF_mm_context], %o0
- mov SRMMU_CTX_REG, %g7
- lda [%g7] ASI_M_MMUREGS, %o3
- sta %o0, [%g7] ASI_M_MMUREGS
- add %o2, -PAGE_SIZE, %o0
-1:
- or %o0, 0x400, %g7
- lda [%g7] ASI_M_FLUSH_PROBE, %g7
- orcc %g7, 0, %g0
- be,a 3f
- mov %o0, %o2
- add %o4, %g5, %g7
-2:
- sub %o2, %g7, %o2
- sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
- andcc %o2, 0xffc, %g0
- sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
- bne 2b
- sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
-3:
- cmp %o2, %o1
- bne 1b
- add %o2, -PAGE_SIZE, %o0
- mov SRMMU_FAULT_STATUS, %g5
- lda [%g5] ASI_M_MMUREGS, %g0
- mov SRMMU_CTX_REG, %g7
- sta %o3, [%g7] ASI_M_MMUREGS
-hypersparc_flush_cache_range_out:
- retl
- nop
-
- /* HyperSparc requires a valid mapping where we are about to flush
- * in order to check for a physical tag match during the flush.
- */
- /* Verified, my ass... */
-hypersparc_flush_cache_page:
- ld [%o0 + VMA_VM_MM], %o0
- ld [%o0 + AOFF_mm_context], %g2
-#ifndef CONFIG_SMP
- cmp %g2, -1
- be hypersparc_flush_cache_page_out
-#endif
- WINDOW_FLUSH(%g4, %g5)
-
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o4
- mov SRMMU_CTX_REG, %o3
- andn %o1, (PAGE_SIZE - 1), %o1
- lda [%o3] ASI_M_MMUREGS, %o2
- sta %g2, [%o3] ASI_M_MMUREGS
- or %o1, 0x400, %o5
- lda [%o5] ASI_M_FLUSH_PROBE, %g1
- orcc %g0, %g1, %g0
- be 2f
- add %o4, %o4, %o5
- sub %o1, -PAGE_SIZE, %o1
- add %o4, %o5, %g1
- add %o4, %g1, %g2
- add %o4, %g2, %g3
- add %o4, %g3, %g4
- add %o4, %g4, %g5
- add %o4, %g5, %g7
-
- /* BLAMMO! */
-1:
- sub %o1, %g7, %o1
- sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
- andcc %o1, 0xffc, %g0
- sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
- bne 1b
- sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
-2:
- mov SRMMU_FAULT_STATUS, %g7
- mov SRMMU_CTX_REG, %g4
- lda [%g7] ASI_M_MMUREGS, %g0
- sta %o2, [%g4] ASI_M_MMUREGS
-hypersparc_flush_cache_page_out:
- retl
- nop
-
-hypersparc_flush_sig_insns:
- flush %o1
- retl
- flush %o1 + 4
-
- /* HyperSparc is copy-back. */
-hypersparc_flush_page_to_ram:
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o4
- andn %o0, (PAGE_SIZE - 1), %o0
- add %o4, %o4, %o5
- or %o0, 0x400, %g7
- lda [%g7] ASI_M_FLUSH_PROBE, %g5
- add %o4, %o5, %g1
- orcc %g5, 0, %g0
- be 2f
- add %o4, %g1, %g2
- add %o4, %g2, %g3
- sub %o0, -PAGE_SIZE, %o0
- add %o4, %g3, %g4
- add %o4, %g4, %g5
- add %o4, %g5, %g7
-
- /* BLAMMO! */
-1:
- sub %o0, %g7, %o0
- sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
- andcc %o0, 0xffc, %g0
- sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
- bne 1b
- sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
-2:
- mov SRMMU_FAULT_STATUS, %g1
- retl
- lda [%g1] ASI_M_MMUREGS, %g0
-
- /* HyperSparc is IO cache coherent. */
-hypersparc_flush_page_for_dma:
- retl
- nop
-
- /* It was noted that at boot time a TLB flush all in a delay slot
- * can deliver an illegal instruction to the processor if the timing
- * is just right...
- */
-hypersparc_flush_tlb_all:
- mov 0x400, %g1
- sta %g0, [%g1] ASI_M_FLUSH_PROBE
- retl
- nop
-
-hypersparc_flush_tlb_mm:
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o1
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o1, -1
- be hypersparc_flush_tlb_mm_out
-#endif
- mov 0x300, %g2
- sta %o1, [%g1] ASI_M_MMUREGS
- sta %g0, [%g2] ASI_M_FLUSH_PROBE
-hypersparc_flush_tlb_mm_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
-hypersparc_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be hypersparc_flush_tlb_range_out
-#endif
- sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
- sta %o3, [%g1] ASI_M_MMUREGS
- and %o1, %o4, %o1
- add %o1, 0x200, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-1:
- sub %o1, %o4, %o1
- cmp %o1, %o2
- blu,a 1b
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-hypersparc_flush_tlb_range_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
-hypersparc_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- andn %o1, (PAGE_SIZE - 1), %o1
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be hypersparc_flush_tlb_page_out
-#endif
- lda [%g1] ASI_M_MMUREGS, %g5
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-hypersparc_flush_tlb_page_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
- __INIT
-
- /* High speed page clear/copy. */
-hypersparc_bzero_1page:
-/* NOTE: This routine has to be shorter than 40insns --jj */
- clr %g1
- mov 32, %g2
- mov 64, %g3
- mov 96, %g4
- mov 128, %g5
- mov 160, %g7
- mov 192, %o2
- mov 224, %o3
- mov 16, %o1
-1:
- stda %g0, [%o0 + %g0] ASI_M_BFILL
- stda %g0, [%o0 + %g2] ASI_M_BFILL
- stda %g0, [%o0 + %g3] ASI_M_BFILL
- stda %g0, [%o0 + %g4] ASI_M_BFILL
- stda %g0, [%o0 + %g5] ASI_M_BFILL
- stda %g0, [%o0 + %g7] ASI_M_BFILL
- stda %g0, [%o0 + %o2] ASI_M_BFILL
- stda %g0, [%o0 + %o3] ASI_M_BFILL
- subcc %o1, 1, %o1
- bne 1b
- add %o0, 256, %o0
-
- retl
- nop
-
-hypersparc_copy_1page:
-/* NOTE: This routine has to be shorter than 70insns --jj */
- sub %o1, %o0, %o2 ! difference
- mov 16, %g1
-1:
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- subcc %g1, 1, %g1
- bne 1b
- add %o0, 32, %o0
-
- retl
- nop
-
- .globl hypersparc_setup_blockops
-hypersparc_setup_blockops:
- sethi %hi(bzero_1page), %o0
- or %o0, %lo(bzero_1page), %o0
- sethi %hi(hypersparc_bzero_1page), %o1
- or %o1, %lo(hypersparc_bzero_1page), %o1
- sethi %hi(hypersparc_copy_1page), %o2
- or %o2, %lo(hypersparc_copy_1page), %o2
- ld [%o1], %o4
-1:
- add %o1, 4, %o1
- st %o4, [%o0]
- add %o0, 4, %o0
- cmp %o1, %o2
- bne 1b
- ld [%o1], %o4
- sethi %hi(__copy_1page), %o0
- or %o0, %lo(__copy_1page), %o0
- sethi %hi(hypersparc_setup_blockops), %o2
- or %o2, %lo(hypersparc_setup_blockops), %o2
- ld [%o1], %o4
-1:
- add %o1, 4, %o1
- st %o4, [%o0]
- add %o0, 4, %o0
- cmp %o1, %o2
- bne 1b
- ld [%o1], %o4
- sta %g0, [%g0] ASI_M_FLUSH_IWHOLE
- retl
- nop
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
index d94d7868feb9..a2cfa8757795 100644
--- a/arch/sparc/mm/io-unit.c
+++ b/arch/sparc/mm/io-unit.c
@@ -18,7 +18,6 @@
#include <asm/io.h>
#include <asm/io-unit.h>
-#include <asm/mxcc.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index 832e5ff8b663..482e08df7bad 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -18,7 +18,6 @@
#include <linux/platform_device.h>
#include <asm/io.h>
-#include <asm/mxcc.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/bitext.h>
@@ -37,11 +36,6 @@
#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
-static int viking_flush;
-/* viking.S */
-extern void viking_flush_page(unsigned long page);
-extern void viking_mxcc_flush_page(unsigned long page);
-
/*
* Values precomputed according to CPU type.
*/
@@ -156,21 +150,9 @@ static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
start = (unsigned long)iopte;
end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
start &= PAGE_MASK;
- if (viking_mxcc_present) {
- while(start < end) {
- viking_mxcc_flush_page(start);
- start += PAGE_SIZE;
- }
- } else if (viking_flush) {
- while(start < end) {
- viking_flush_page(start);
- start += PAGE_SIZE;
- }
- } else {
- while(start < end) {
- __flush_page_to_ram(start);
- start += PAGE_SIZE;
- }
+ while(start < end) {
+ __flush_page_to_ram(start);
+ start += PAGE_SIZE;
}
}
@@ -344,12 +326,7 @@ static void *sbus_iommu_alloc(struct device *dev, size_t len,
pmd_t *pmdp;
pte_t *ptep;
- if (viking_mxcc_present)
- viking_mxcc_flush_page(page);
- else if (viking_flush)
- viking_flush_page(page);
- else
- __flush_page_to_ram(page);
+ __flush_page_to_ram(page);
pmdp = pmd_off_k(addr);
ptep = pte_offset_kernel(pmdp, addr);
diff --git a/arch/sparc/mm/mm_32.h b/arch/sparc/mm/mm_32.h
index ee55f1080634..2c83b8ce742d 100644
--- a/arch/sparc/mm/mm_32.h
+++ b/arch/sparc/mm/mm_32.h
@@ -9,7 +9,6 @@ void window_ret_fault(struct pt_regs *regs);
/* srmmu.c */
extern char *srmmu_name;
-extern int viking_mxcc_present;
extern int flush_page_for_dma_global;
extern void (*poke_srmmu)(void);
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 3a7e10729a02..4a3778549c6f 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -40,13 +40,7 @@
#include <asm/io.h>
/* Now the cpu specific definitions. */
-#include <asm/turbosparc.h>
-#include <asm/tsunami.h>
-#include <asm/viking.h>
-#include <asm/swift.h>
#include <asm/leon.h>
-#include <asm/mxcc.h>
-#include <asm/ross.h>
#include "mm_32.h"
@@ -65,12 +59,6 @@ EXPORT_SYMBOL(sparc32_cachetlb_ops);
#ifdef CONFIG_SMP
const struct sparc32_cachetlb_ops *local_ops;
-
-#define FLUSH_BEGIN(mm)
-#define FLUSH_END
-#else
-#define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
-#define FLUSH_END }
#endif
int flush_page_for_dma_global = 1;
@@ -80,11 +68,8 @@ char *srmmu_name;
ctxd_t *srmmu_ctx_table_phys;
static ctxd_t *srmmu_context_table;
-int viking_mxcc_present;
static DEFINE_SPINLOCK(srmmu_context_spinlock);
-static int is_hypersparc;
-
static int srmmu_cache_pagetables;
/* these will be initialized in srmmu_nocache_calcsize() */
@@ -112,25 +97,6 @@ static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
set_pte((pte_t *)ctxp, pte);
}
-/*
- * Locations of MSI Registers.
- */
-#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
-
-/*
- * Useful bits in the MSI Registers.
- */
-#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
-
-static void msi_set_sync(void)
-{
- __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
- "andn %%g3, %2, %%g3\n\t"
- "sta %%g3, [%0] %1\n\t" : :
- "r" (MSI_MBUS_ARBEN),
- "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
-}
-
void pmd_set(pmd_t *pmdp, pte_t *ptep)
{
unsigned long ptp = __nocache_pa(ptep) >> 4;
@@ -478,11 +444,7 @@ void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
}
- if (sparc_cpu_model == sparc_leon)
- leon_switch_mm();
-
- if (is_hypersparc)
- hyper_flush_whole_icache();
+ leon_switch_mm();
srmmu_set_context(mm->context);
}
@@ -557,110 +519,6 @@ void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
flush_tlb_all();
}
-/* tsunami.S */
-extern void tsunami_flush_cache_all(void);
-extern void tsunami_flush_cache_mm(struct mm_struct *mm);
-extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void tsunami_flush_page_to_ram(unsigned long page);
-extern void tsunami_flush_page_for_dma(unsigned long page);
-extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-extern void tsunami_flush_tlb_all(void);
-extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
-extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-extern void tsunami_setup_blockops(void);
-
-/* swift.S */
-extern void swift_flush_cache_all(void);
-extern void swift_flush_cache_mm(struct mm_struct *mm);
-extern void swift_flush_cache_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void swift_flush_page_to_ram(unsigned long page);
-extern void swift_flush_page_for_dma(unsigned long page);
-extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-extern void swift_flush_tlb_all(void);
-extern void swift_flush_tlb_mm(struct mm_struct *mm);
-extern void swift_flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-
-#if 0 /* P3: deadwood to debug precise flushes on Swift. */
-void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- int cctx, ctx1;
-
- page &= PAGE_MASK;
- if ((ctx1 = vma->vm_mm->context) != -1) {
- cctx = srmmu_get_context();
-/* Is context # ever different from current context? P3 */
- if (cctx != ctx1) {
- printk("flush ctx %02x curr %02x\n", ctx1, cctx);
- srmmu_set_context(ctx1);
- swift_flush_page(page);
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (page), "i" (ASI_M_FLUSH_PROBE));
- srmmu_set_context(cctx);
- } else {
- /* Rm. prot. bits from virt. c. */
- /* swift_flush_cache_all(); */
- /* swift_flush_cache_page(vma, page); */
- swift_flush_page(page);
-
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (page), "i" (ASI_M_FLUSH_PROBE));
- /* same as above: srmmu_flush_tlb_page() */
- }
- }
-}
-#endif
-
-/*
- * The following are all MBUS based SRMMU modules, and therefore could
- * be found in a multiprocessor configuration. On the whole, these
- * chips seems to be much more touchy about DVMA and page tables
- * with respect to cache coherency.
- */
-
-/* viking.S */
-extern void viking_flush_cache_all(void);
-extern void viking_flush_cache_mm(struct mm_struct *mm);
-extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void viking_flush_page_to_ram(unsigned long page);
-extern void viking_flush_page_for_dma(unsigned long page);
-extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
-extern void viking_flush_page(unsigned long page);
-extern void viking_mxcc_flush_page(unsigned long page);
-extern void viking_flush_tlb_all(void);
-extern void viking_flush_tlb_mm(struct mm_struct *mm);
-extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-extern void viking_flush_tlb_page(struct vm_area_struct *vma,
- unsigned long page);
-extern void sun4dsmp_flush_tlb_all(void);
-extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
-extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
- unsigned long page);
-
-/* hypersparc.S */
-extern void hypersparc_flush_cache_all(void);
-extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
-extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void hypersparc_flush_page_to_ram(unsigned long page);
-extern void hypersparc_flush_page_for_dma(unsigned long page);
-extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-extern void hypersparc_flush_tlb_all(void);
-extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
-extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-extern void hypersparc_setup_blockops(void);
-
/*
* NOTE: All of this startup code assumes the low 16mb (approx.) of
* kernel mappings are done with one single contiguous chunk of
@@ -747,18 +605,7 @@ static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
/* These flush types are not available on all chips... */
static inline unsigned long srmmu_probe(unsigned long vaddr)
{
- unsigned long retval;
-
- if (sparc_cpu_model != sparc_leon) {
-
- vaddr &= PAGE_MASK;
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
- } else {
- retval = leon_swprobe(vaddr, NULL);
- }
- return retval;
+ return leon_swprobe(vaddr, NULL);
}
/*
@@ -904,20 +751,16 @@ void __init srmmu_paging_init(void)
init_mm.context = (unsigned long) NO_CONTEXT;
sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
- if (sparc_cpu_model == sun4d)
- num_contexts = 65536; /* We know it is Viking */
- else {
- /* Find the number of contexts on the srmmu. */
- cpunode = prom_getchild(prom_root_node);
- num_contexts = 0;
- while (cpunode != 0) {
- prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
- if (!strcmp(node_str, "cpu")) {
- num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
- break;
- }
- cpunode = prom_getsibling(cpunode);
+ /* Find the number of contexts on the srmmu. */
+ cpunode = prom_getchild(prom_root_node);
+ num_contexts = 0;
+ while (cpunode != 0) {
+ prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
+ if (!strcmp(node_str, "cpu")) {
+ num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
+ break;
}
+ cpunode = prom_getsibling(cpunode);
}
if (!num_contexts) {
@@ -1014,577 +857,6 @@ void destroy_context(struct mm_struct *mm)
}
}
-/* Init various srmmu chip types. */
-static void __init srmmu_is_bad(void)
-{
- prom_printf("Could not determine SRMMU chip type.\n");
- prom_halt();
-}
-
-static void __init init_vac_layout(void)
-{
- phandle nd;
- int cache_lines;
- char node_str[128];
-#ifdef CONFIG_SMP
- int cpu = 0;
- unsigned long max_size = 0;
- unsigned long min_line_size = 0x10000000;
-#endif
-
- nd = prom_getchild(prom_root_node);
- while ((nd = prom_getsibling(nd)) != 0) {
- prom_getstring(nd, "device_type", node_str, sizeof(node_str));
- if (!strcmp(node_str, "cpu")) {
- vac_line_size = prom_getint(nd, "cache-line-size");
- if (vac_line_size == -1) {
- prom_printf("can't determine cache-line-size, halting.\n");
- prom_halt();
- }
- cache_lines = prom_getint(nd, "cache-nlines");
- if (cache_lines == -1) {
- prom_printf("can't determine cache-nlines, halting.\n");
- prom_halt();
- }
-
- vac_cache_size = cache_lines * vac_line_size;
-#ifdef CONFIG_SMP
- if (vac_cache_size > max_size)
- max_size = vac_cache_size;
- if (vac_line_size < min_line_size)
- min_line_size = vac_line_size;
- //FIXME: cpus not contiguous!!
- cpu++;
- if (cpu >= nr_cpu_ids || !cpu_online(cpu))
- break;
-#else
- break;
-#endif
- }
- }
- if (nd == 0) {
- prom_printf("No CPU nodes found, halting.\n");
- prom_halt();
- }
-#ifdef CONFIG_SMP
- vac_cache_size = max_size;
- vac_line_size = min_line_size;
-#endif
- printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
- (int)vac_cache_size, (int)vac_line_size);
-}
-
-static void poke_hypersparc(void)
-{
- volatile unsigned long clear;
- unsigned long mreg = srmmu_get_mmureg();
-
- hyper_flush_unconditional_combined();
-
- mreg &= ~(HYPERSPARC_CWENABLE);
- mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
- mreg |= (HYPERSPARC_CMODE);
-
- srmmu_set_mmureg(mreg);
-
-#if 0 /* XXX I think this is bad news... -DaveM */
- hyper_clear_all_tags();
-#endif
-
- put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
- hyper_flush_whole_icache();
- clear = srmmu_get_faddr();
- clear = srmmu_get_fstatus();
-}
-
-static const struct sparc32_cachetlb_ops hypersparc_ops = {
- .cache_all = hypersparc_flush_cache_all,
- .cache_mm = hypersparc_flush_cache_mm,
- .cache_page = hypersparc_flush_cache_page,
- .cache_range = hypersparc_flush_cache_range,
- .tlb_all = hypersparc_flush_tlb_all,
- .tlb_mm = hypersparc_flush_tlb_mm,
- .tlb_page = hypersparc_flush_tlb_page,
- .tlb_range = hypersparc_flush_tlb_range,
- .page_to_ram = hypersparc_flush_page_to_ram,
- .sig_insns = hypersparc_flush_sig_insns,
- .page_for_dma = hypersparc_flush_page_for_dma,
-};
-
-static void __init init_hypersparc(void)
-{
- srmmu_name = "ROSS HyperSparc";
-
- init_vac_layout();
-
- is_hypersparc = 1;
- sparc32_cachetlb_ops = &hypersparc_ops;
-
- poke_srmmu = poke_hypersparc;
-
- hypersparc_setup_blockops();
-}
-
-static void poke_swift(void)
-{
- unsigned long mreg;
-
- /* Clear any crap from the cache or else... */
- swift_flush_cache_all();
-
- /* Enable I & D caches */
- mreg = srmmu_get_mmureg();
- mreg |= (SWIFT_IE | SWIFT_DE);
- /*
- * The Swift branch folding logic is completely broken. At
- * trap time, if things are just right, if can mistakenly
- * think that a trap is coming from kernel mode when in fact
- * it is coming from user mode (it mis-executes the branch in
- * the trap code). So you see things like crashme completely
- * hosing your machine which is completely unacceptable. Turn
- * this shit off... nice job Fujitsu.
- */
- mreg &= ~(SWIFT_BF);
- srmmu_set_mmureg(mreg);
-}
-
-static const struct sparc32_cachetlb_ops swift_ops = {
- .cache_all = swift_flush_cache_all,
- .cache_mm = swift_flush_cache_mm,
- .cache_page = swift_flush_cache_page,
- .cache_range = swift_flush_cache_range,
- .tlb_all = swift_flush_tlb_all,
- .tlb_mm = swift_flush_tlb_mm,
- .tlb_page = swift_flush_tlb_page,
- .tlb_range = swift_flush_tlb_range,
- .page_to_ram = swift_flush_page_to_ram,
- .sig_insns = swift_flush_sig_insns,
- .page_for_dma = swift_flush_page_for_dma,
-};
-
-#define SWIFT_MASKID_ADDR 0x10003018
-static void __init init_swift(void)
-{
- unsigned long swift_rev;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- "srl %0, 0x18, %0\n\t" :
- "=r" (swift_rev) :
- "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
- srmmu_name = "Fujitsu Swift";
-
- sparc32_cachetlb_ops = &swift_ops;
- flush_page_for_dma_global = 0;
-
- /*
- * Are you now convinced that the Swift is one of the
- * biggest VLSI abortions of all time? Bravo Fujitsu!
- * Fujitsu, the !#?!%$'d up processor people. I bet if
- * you examined the microcode of the Swift you'd find
- * XXX's all over the place.
- */
- poke_srmmu = poke_swift;
-}
-
-static void turbosparc_flush_cache_all(void)
-{
- flush_user_windows();
- turbosparc_idflash_clear();
-}
-
-static void turbosparc_flush_cache_mm(struct mm_struct *mm)
-{
- FLUSH_BEGIN(mm)
- flush_user_windows();
- turbosparc_idflash_clear();
- FLUSH_END
-}
-
-static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
- FLUSH_BEGIN(vma->vm_mm)
- flush_user_windows();
- turbosparc_idflash_clear();
- FLUSH_END
-}
-
-static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
-{
- FLUSH_BEGIN(vma->vm_mm)
- flush_user_windows();
- if (vma->vm_flags & VM_EXEC)
- turbosparc_flush_icache();
- turbosparc_flush_dcache();
- FLUSH_END
-}
-
-/* TurboSparc is copy-back, if we turn it on, but this does not work. */
-static void turbosparc_flush_page_to_ram(unsigned long page)
-{
-#ifdef TURBOSPARC_WRITEBACK
- volatile unsigned long clear;
-
- if (srmmu_probe(page))
- turbosparc_flush_page_cache(page);
- clear = srmmu_get_fstatus();
-#endif
-}
-
-static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
-{
-}
-
-static void turbosparc_flush_page_for_dma(unsigned long page)
-{
- turbosparc_flush_dcache();
-}
-
-static void turbosparc_flush_tlb_all(void)
-{
- srmmu_flush_whole_tlb();
-}
-
-static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
-{
- FLUSH_BEGIN(mm)
- srmmu_flush_whole_tlb();
- FLUSH_END
-}
-
-static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
- FLUSH_BEGIN(vma->vm_mm)
- srmmu_flush_whole_tlb();
- FLUSH_END
-}
-
-static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- FLUSH_BEGIN(vma->vm_mm)
- srmmu_flush_whole_tlb();
- FLUSH_END
-}
-
-
-static void poke_turbosparc(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
- unsigned long ccreg;
-
- /* Clear any crap from the cache or else... */
- turbosparc_flush_cache_all();
- /* Temporarily disable I & D caches */
- mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
- mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
- srmmu_set_mmureg(mreg);
-
- ccreg = turbosparc_get_ccreg();
-
-#ifdef TURBOSPARC_WRITEBACK
- ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
- ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
- /* Write-back D-cache, emulate VLSI
- * abortion number three, not number one */
-#else
- /* For now let's play safe, optimize later */
- ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
- /* Do DVMA snooping in Dcache, Write-thru D-cache */
- ccreg &= ~(TURBOSPARC_uS2);
- /* Emulate VLSI abortion number three, not number one */
-#endif
-
- switch (ccreg & 7) {
- case 0: /* No SE cache */
- case 7: /* Test mode */
- break;
- default:
- ccreg |= (TURBOSPARC_SCENABLE);
- }
- turbosparc_set_ccreg(ccreg);
-
- mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
- mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
- srmmu_set_mmureg(mreg);
-}
-
-static const struct sparc32_cachetlb_ops turbosparc_ops = {
- .cache_all = turbosparc_flush_cache_all,
- .cache_mm = turbosparc_flush_cache_mm,
- .cache_page = turbosparc_flush_cache_page,
- .cache_range = turbosparc_flush_cache_range,
- .tlb_all = turbosparc_flush_tlb_all,
- .tlb_mm = turbosparc_flush_tlb_mm,
- .tlb_page = turbosparc_flush_tlb_page,
- .tlb_range = turbosparc_flush_tlb_range,
- .page_to_ram = turbosparc_flush_page_to_ram,
- .sig_insns = turbosparc_flush_sig_insns,
- .page_for_dma = turbosparc_flush_page_for_dma,
-};
-
-static void __init init_turbosparc(void)
-{
- srmmu_name = "Fujitsu TurboSparc";
- sparc32_cachetlb_ops = &turbosparc_ops;
- poke_srmmu = poke_turbosparc;
-}
-
-static void poke_tsunami(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
-
- tsunami_flush_icache();
- tsunami_flush_dcache();
- mreg &= ~TSUNAMI_ITD;
- mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
- srmmu_set_mmureg(mreg);
-}
-
-static const struct sparc32_cachetlb_ops tsunami_ops = {
- .cache_all = tsunami_flush_cache_all,
- .cache_mm = tsunami_flush_cache_mm,
- .cache_page = tsunami_flush_cache_page,
- .cache_range = tsunami_flush_cache_range,
- .tlb_all = tsunami_flush_tlb_all,
- .tlb_mm = tsunami_flush_tlb_mm,
- .tlb_page = tsunami_flush_tlb_page,
- .tlb_range = tsunami_flush_tlb_range,
- .page_to_ram = tsunami_flush_page_to_ram,
- .sig_insns = tsunami_flush_sig_insns,
- .page_for_dma = tsunami_flush_page_for_dma,
-};
-
-static void __init init_tsunami(void)
-{
- /*
- * Tsunami's pretty sane, Sun and TI actually got it
- * somewhat right this time. Fujitsu should have
- * taken some lessons from them.
- */
-
- srmmu_name = "TI Tsunami";
- sparc32_cachetlb_ops = &tsunami_ops;
- poke_srmmu = poke_tsunami;
-
- tsunami_setup_blockops();
-}
-
-static void poke_viking(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
- static int smp_catch;
-
- if (viking_mxcc_present) {
- unsigned long mxcc_control = mxcc_get_creg();
-
- mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
- mxcc_control &= ~(MXCC_CTL_RRC);
- mxcc_set_creg(mxcc_control);
-
- /*
- * We don't need memory parity checks.
- * XXX This is a mess, have to dig out later. ecd.
- viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
- */
-
- /* We do cache ptables on MXCC. */
- mreg |= VIKING_TCENABLE;
- } else {
- unsigned long bpreg;
-
- mreg &= ~(VIKING_TCENABLE);
- if (smp_catch++) {
- /* Must disable mixed-cmd mode here for other cpu's. */
- bpreg = viking_get_bpreg();
- bpreg &= ~(VIKING_ACTION_MIX);
- viking_set_bpreg(bpreg);
-
- /* Just in case PROM does something funny. */
- msi_set_sync();
- }
- }
-
- mreg |= VIKING_SPENABLE;
- mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
- mreg |= VIKING_SBENABLE;
- mreg &= ~(VIKING_ACENABLE);
- srmmu_set_mmureg(mreg);
-}
-
-static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
- .cache_all = viking_flush_cache_all,
- .cache_mm = viking_flush_cache_mm,
- .cache_page = viking_flush_cache_page,
- .cache_range = viking_flush_cache_range,
- .tlb_all = viking_flush_tlb_all,
- .tlb_mm = viking_flush_tlb_mm,
- .tlb_page = viking_flush_tlb_page,
- .tlb_range = viking_flush_tlb_range,
- .page_to_ram = viking_flush_page_to_ram,
- .sig_insns = viking_flush_sig_insns,
- .page_for_dma = viking_flush_page_for_dma,
-};
-
-#ifdef CONFIG_SMP
-/* On sun4d the cpu broadcasts local TLB flushes, so we can just
- * perform the local TLB flush and all the other cpus will see it.
- * But, unfortunately, there is a bug in the sun4d XBUS backplane
- * that requires that we add some synchronization to these flushes.
- *
- * The bug is that the fifo which keeps track of all the pending TLB
- * broadcasts in the system is an entry or two too small, so if we
- * have too many going at once we'll overflow that fifo and lose a TLB
- * flush resulting in corruption.
- *
- * Our workaround is to take a global spinlock around the TLB flushes,
- * which guarentees we won't ever have too many pending. It's a big
- * hammer, but a semaphore like system to make sure we only have N TLB
- * flushes going at once will require SMP locking anyways so there's
- * no real value in trying any harder than this.
- */
-static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
- .cache_all = viking_flush_cache_all,
- .cache_mm = viking_flush_cache_mm,
- .cache_page = viking_flush_cache_page,
- .cache_range = viking_flush_cache_range,
- .tlb_all = sun4dsmp_flush_tlb_all,
- .tlb_mm = sun4dsmp_flush_tlb_mm,
- .tlb_page = sun4dsmp_flush_tlb_page,
- .tlb_range = sun4dsmp_flush_tlb_range,
- .page_to_ram = viking_flush_page_to_ram,
- .sig_insns = viking_flush_sig_insns,
- .page_for_dma = viking_flush_page_for_dma,
-};
-#endif
-
-static void __init init_viking(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
-
- /* Ahhh, the viking. SRMMU VLSI abortion number two... */
- if (mreg & VIKING_MMODE) {
- srmmu_name = "TI Viking";
- viking_mxcc_present = 0;
- msi_set_sync();
-
- /*
- * We need this to make sure old viking takes no hits
- * on its cache for dma snoops to workaround the
- * "load from non-cacheable memory" interrupt bug.
- * This is only necessary because of the new way in
- * which we use the IOMMU.
- */
- viking_ops.page_for_dma = viking_flush_page;
-#ifdef CONFIG_SMP
- viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
-#endif
- flush_page_for_dma_global = 0;
- } else {
- srmmu_name = "TI Viking/MXCC";
- viking_mxcc_present = 1;
- srmmu_cache_pagetables = 1;
- }
-
- sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
- &viking_ops;
-#ifdef CONFIG_SMP
- if (sparc_cpu_model == sun4d)
- sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
- &viking_sun4d_smp_ops;
-#endif
-
- poke_srmmu = poke_viking;
-}
-
-/* Probe for the srmmu chip version. */
-static void __init get_srmmu_type(void)
-{
- unsigned long mreg, psr;
- unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
-
- mreg = srmmu_get_mmureg(); psr = get_psr();
- mod_typ = (mreg & 0xf0000000) >> 28;
- mod_rev = (mreg & 0x0f000000) >> 24;
- psr_typ = (psr >> 28) & 0xf;
- psr_vers = (psr >> 24) & 0xf;
-
- /* First, check for sparc-leon. */
- if (sparc_cpu_model == sparc_leon) {
- init_leon();
- return;
- }
-
- /* Second, check for HyperSparc or Cypress. */
- if (mod_typ == 1) {
- switch (mod_rev) {
- case 7:
- /* UP or MP Hypersparc */
- init_hypersparc();
- break;
- case 0:
- case 2:
- case 10:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- default:
- prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
- prom_halt();
- break;
- }
- return;
- }
-
- /* Now Fujitsu TurboSparc. It might happen that it is
- * in Swift emulation mode, so we will check later...
- */
- if (psr_typ == 0 && psr_vers == 5) {
- init_turbosparc();
- return;
- }
-
- /* Next check for Fujitsu Swift. */
- if (psr_typ == 0 && psr_vers == 4) {
- phandle cpunode;
- char node_str[128];
-
- /* Look if it is not a TurboSparc emulating Swift... */
- cpunode = prom_getchild(prom_root_node);
- while ((cpunode = prom_getsibling(cpunode)) != 0) {
- prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
- if (!strcmp(node_str, "cpu")) {
- if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
- prom_getintdefault(cpunode, "psr-version", 1) == 5) {
- init_turbosparc();
- return;
- }
- break;
- }
- }
-
- init_swift();
- return;
- }
-
- /* Now the Viking family of srmmu. */
- if (psr_typ == 4 &&
- ((psr_vers == 0) ||
- ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
- init_viking();
- return;
- }
-
- /* Finally the Tsunami. */
- if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
- init_tsunami();
- return;
- }
-
- /* Oh well */
- srmmu_is_bad();
-}
-
#ifdef CONFIG_SMP
/* Local cross-calls. */
static void smp_flush_page_for_dma(unsigned long page)
@@ -1734,34 +1006,20 @@ static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
};
#endif
-/* Load up routines and constants for sun4m and sun4d mmu */
+/* Load up routines and constants for mmu */
void __init load_mmu(void)
{
/* Functions */
- get_srmmu_type();
+ init_leon();
#ifdef CONFIG_SMP
/* El switcheroo... */
local_ops = sparc32_cachetlb_ops;
- if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
- smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
- smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
- smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
- smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
- }
-
- if (poke_srmmu == poke_viking) {
- /* Avoid unnecessary cross calls. */
- smp_cachetlb_ops.cache_all = local_ops->cache_all;
- smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
- smp_cachetlb_ops.cache_range = local_ops->cache_range;
- smp_cachetlb_ops.cache_page = local_ops->cache_page;
-
- smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
- smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
- smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
- }
+ smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
+ smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
+ smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
+ smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
/* It really is const after this point. */
sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
diff --git a/arch/sparc/mm/swift.S b/arch/sparc/mm/swift.S
deleted file mode 100644
index f414bfd8d899..000000000000
--- a/arch/sparc/mm/swift.S
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * swift.S: MicroSparc-II mmu/cache operations.
- *
- * Copyright (C) 1999 David S. Miller ([email protected])
- */
-
-#include <asm/psr.h>
-#include <asm/asi.h>
-#include <asm/page.h>
-#include <asm/pgtsrmmu.h>
-#include <asm/asm-offsets.h>
-
- .text
- .align 4
-
-#if 1 /* XXX screw this, I can't get the VAC flushes working
- * XXX reliably... -DaveM
- */
- .globl swift_flush_cache_all, swift_flush_cache_mm
- .globl swift_flush_cache_range, swift_flush_cache_page
- .globl swift_flush_page_for_dma
- .globl swift_flush_page_to_ram
-
-swift_flush_cache_all:
-swift_flush_cache_mm:
-swift_flush_cache_range:
-swift_flush_cache_page:
-swift_flush_page_for_dma:
-swift_flush_page_to_ram:
- sethi %hi(0x2000), %o0
-1: subcc %o0, 0x10, %o0
- add %o0, %o0, %o1
- sta %g0, [%o0] ASI_M_DATAC_TAG
- bne 1b
- sta %g0, [%o1] ASI_M_TXTC_TAG
- retl
- nop
-#else
-
- .globl swift_flush_cache_all
-swift_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
-
- /* Just clear out all the tags. */
- sethi %hi(16 * 1024), %o0
-1: subcc %o0, 16, %o0
- sta %g0, [%o0] ASI_M_TXTC_TAG
- bne 1b
- sta %g0, [%o0] ASI_M_DATAC_TAG
- retl
- nop
-
- .globl swift_flush_cache_mm
-swift_flush_cache_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be swift_flush_cache_mm_out
- WINDOW_FLUSH(%g4, %g5)
- rd %psr, %g1
- andn %g1, PSR_ET, %g3
- wr %g3, 0x0, %psr
- nop
- nop
- mov SRMMU_CTX_REG, %g7
- lda [%g7] ASI_M_MMUREGS, %g5
- sta %g2, [%g7] ASI_M_MMUREGS
-
-#if 1
- sethi %hi(0x2000), %o0
-1: subcc %o0, 0x10, %o0
- sta %g0, [%o0] ASI_M_FLUSH_CTX
- bne 1b
- nop
-#else
- clr %o0
- or %g0, 2048, %g7
- or %g0, 2048, %o1
- add %o1, 2048, %o2
- add %o2, 2048, %o3
- mov 16, %o4
- add %o4, 2048, %o5
- add %o5, 2048, %g2
- add %g2, 2048, %g3
-1: sta %g0, [%o0 ] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
- subcc %g7, 32, %g7
- bne 1b
- add %o0, 32, %o0
-#endif
-
- mov SRMMU_CTX_REG, %g7
- sta %g5, [%g7] ASI_M_MMUREGS
- wr %g1, 0x0, %psr
- nop
- nop
-swift_flush_cache_mm_out:
- retl
- nop
-
- .globl swift_flush_cache_range
-swift_flush_cache_range:
- ld [%o0 + VMA_VM_MM], %o0
- sub %o2, %o1, %o2
- sethi %hi(4096), %o3
- cmp %o2, %o3
- bgu swift_flush_cache_mm
- nop
- b 70f
- nop
-
- .globl swift_flush_cache_page
-swift_flush_cache_page:
- ld [%o0 + VMA_VM_MM], %o0
-70:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be swift_flush_cache_page_out
- WINDOW_FLUSH(%g4, %g5)
- rd %psr, %g1
- andn %g1, PSR_ET, %g3
- wr %g3, 0x0, %psr
- nop
- nop
- mov SRMMU_CTX_REG, %g7
- lda [%g7] ASI_M_MMUREGS, %g5
- sta %g2, [%g7] ASI_M_MMUREGS
-
- andn %o1, (PAGE_SIZE - 1), %o1
-#if 1
- sethi %hi(0x1000), %o0
-1: subcc %o0, 0x10, %o0
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- bne 1b
- nop
-#else
- or %g0, 512, %g7
- or %g0, 512, %o0
- add %o0, 512, %o2
- add %o2, 512, %o3
- add %o3, 512, %o4
- add %o4, 512, %o5
- add %o5, 512, %g3
- add %g3, 512, %g4
-1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
- subcc %g7, 16, %g7
- bne 1b
- add %o1, 16, %o1
-#endif
-
- mov SRMMU_CTX_REG, %g7
- sta %g5, [%g7] ASI_M_MMUREGS
- wr %g1, 0x0, %psr
- nop
- nop
-swift_flush_cache_page_out:
- retl
- nop
-
- /* Swift is write-thru, however it is not
- * I/O nor TLB-walk coherent. Also it has
- * caches which are virtually indexed and tagged.
- */
- .globl swift_flush_page_for_dma
- .globl swift_flush_page_to_ram
-swift_flush_page_for_dma:
-swift_flush_page_to_ram:
- andn %o0, (PAGE_SIZE - 1), %o1
-#if 1
- sethi %hi(0x1000), %o0
-1: subcc %o0, 0x10, %o0
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- bne 1b
- nop
-#else
- or %g0, 512, %g7
- or %g0, 512, %o0
- add %o0, 512, %o2
- add %o2, 512, %o3
- add %o3, 512, %o4
- add %o4, 512, %o5
- add %o5, 512, %g3
- add %g3, 512, %g4
-1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
- subcc %g7, 16, %g7
- bne 1b
- add %o1, 16, %o1
-#endif
- retl
- nop
-#endif
-
- .globl swift_flush_sig_insns
-swift_flush_sig_insns:
- flush %o1
- retl
- flush %o1 + 4
-
- .globl swift_flush_tlb_mm
- .globl swift_flush_tlb_range
- .globl swift_flush_tlb_all
-swift_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
-swift_flush_tlb_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be swift_flush_tlb_all_out
-swift_flush_tlb_all:
- mov 0x400, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-swift_flush_tlb_all_out:
- retl
- nop
-
- .globl swift_flush_tlb_page
-swift_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- andn %o1, (PAGE_SIZE - 1), %o1
- cmp %o3, -1
- be swift_flush_tlb_page_out
- nop
-#if 1
- mov 0x400, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-#else
- lda [%g1] ASI_M_MMUREGS, %g5
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
-#endif
-swift_flush_tlb_page_out:
- retl
- nop
diff --git a/arch/sparc/mm/tsunami.S b/arch/sparc/mm/tsunami.S
deleted file mode 100644
index 62b742df65dc..000000000000
--- a/arch/sparc/mm/tsunami.S
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * tsunami.S: High speed MicroSparc-I mmu/cache operations.
- *
- * Copyright (C) 1997 David S. Miller ([email protected])
- */
-
-#include <asm/ptrace.h>
-#include <asm/asm-offsets.h>
-#include <asm/psr.h>
-#include <asm/asi.h>
-#include <asm/page.h>
-#include <asm/pgtsrmmu.h>
-
- .text
- .align 4
-
- .globl tsunami_flush_cache_all, tsunami_flush_cache_mm
- .globl tsunami_flush_cache_range, tsunami_flush_cache_page
- .globl tsunami_flush_page_to_ram, tsunami_flush_page_for_dma
- .globl tsunami_flush_sig_insns
- .globl tsunami_flush_tlb_all, tsunami_flush_tlb_mm
- .globl tsunami_flush_tlb_range, tsunami_flush_tlb_page
-
- /* Sliiick... */
-tsunami_flush_cache_page:
-tsunami_flush_cache_range:
- ld [%o0 + VMA_VM_MM], %o0
-tsunami_flush_cache_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be tsunami_flush_cache_out
-tsunami_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
-tsunami_flush_page_for_dma:
- sta %g0, [%g0] ASI_M_IC_FLCLEAR
- sta %g0, [%g0] ASI_M_DC_FLCLEAR
-tsunami_flush_cache_out:
-tsunami_flush_page_to_ram:
- retl
- nop
-
-tsunami_flush_sig_insns:
- flush %o1
- retl
- flush %o1 + 4
-
- /* More slick stuff... */
-tsunami_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
-tsunami_flush_tlb_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be tsunami_flush_tlb_out
-tsunami_flush_tlb_all:
- mov 0x400, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- nop
- nop
- nop
- nop
- nop
-tsunami_flush_tlb_out:
- retl
- nop
-
- /* This one can be done in a fine grained manner... */
-tsunami_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- andn %o1, (PAGE_SIZE - 1), %o1
- cmp %o3, -1
- be tsunami_flush_tlb_page_out
- lda [%g1] ASI_M_MMUREGS, %g5
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- nop
- nop
- nop
- nop
- nop
-tsunami_flush_tlb_page_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
-#define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \
- ldd [src + offset + 0x18], t0; \
- std t0, [dst + offset + 0x18]; \
- ldd [src + offset + 0x10], t2; \
- std t2, [dst + offset + 0x10]; \
- ldd [src + offset + 0x08], t0; \
- std t0, [dst + offset + 0x08]; \
- ldd [src + offset + 0x00], t2; \
- std t2, [dst + offset + 0x00];
-
-tsunami_copy_1page:
-/* NOTE: This routine has to be shorter than 70insns --jj */
- or %g0, (PAGE_SIZE >> 8), %g1
-1:
- MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5)
- subcc %g1, 1, %g1
- add %o0, 0x100, %o0
- bne 1b
- add %o1, 0x100, %o1
-
- .globl tsunami_setup_blockops
-tsunami_setup_blockops:
- sethi %hi(__copy_1page), %o0
- or %o0, %lo(__copy_1page), %o0
- sethi %hi(tsunami_copy_1page), %o1
- or %o1, %lo(tsunami_copy_1page), %o1
- sethi %hi(tsunami_setup_blockops), %o2
- or %o2, %lo(tsunami_setup_blockops), %o2
- ld [%o1], %o4
-1: add %o1, 4, %o1
- st %o4, [%o0]
- add %o0, 4, %o0
- cmp %o1, %o2
- bne 1b
- ld [%o1], %o4
- sta %g0, [%g0] ASI_M_IC_FLCLEAR
- sta %g0, [%g0] ASI_M_DC_FLCLEAR
- retl
- nop
diff --git a/arch/sparc/mm/viking.S b/arch/sparc/mm/viking.S
deleted file mode 100644
index 48f062de7a7f..000000000000
--- a/arch/sparc/mm/viking.S
+++ /dev/null
@@ -1,284 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * viking.S: High speed Viking cache/mmu operations
- *
- * Copyright (C) 1997 Eddie C. Dost ([email protected])
- * Copyright (C) 1997,1998,1999 Jakub Jelinek ([email protected])
- * Copyright (C) 1999 Pavel Semerad ([email protected])
- */
-
-#include <asm/ptrace.h>
-#include <asm/psr.h>
-#include <asm/asm-offsets.h>
-#include <asm/asi.h>
-#include <asm/mxcc.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pgtsrmmu.h>
-#include <asm/viking.h>
-
-#ifdef CONFIG_SMP
- .data
- .align 4
-sun4dsmp_flush_tlb_spin:
- .word 0
-#endif
-
- .text
- .align 4
-
- .globl viking_flush_cache_all, viking_flush_cache_mm
- .globl viking_flush_cache_range, viking_flush_cache_page
- .globl viking_flush_page, viking_mxcc_flush_page
- .globl viking_flush_page_for_dma, viking_flush_page_to_ram
- .globl viking_flush_sig_insns
- .globl viking_flush_tlb_all, viking_flush_tlb_mm
- .globl viking_flush_tlb_range, viking_flush_tlb_page
-
-viking_flush_page:
- sethi %hi(PAGE_OFFSET), %g2
- sub %o0, %g2, %g3
- srl %g3, 12, %g1 ! ppage >> 12
-
- clr %o1 ! set counter, 0 - 127
- sethi %hi(PAGE_OFFSET + PAGE_SIZE - 0x80000000), %o3
- sethi %hi(0x80000000), %o4
- sethi %hi(VIKING_PTAG_VALID), %o5
- sethi %hi(2*PAGE_SIZE), %o0
- sethi %hi(PAGE_SIZE), %g7
- clr %o2 ! block counter, 0 - 3
-5:
- sll %o1, 5, %g4
- or %g4, %o4, %g4 ! 0x80000000 | (set << 5)
-
- sll %o2, 26, %g5 ! block << 26
-6:
- or %g5, %g4, %g5
- ldda [%g5] ASI_M_DATAC_TAG, %g2
- cmp %g3, %g1 ! ptag == ppage?
- bne 7f
- inc %o2
-
- andcc %g2, %o5, %g0 ! ptag VALID?
- be 7f
- add %g4, %o3, %g2 ! (PAGE_OFFSET + PAGE_SIZE) | (set << 5)
- ld [%g2], %g3
- ld [%g2 + %g7], %g3
- add %g2, %o0, %g2
- ld [%g2], %g3
- ld [%g2 + %g7], %g3
- add %g2, %o0, %g2
- ld [%g2], %g3
- ld [%g2 + %g7], %g3
- add %g2, %o0, %g2
- ld [%g2], %g3
- b 8f
- ld [%g2 + %g7], %g3
-
-7:
- cmp %o2, 3
- ble 6b
- sll %o2, 26, %g5 ! block << 26
-
-8: inc %o1
- cmp %o1, 0x7f
- ble 5b
- clr %o2
-
-9: retl
- nop
-
-viking_mxcc_flush_page:
- sethi %hi(PAGE_OFFSET), %g2
- sub %o0, %g2, %g3
- sub %g3, -PAGE_SIZE, %g3 ! ppage + PAGE_SIZE
- sethi %hi(MXCC_SRCSTREAM), %o3 ! assume %hi(MXCC_SRCSTREAM) == %hi(MXCC_DESTSTREAM)
- mov 0x10, %g2 ! set cacheable bit
- or %o3, %lo(MXCC_SRCSTREAM), %o2
- or %o3, %lo(MXCC_DESSTREAM), %o3
- sub %g3, MXCC_STREAM_SIZE, %g3
-6:
- stda %g2, [%o2] ASI_M_MXCC
- stda %g2, [%o3] ASI_M_MXCC
- andncc %g3, PAGE_MASK, %g0
- bne 6b
- sub %g3, MXCC_STREAM_SIZE, %g3
-
-9: retl
- nop
-
-viking_flush_cache_page:
-viking_flush_cache_range:
-#ifndef CONFIG_SMP
- ld [%o0 + VMA_VM_MM], %o0
-#endif
-viking_flush_cache_mm:
-#ifndef CONFIG_SMP
- ld [%o0 + AOFF_mm_context], %g1
- cmp %g1, -1
- bne viking_flush_cache_all
- nop
- b,a viking_flush_cache_out
-#endif
-viking_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
-viking_flush_cache_out:
- retl
- nop
-
-viking_flush_tlb_all:
- mov 0x400, %g1
- retl
- sta %g0, [%g1] ASI_M_FLUSH_PROBE
-
-viking_flush_tlb_mm:
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o1
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o1, -1
- be 1f
-#endif
- mov 0x300, %g2
- sta %o1, [%g1] ASI_M_MMUREGS
- sta %g0, [%g2] ASI_M_FLUSH_PROBE
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-#ifndef CONFIG_SMP
-1: retl
- nop
-#endif
-
-viking_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be 2f
-#endif
- sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
- sta %o3, [%g1] ASI_M_MMUREGS
- and %o1, %o4, %o1
- add %o1, 0x200, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-1: sub %o1, %o4, %o1
- cmp %o1, %o2
- blu,a 1b
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-#ifndef CONFIG_SMP
-2: retl
- nop
-#endif
-
-viking_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be 1f
-#endif
- and %o1, PAGE_MASK, %o1
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-#ifndef CONFIG_SMP
-1: retl
- nop
-#endif
-
-viking_flush_page_to_ram:
-viking_flush_page_for_dma:
-viking_flush_sig_insns:
- retl
- nop
-
-#ifdef CONFIG_SMP
- .globl sun4dsmp_flush_tlb_all, sun4dsmp_flush_tlb_mm
- .globl sun4dsmp_flush_tlb_range, sun4dsmp_flush_tlb_page
-sun4dsmp_flush_tlb_all:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 2f
- mov 0x400, %g1
- sta %g0, [%g1] ASI_M_FLUSH_PROBE
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-2: tst %g5
- bne,a 2b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
-
-sun4dsmp_flush_tlb_mm:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 2f
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o1
- lda [%g1] ASI_M_MMUREGS, %g5
- mov 0x300, %g2
- sta %o1, [%g1] ASI_M_MMUREGS
- sta %g0, [%g2] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-2: tst %g5
- bne,a 2b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
-
-sun4dsmp_flush_tlb_range:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 3f
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + VMA_VM_MM], %o0
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
- sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
- sta %o3, [%g1] ASI_M_MMUREGS
- and %o1, %o4, %o1
- add %o1, 0x200, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-2: sub %o1, %o4, %o1
- cmp %o1, %o2
- blu,a 2b
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-3: tst %g5
- bne,a 3b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
-
-sun4dsmp_flush_tlb_page:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 2f
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + VMA_VM_MM], %o0
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
- and %o1, PAGE_MASK, %o1
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-2: tst %g5
- bne,a 2b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
- nop
-#endif
--
2.34.1
From: Sam Ravnborg <[email protected]>
The p9100 driver is only relevant for the Sparcbook 3 machine,
and with sun4m support removed this driver is no longer relevant.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Thomas Zimmermann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
Cc: Helge Deller <[email protected]>
---
drivers/video/fbdev/Kconfig | 8 -
drivers/video/fbdev/Makefile | 1 -
drivers/video/fbdev/p9100.c | 372 -------------------------------------------
3 files changed, 381 deletions(-)
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index a74f7fd3ba0c..9f1d365ed040 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -550,14 +550,6 @@ config FB_CG14
This is the frame buffer device driver for the CGfourteen frame
buffer on Desktop SPARCsystems with the SX graphics option.
-config FB_P9100
- bool "P9100 (Sparcbook 3 only) support"
- depends on FB_SBUS
- select FB_SBUS_HELPERS
- help
- This is the frame buffer device driver for the P9100 card
- supported on Sparcbook 3 machines.
-
config FB_LEO
bool "Leo (ZX) support"
depends on FB_SBUS
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
index 3eecd51267fa..3f4ac048d355 100644
--- a/drivers/video/fbdev/Makefile
+++ b/drivers/video/fbdev/Makefile
@@ -50,7 +50,6 @@ obj-$(CONFIG_FB_CG6) += cg6.o
obj-$(CONFIG_FB_CG3) += cg3.o
obj-$(CONFIG_FB_BW2) += bw2.o
obj-$(CONFIG_FB_CG14) += cg14.o
-obj-$(CONFIG_FB_P9100) += p9100.o
obj-$(CONFIG_FB_TCX) += tcx.o
obj-$(CONFIG_FB_LEO) += leo.o
obj-$(CONFIG_FB_ACORN) += acornfb.o
diff --git a/drivers/video/fbdev/p9100.c b/drivers/video/fbdev/p9100.c
deleted file mode 100644
index e1356f8a866e..000000000000
--- a/drivers/video/fbdev/p9100.c
+++ /dev/null
@@ -1,372 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* p9100.c: P9100 frame buffer driver
- *
- * Copyright (C) 2003, 2006 David S. Miller ([email protected])
- * Copyright 1999 Derrick J Brashear ([email protected])
- *
- * Driver layout based loosely on tgafb.c, see that file for credits.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/fb.h>
-#include <linux/mm.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-
-#include <asm/io.h>
-#include <asm/fbio.h>
-
-#include "sbuslib.h"
-
-/*
- * Local functions.
- */
-
-static int p9100_setcolreg(unsigned, unsigned, unsigned, unsigned,
- unsigned, struct fb_info *);
-static int p9100_blank(int, struct fb_info *);
-
-static int p9100_sbusfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
-static int p9100_sbusfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg);
-
-/*
- * Frame buffer operations
- */
-
-static const struct fb_ops p9100_ops = {
- .owner = THIS_MODULE,
- FB_DEFAULT_SBUS_OPS(p9100),
- .fb_setcolreg = p9100_setcolreg,
- .fb_blank = p9100_blank,
-};
-
-/* P9100 control registers */
-#define P9100_SYSCTL_OFF 0x0UL
-#define P9100_VIDEOCTL_OFF 0x100UL
-#define P9100_VRAMCTL_OFF 0x180UL
-#define P9100_RAMDAC_OFF 0x200UL
-#define P9100_VIDEOCOPROC_OFF 0x400UL
-
-/* P9100 command registers */
-#define P9100_CMD_OFF 0x0UL
-
-/* P9100 framebuffer memory */
-#define P9100_FB_OFF 0x0UL
-
-/* 3 bits: 2=8bpp 3=16bpp 5=32bpp 7=24bpp */
-#define SYS_CONFIG_PIXELSIZE_SHIFT 26
-
-#define SCREENPAINT_TIMECTL1_ENABLE_VIDEO 0x20 /* 0 = off, 1 = on */
-
-struct p9100_regs {
- /* Registers for the system control */
- u32 sys_base;
- u32 sys_config;
- u32 sys_intr;
- u32 sys_int_ena;
- u32 sys_alt_rd;
- u32 sys_alt_wr;
- u32 sys_xxx[58];
-
- /* Registers for the video control */
- u32 vid_base;
- u32 vid_hcnt;
- u32 vid_htotal;
- u32 vid_hsync_rise;
- u32 vid_hblank_rise;
- u32 vid_hblank_fall;
- u32 vid_hcnt_preload;
- u32 vid_vcnt;
- u32 vid_vlen;
- u32 vid_vsync_rise;
- u32 vid_vblank_rise;
- u32 vid_vblank_fall;
- u32 vid_vcnt_preload;
- u32 vid_screenpaint_addr;
- u32 vid_screenpaint_timectl1;
- u32 vid_screenpaint_qsfcnt;
- u32 vid_screenpaint_timectl2;
- u32 vid_xxx[15];
-
- /* Registers for the video control */
- u32 vram_base;
- u32 vram_memcfg;
- u32 vram_refresh_pd;
- u32 vram_refresh_cnt;
- u32 vram_raslo_max;
- u32 vram_raslo_cur;
- u32 pwrup_cfg;
- u32 vram_xxx[25];
-
- /* Registers for IBM RGB528 Palette */
- u32 ramdac_cmap_wridx;
- u32 ramdac_palette_data;
- u32 ramdac_pixel_mask;
- u32 ramdac_palette_rdaddr;
- u32 ramdac_idx_lo;
- u32 ramdac_idx_hi;
- u32 ramdac_idx_data;
- u32 ramdac_idx_ctl;
- u32 ramdac_xxx[1784];
-};
-
-struct p9100_cmd_parameng {
- u32 parameng_status;
- u32 parameng_bltcmd;
- u32 parameng_quadcmd;
-};
-
-struct p9100_par {
- spinlock_t lock;
- struct p9100_regs __iomem *regs;
-
- u32 flags;
-#define P9100_FLAG_BLANKED 0x00000001
-
- unsigned long which_io;
-};
-
-/**
- * p9100_setcolreg - Optional function. Sets a color register.
- * @regno: boolean, 0 copy local, 1 get_user() function
- * @red: frame buffer colormap structure
- * @green: The green value which can be up to 16 bits wide
- * @blue: The blue value which can be up to 16 bits wide.
- * @transp: If supported the alpha value which can be up to 16 bits wide.
- * @info: frame buffer info structure
- */
-static int p9100_setcolreg(unsigned regno,
- unsigned red, unsigned green, unsigned blue,
- unsigned transp, struct fb_info *info)
-{
- struct p9100_par *par = (struct p9100_par *) info->par;
- struct p9100_regs __iomem *regs = par->regs;
- unsigned long flags;
-
- if (regno >= 256)
- return 1;
-
- red >>= 8;
- green >>= 8;
- blue >>= 8;
-
- spin_lock_irqsave(&par->lock, flags);
-
- sbus_writel((regno << 16), ®s->ramdac_cmap_wridx);
- sbus_writel((red << 16), ®s->ramdac_palette_data);
- sbus_writel((green << 16), ®s->ramdac_palette_data);
- sbus_writel((blue << 16), ®s->ramdac_palette_data);
-
- spin_unlock_irqrestore(&par->lock, flags);
-
- return 0;
-}
-
-/**
- * p9100_blank - Optional function. Blanks the display.
- * @blank: the blank mode we want.
- * @info: frame buffer structure that represents a single frame buffer
- */
-static int
-p9100_blank(int blank, struct fb_info *info)
-{
- struct p9100_par *par = (struct p9100_par *) info->par;
- struct p9100_regs __iomem *regs = par->regs;
- unsigned long flags;
- u32 val;
-
- spin_lock_irqsave(&par->lock, flags);
-
- switch (blank) {
- case FB_BLANK_UNBLANK: /* Unblanking */
- val = sbus_readl(®s->vid_screenpaint_timectl1);
- val |= SCREENPAINT_TIMECTL1_ENABLE_VIDEO;
- sbus_writel(val, ®s->vid_screenpaint_timectl1);
- par->flags &= ~P9100_FLAG_BLANKED;
- break;
-
- case FB_BLANK_NORMAL: /* Normal blanking */
- case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
- case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
- case FB_BLANK_POWERDOWN: /* Poweroff */
- val = sbus_readl(®s->vid_screenpaint_timectl1);
- val &= ~SCREENPAINT_TIMECTL1_ENABLE_VIDEO;
- sbus_writel(val, ®s->vid_screenpaint_timectl1);
- par->flags |= P9100_FLAG_BLANKED;
- break;
- }
-
- spin_unlock_irqrestore(&par->lock, flags);
-
- return 0;
-}
-
-static struct sbus_mmap_map p9100_mmap_map[] = {
- { CG3_MMAP_OFFSET, 0, SBUS_MMAP_FBSIZE(1) },
- { 0, 0, 0 }
-};
-
-static int p9100_sbusfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
-{
- struct p9100_par *par = (struct p9100_par *)info->par;
-
- return sbusfb_mmap_helper(p9100_mmap_map,
- info->fix.smem_start, info->fix.smem_len,
- par->which_io, vma);
-}
-
-static int p9100_sbusfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
-{
- /* Make it look like a cg3. */
- return sbusfb_ioctl_helper(cmd, arg, info,
- FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
-}
-
-/*
- * Initialisation
- */
-
-static void p9100_init_fix(struct fb_info *info, int linebytes, struct device_node *dp)
-{
- snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
-
- info->fix.type = FB_TYPE_PACKED_PIXELS;
- info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
-
- info->fix.line_length = linebytes;
-
- info->fix.accel = FB_ACCEL_SUN_CGTHREE;
-}
-
-static int p9100_probe(struct platform_device *op)
-{
- struct device_node *dp = op->dev.of_node;
- struct fb_info *info;
- struct p9100_par *par;
- int linebytes, err;
-
- info = framebuffer_alloc(sizeof(struct p9100_par), &op->dev);
-
- err = -ENOMEM;
- if (!info)
- goto out_err;
- par = info->par;
-
- spin_lock_init(&par->lock);
-
- /* This is the framebuffer and the only resource apps can mmap. */
- info->fix.smem_start = op->resource[2].start;
- par->which_io = op->resource[2].flags & IORESOURCE_BITS;
-
- sbusfb_fill_var(&info->var, dp, 8);
- info->var.red.length = 8;
- info->var.green.length = 8;
- info->var.blue.length = 8;
-
- linebytes = of_getintprop_default(dp, "linebytes", info->var.xres);
- info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
-
- par->regs = of_ioremap(&op->resource[0], 0,
- sizeof(struct p9100_regs), "p9100 regs");
- if (!par->regs)
- goto out_release_fb;
-
- info->fbops = &p9100_ops;
- info->screen_base = of_ioremap(&op->resource[2], 0,
- info->fix.smem_len, "p9100 ram");
- if (!info->screen_base)
- goto out_unmap_regs;
-
- p9100_blank(FB_BLANK_UNBLANK, info);
-
- if (fb_alloc_cmap(&info->cmap, 256, 0))
- goto out_unmap_screen;
-
- p9100_init_fix(info, linebytes, dp);
-
- err = register_framebuffer(info);
- if (err < 0)
- goto out_dealloc_cmap;
-
- fb_set_cmap(&info->cmap, info);
-
- dev_set_drvdata(&op->dev, info);
-
- printk(KERN_INFO "%pOF: p9100 at %lx:%lx\n",
- dp,
- par->which_io, info->fix.smem_start);
-
- return 0;
-
-out_dealloc_cmap:
- fb_dealloc_cmap(&info->cmap);
-
-out_unmap_screen:
- of_iounmap(&op->resource[2], info->screen_base, info->fix.smem_len);
-
-out_unmap_regs:
- of_iounmap(&op->resource[0], par->regs, sizeof(struct p9100_regs));
-
-out_release_fb:
- framebuffer_release(info);
-
-out_err:
- return err;
-}
-
-static void p9100_remove(struct platform_device *op)
-{
- struct fb_info *info = dev_get_drvdata(&op->dev);
- struct p9100_par *par = info->par;
-
- unregister_framebuffer(info);
- fb_dealloc_cmap(&info->cmap);
-
- of_iounmap(&op->resource[0], par->regs, sizeof(struct p9100_regs));
- of_iounmap(&op->resource[2], info->screen_base, info->fix.smem_len);
-
- framebuffer_release(info);
-}
-
-static const struct of_device_id p9100_match[] = {
- {
- .name = "p9100",
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, p9100_match);
-
-static struct platform_driver p9100_driver = {
- .driver = {
- .name = "p9100",
- .of_match_table = p9100_match,
- },
- .probe = p9100_probe,
- .remove_new = p9100_remove,
-};
-
-static int __init p9100_init(void)
-{
- if (fb_get_options("p9100fb", NULL))
- return -ENODEV;
-
- return platform_driver_register(&p9100_driver);
-}
-
-static void __exit p9100_exit(void)
-{
- platform_driver_unregister(&p9100_driver);
-}
-
-module_init(p9100_init);
-module_exit(p9100_exit);
-
-MODULE_DESCRIPTION("framebuffer driver for P9100 chipsets");
-MODULE_AUTHOR("David S. Miller <[email protected]>");
-MODULE_VERSION("2.0");
-MODULE_LICENSE("GPL");
--
2.34.1
From: Sam Ravnborg <[email protected]>
The uctrl driver is only relevant for the Sparcbook 3 machine,
and with sun4m support removed this driver is no logner relevant.
Signed-off-by: Sam Ravnborg <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
drivers/sbus/char/Kconfig | 8 -
drivers/sbus/char/Makefile | 1 -
drivers/sbus/char/uctrl.c | 434 ---------------------------------------------
3 files changed, 443 deletions(-)
diff --git a/drivers/sbus/char/Kconfig b/drivers/sbus/char/Kconfig
index 7c0a308e4959..8b80abc554ed 100644
--- a/drivers/sbus/char/Kconfig
+++ b/drivers/sbus/char/Kconfig
@@ -21,14 +21,6 @@ config OBP_FLASH
The OpenBoot PROM on Ultra systems is flashable. If you want to be
able to upgrade the OBP firmware, say Y here.
-config TADPOLE_TS102_UCTRL
- tristate "Tadpole TS102 Microcontroller support"
- help
- Say Y here to directly support the TS102 Microcontroller interface
- on the Tadpole Sparcbook 3. This device handles power-management
- events, and can also notice the attachment/detachment of external
- monitors and mice.
-
config BBC_I2C
tristate "UltraSPARC-III bootbus i2c controller driver"
depends on PCI && SPARC64
diff --git a/drivers/sbus/char/Makefile b/drivers/sbus/char/Makefile
index 44347c918f6b..9db2faabfae8 100644
--- a/drivers/sbus/char/Makefile
+++ b/drivers/sbus/char/Makefile
@@ -14,6 +14,5 @@ obj-$(CONFIG_ENVCTRL) += envctrl.o
obj-$(CONFIG_DISPLAY7SEG) += display7seg.o
obj-$(CONFIG_OBP_FLASH) += flash.o
obj-$(CONFIG_SUN_OPENPROMIO) += openprom.o
-obj-$(CONFIG_TADPOLE_TS102_UCTRL) += uctrl.o
obj-$(CONFIG_BBC_I2C) += bbc.o
obj-$(CONFIG_ORACLE_DAX) += oradax.o
diff --git a/drivers/sbus/char/uctrl.c b/drivers/sbus/char/uctrl.c
deleted file mode 100644
index cf15a4186d03..000000000000
--- a/drivers/sbus/char/uctrl.c
+++ /dev/null
@@ -1,434 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
- *
- * Copyright 1999 Derrick J Brashear ([email protected])
- * Copyright 2008 David S. Miller ([email protected])
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/slab.h>
-#include <linux/mutex.h>
-#include <linux/ioport.h>
-#include <linux/miscdevice.h>
-#include <linux/mm.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-
-#define DEBUG 1
-#ifdef DEBUG
-#define dprintk(x) printk x
-#else
-#define dprintk(x)
-#endif
-
-struct uctrl_regs {
- u32 uctrl_intr;
- u32 uctrl_data;
- u32 uctrl_stat;
- u32 uctrl_xxx[5];
-};
-
-struct ts102_regs {
- u32 card_a_intr;
- u32 card_a_stat;
- u32 card_a_ctrl;
- u32 card_a_xxx;
- u32 card_b_intr;
- u32 card_b_stat;
- u32 card_b_ctrl;
- u32 card_b_xxx;
- u32 uctrl_intr;
- u32 uctrl_data;
- u32 uctrl_stat;
- u32 uctrl_xxx;
- u32 ts102_xxx[4];
-};
-
-/* Bits for uctrl_intr register */
-#define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */
-#define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */
-#define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */
-#define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */
-#define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */
-#define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */
-#define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */
-#define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */
-
-/* Bits for uctrl_stat register */
-#define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */
-#define UCTRL_STAT_TXNF_STA 0x02 /* transmit FIFO not full status */
-#define UCTRL_STAT_RXNE_STA 0x04 /* receive FIFO not empty status */
-#define UCTRL_STAT_RXO_STA 0x08 /* receive FIFO overflow status */
-
-static DEFINE_MUTEX(uctrl_mutex);
-static const char *uctrl_extstatus[16] = {
- "main power available",
- "internal battery attached",
- "external battery attached",
- "external VGA attached",
- "external keyboard attached",
- "external mouse attached",
- "lid down",
- "internal battery currently charging",
- "external battery currently charging",
- "internal battery currently discharging",
- "external battery currently discharging",
-};
-
-/* Everything required for one transaction with the uctrl */
-struct uctrl_txn {
- u8 opcode;
- u8 inbits;
- u8 outbits;
- u8 *inbuf;
- u8 *outbuf;
-};
-
-struct uctrl_status {
- u8 current_temp; /* 0x07 */
- u8 reset_status; /* 0x0b */
- u16 event_status; /* 0x0c */
- u16 error_status; /* 0x10 */
- u16 external_status; /* 0x11, 0x1b */
- u8 internal_charge; /* 0x18 */
- u8 external_charge; /* 0x19 */
- u16 control_lcd; /* 0x20 */
- u8 control_bitport; /* 0x21 */
- u8 speaker_volume; /* 0x23 */
- u8 control_tft_brightness; /* 0x24 */
- u8 control_kbd_repeat_delay; /* 0x28 */
- u8 control_kbd_repeat_period; /* 0x29 */
- u8 control_screen_contrast; /* 0x2F */
-};
-
-enum uctrl_opcode {
- READ_SERIAL_NUMBER=0x1,
- READ_ETHERNET_ADDRESS=0x2,
- READ_HARDWARE_VERSION=0x3,
- READ_MICROCONTROLLER_VERSION=0x4,
- READ_MAX_TEMPERATURE=0x5,
- READ_MIN_TEMPERATURE=0x6,
- READ_CURRENT_TEMPERATURE=0x7,
- READ_SYSTEM_VARIANT=0x8,
- READ_POWERON_CYCLES=0x9,
- READ_POWERON_SECONDS=0xA,
- READ_RESET_STATUS=0xB,
- READ_EVENT_STATUS=0xC,
- READ_REAL_TIME_CLOCK=0xD,
- READ_EXTERNAL_VGA_PORT=0xE,
- READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
- READ_ERROR_STATUS=0x10,
- READ_EXTERNAL_STATUS=0x11,
- READ_USER_CONFIGURATION_AREA=0x12,
- READ_MICROCONTROLLER_VOLTAGE=0x13,
- READ_INTERNAL_BATTERY_VOLTAGE=0x14,
- READ_DCIN_VOLTAGE=0x15,
- READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
- READ_VERTICAL_POINTER_VOLTAGE=0x17,
- READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
- READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
- READ_REAL_TIME_CLOCK_ALARM=0x1A,
- READ_EVENT_STATUS_NO_RESET=0x1B,
- READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
- READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
- READ_EEPROM_STATUS=0x1E,
- CONTROL_LCD=0x20,
- CONTROL_BITPORT=0x21,
- SPEAKER_VOLUME=0x23,
- CONTROL_TFT_BRIGHTNESS=0x24,
- CONTROL_WATCHDOG=0x25,
- CONTROL_FACTORY_EEPROM_AREA=0x26,
- CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
- CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
- CONTROL_TIMEZONE=0x2A,
- CONTROL_MARK_SPACE_RATIO=0x2B,
- CONTROL_DIAGNOSTIC_MODE=0x2E,
- CONTROL_SCREEN_CONTRAST=0x2F,
- RING_BELL=0x30,
- SET_DIAGNOSTIC_STATUS=0x32,
- CLEAR_KEY_COMBINATION_TABLE=0x33,
- PERFORM_SOFTWARE_RESET=0x34,
- SET_REAL_TIME_CLOCK=0x35,
- RECALIBRATE_POINTING_STICK=0x36,
- SET_BELL_FREQUENCY=0x37,
- SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
- SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
- SET_REAL_TIME_CLOCK_ALARM=0x3B,
- READ_EEPROM=0x40,
- WRITE_EEPROM=0x41,
- WRITE_TO_STATUS_DISPLAY=0x42,
- DEFINE_SPECIAL_CHARACTER=0x43,
- DEFINE_KEY_COMBINATION_ENTRY=0x50,
- DEFINE_STRING_TABLE_ENTRY=0x51,
- DEFINE_STATUS_SCREEN_DISPLAY=0x52,
- PERFORM_EMU_COMMANDS=0x64,
- READ_EMU_REGISTER=0x65,
- WRITE_EMU_REGISTER=0x66,
- READ_EMU_RAM=0x67,
- WRITE_EMU_RAM=0x68,
- READ_BQ_REGISTER=0x69,
- WRITE_BQ_REGISTER=0x6A,
- SET_USER_PASSWORD=0x70,
- VERIFY_USER_PASSWORD=0x71,
- GET_SYSTEM_PASSWORD_KEY=0x72,
- VERIFY_SYSTEM_PASSWORD=0x73,
- POWER_OFF=0x82,
- POWER_RESTART=0x83,
-};
-
-static struct uctrl_driver {
- struct uctrl_regs __iomem *regs;
- int irq;
- int pending;
- struct uctrl_status status;
-} *global_driver;
-
-static void uctrl_get_event_status(struct uctrl_driver *);
-static void uctrl_get_external_status(struct uctrl_driver *);
-
-static long
-uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- switch (cmd) {
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int
-uctrl_open(struct inode *inode, struct file *file)
-{
- mutex_lock(&uctrl_mutex);
- uctrl_get_event_status(global_driver);
- uctrl_get_external_status(global_driver);
- mutex_unlock(&uctrl_mutex);
- return 0;
-}
-
-static irqreturn_t uctrl_interrupt(int irq, void *dev_id)
-{
- return IRQ_HANDLED;
-}
-
-static const struct file_operations uctrl_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .unlocked_ioctl = uctrl_ioctl,
- .open = uctrl_open,
-};
-
-static struct miscdevice uctrl_dev = {
- UCTRL_MINOR,
- "uctrl",
- &uctrl_fops
-};
-
-/* Wait for space to write, then write to it */
-#define WRITEUCTLDATA(value) \
-{ \
- unsigned int i; \
- for (i = 0; i < 10000; i++) { \
- if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \
- break; \
- } \
- dprintk(("write data 0x%02x\n", value)); \
- sbus_writel(value, &driver->regs->uctrl_data); \
-}
-
-/* Wait for something to read, read it, then clear the bit */
-#define READUCTLDATA(value) \
-{ \
- unsigned int i; \
- value = 0; \
- for (i = 0; i < 10000; i++) { \
- if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \
- break; \
- udelay(1); \
- } \
- value = sbus_readl(&driver->regs->uctrl_data); \
- dprintk(("read data 0x%02x\n", value)); \
- sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \
-}
-
-static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn)
-{
- int stat, incnt, outcnt, bytecnt, intr;
- u32 byte;
-
- stat = sbus_readl(&driver->regs->uctrl_stat);
- intr = sbus_readl(&driver->regs->uctrl_intr);
- sbus_writel(stat, &driver->regs->uctrl_stat);
-
- dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
-
- incnt = txn->inbits;
- outcnt = txn->outbits;
- byte = (txn->opcode << 8);
- WRITEUCTLDATA(byte);
-
- bytecnt = 0;
- while (incnt > 0) {
- byte = (txn->inbuf[bytecnt] << 8);
- WRITEUCTLDATA(byte);
- incnt--;
- bytecnt++;
- }
-
- /* Get the ack */
- READUCTLDATA(byte);
- dprintk(("ack was %x\n", (byte >> 8)));
-
- bytecnt = 0;
- while (outcnt > 0) {
- READUCTLDATA(byte);
- txn->outbuf[bytecnt] = (byte >> 8);
- dprintk(("set byte to %02x\n", byte));
- outcnt--;
- bytecnt++;
- }
-}
-
-static void uctrl_get_event_status(struct uctrl_driver *driver)
-{
- struct uctrl_txn txn;
- u8 outbits[2];
-
- txn.opcode = READ_EVENT_STATUS;
- txn.inbits = 0;
- txn.outbits = 2;
- txn.inbuf = NULL;
- txn.outbuf = outbits;
-
- uctrl_do_txn(driver, &txn);
-
- dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
- driver->status.event_status =
- ((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
- dprintk(("ev is %x\n", driver->status.event_status));
-}
-
-static void uctrl_get_external_status(struct uctrl_driver *driver)
-{
- struct uctrl_txn txn;
- u8 outbits[2];
- int i, v;
-
- txn.opcode = READ_EXTERNAL_STATUS;
- txn.inbits = 0;
- txn.outbits = 2;
- txn.inbuf = NULL;
- txn.outbuf = outbits;
-
- uctrl_do_txn(driver, &txn);
-
- dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
- driver->status.external_status =
- ((outbits[0] * 256) + (outbits[1]));
- dprintk(("ex is %x\n", driver->status.external_status));
- v = driver->status.external_status;
- for (i = 0; v != 0; i++, v >>= 1) {
- if (v & 1) {
- dprintk(("%s%s", " ", uctrl_extstatus[i]));
- }
- }
- dprintk(("\n"));
-
-}
-
-static int uctrl_probe(struct platform_device *op)
-{
- struct uctrl_driver *p;
- int err = -ENOMEM;
-
- p = kzalloc(sizeof(*p), GFP_KERNEL);
- if (!p) {
- printk(KERN_ERR "uctrl: Unable to allocate device struct.\n");
- goto out;
- }
-
- p->regs = of_ioremap(&op->resource[0], 0,
- resource_size(&op->resource[0]),
- "uctrl");
- if (!p->regs) {
- printk(KERN_ERR "uctrl: Unable to map registers.\n");
- goto out_free;
- }
-
- p->irq = op->archdata.irqs[0];
- err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p);
- if (err) {
- printk(KERN_ERR "uctrl: Unable to register irq.\n");
- goto out_iounmap;
- }
-
- err = misc_register(&uctrl_dev);
- if (err) {
- printk(KERN_ERR "uctrl: Unable to register misc device.\n");
- goto out_free_irq;
- }
-
- sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr);
- printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n",
- op->dev.of_node, p->regs, p->irq);
- uctrl_get_event_status(p);
- uctrl_get_external_status(p);
-
- dev_set_drvdata(&op->dev, p);
- global_driver = p;
-
-out:
- return err;
-
-out_free_irq:
- free_irq(p->irq, p);
-
-out_iounmap:
- of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
-
-out_free:
- kfree(p);
- goto out;
-}
-
-static void uctrl_remove(struct platform_device *op)
-{
- struct uctrl_driver *p = dev_get_drvdata(&op->dev);
-
- if (p) {
- misc_deregister(&uctrl_dev);
- free_irq(p->irq, p);
- of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0]));
- kfree(p);
- }
-}
-
-static const struct of_device_id uctrl_match[] = {
- {
- .name = "uctrl",
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, uctrl_match);
-
-static struct platform_driver uctrl_driver = {
- .driver = {
- .name = "uctrl",
- .of_match_table = uctrl_match,
- },
- .probe = uctrl_probe,
- .remove_new = uctrl_remove,
-};
-
-
-module_platform_driver(uctrl_driver);
-
-MODULE_LICENSE("GPL");
--
2.34.1
Hi Sam,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 84b76d05828a1909e20d0f66553b876b801f98c8]
url: https://github.com/intel-lab-lkp/linux/commits/Sam-Ravnborg-via-B4-Relay/sparc32-Update-defconfig-to-LEON-SMP/20240310-021717
base: 84b76d05828a1909e20d0f66553b876b801f98c8
patch link: https://lore.kernel.org/r/20240309-sunset-v2-14-f09912574d2c%40ravnborg.org
patch subject: [PATCH v2 14/28] sparc32: Drop unused mmu models
config: sparc-randconfig-r113-20240310 (https://download.01.org/0day-ci/archive/20240310/[email protected]/config)
compiler: sparc-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240310/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> arch/sparc/mm/srmmu.c:49:5: sparse: sparse: symbol 'vac_line_size' was not declared. Should it be static?
vim +/vac_line_size +49 arch/sparc/mm/srmmu.c
accf032cfa582e Sam Ravnborg 2012-05-19 46
^1da177e4c3f41 Linus Torvalds 2005-04-16 47 int vac_cache_size;
9d262d95114cf2 Guenter Roeck 2017-04-01 48 EXPORT_SYMBOL(vac_cache_size);
^1da177e4c3f41 Linus Torvalds 2005-04-16 @49 int vac_line_size;
^1da177e4c3f41 Linus Torvalds 2005-04-16 50
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi kernel test robot et al.
On Sun, Mar 10, 2024 at 06:37:53PM +0800, kernel test robot wrote:
> Hi Sam,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on 84b76d05828a1909e20d0f66553b876b801f98c8]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Sam-Ravnborg-via-B4-Relay/sparc32-Update-defconfig-to-LEON-SMP/20240310-021717
> base: 84b76d05828a1909e20d0f66553b876b801f98c8
> patch link: https://lore.kernel.org/r/20240309-sunset-v2-14-f09912574d2c%40ravnborg.org
> patch subject: [PATCH v2 14/28] sparc32: Drop unused mmu models
> config: sparc-randconfig-r113-20240310 (https://download.01.org/0day-ci/archive/20240310/[email protected]/config)
> compiler: sparc-linux-gcc (GCC) 13.2.0
> reproduce: (https://download.01.org/0day-ci/archive/20240310/[email protected]/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <[email protected]>
> | Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
>
> sparse warnings: (new ones prefixed by >>)
> >> arch/sparc/mm/srmmu.c:49:5: sparse: sparse: symbol 'vac_line_size' was not declared. Should it be static?
>
> vim +/vac_line_size +49 arch/sparc/mm/srmmu.c
>
> accf032cfa582e Sam Ravnborg 2012-05-19 46
> ^1da177e4c3f41 Linus Torvalds 2005-04-16 47 int vac_cache_size;
> 9d262d95114cf2 Guenter Roeck 2017-04-01 48 EXPORT_SYMBOL(vac_cache_size);
> ^1da177e4c3f41 Linus Torvalds 2005-04-16 @49 int vac_line_size;
> ^1da177e4c3f41 Linus Torvalds 2005-04-16 50
vac_line_size is no longer used and can be deleted.
vac_cache_size is never written to and can be deleted too.
vac_cache_size is used in shmparam_32.h like this:
#define SHMLBA (vac_cache_size ? vac_cache_size : PAGE_SIZE)
The same file has:
#define __ARCH_FORCE_SHMLBA 1
If I understand it right then when SHMLBA equals PAGE_SIZE then there is
no need to define __ARCH_FORCE_SHMLBA and sparc32 can use the asm-generic
variant of shmparam.h
I will do this change in v3.
Sam
On Sat, Mar 9, 2024, at 19:15, Sam Ravnborg via B4 Relay wrote:
> From: Sam Ravnborg <[email protected]>
>
> The p9100 driver is only relevant for the Sparcbook 3 machine,
> and with sun4m support removed this driver is no longer relevant.
>
> Signed-off-by: Sam Ravnborg <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Acked-by: Thomas Zimmermann <[email protected]>
> Cc: "David S. Miller" <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Andreas Larsson <[email protected]>
> Cc: Helge Deller <[email protected]>
> ---
> drivers/video/fbdev/Kconfig | 8 -
> drivers/video/fbdev/Makefile | 1 -
> drivers/video/fbdev/p9100.c | 372 -------------------------------------------
> 3 files changed, 381 deletions(-)
I tried to figure out if there are other drivers in the same
category and found the list at
https://everything2.com/title/Sun+graphics+cards
As far as I can tell, the only SBUS graphics that were
shipped on sparc64 are FB_FFB and FB_CG6, so we could
go further and remove BW2, CG3, TCX, CG14 and LEO as
well.
No need to change anything here for the moment, dropping
p9100 is already a step in the right direction.
Arnd
Hi Arnd.
On Mon, Mar 11, 2024 at 03:05:25PM +0100, Arnd Bergmann wrote:
> On Sat, Mar 9, 2024, at 19:15, Sam Ravnborg via B4 Relay wrote:
> > From: Sam Ravnborg <[email protected]>
> >
> > The p9100 driver is only relevant for the Sparcbook 3 machine,
> > and with sun4m support removed this driver is no longer relevant.
> >
> > Signed-off-by: Sam Ravnborg <[email protected]>
> > Acked-by: Arnd Bergmann <[email protected]>
> > Acked-by: Thomas Zimmermann <[email protected]>
> > Cc: "David S. Miller" <[email protected]>
> > Cc: Arnd Bergmann <[email protected]>
> > Cc: Andreas Larsson <[email protected]>
> > Cc: Helge Deller <[email protected]>
> > ---
> > drivers/video/fbdev/Kconfig | 8 -
> > drivers/video/fbdev/Makefile | 1 -
> > drivers/video/fbdev/p9100.c | 372 -------------------------------------------
> > 3 files changed, 381 deletions(-)
>
> I tried to figure out if there are other drivers in the same
> category and found the list at
> https://everything2.com/title/Sun+graphics+cards
>
> As far as I can tell, the only SBUS graphics that were
> shipped on sparc64 are FB_FFB and FB_CG6, so we could
> go further and remove BW2, CG3, TCX, CG14 and LEO as
> well.
Looks like you are right, so we can drop more - good.
As you already wrote - let's get the current patch set processed first.
I did a quick hack on top of my current sparc32 patches.
This is nice reduction of ~2700 lines and 5 fbdev drivers less to care
about.
Sam
Drop mmu models not used by LEON, including their header files.
This includes removal of unused includes in various files to fix the
build.
With this change SHMLBA is always PAGE_SIZE so use the
asm-generic variant of shmparam.h for sparc32.
__ARCH_FORCE_SHMLBA is then no longer defined, but
this should be OK if my analysis is correct.
Signed-off-by: Sam Ravnborg <[email protected]>
Cc: "David S. Miller" <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Andreas Larsson <[email protected]>
---
Posted v3 here to avoid resending the whole series.
In v3 the asm-generic shmparam.h are introduced and a few
unused variables (reported by kernel test robot) was dropped.
Sam
arch/sparc/include/asm/mxcc.h | 138 -----
arch/sparc/include/asm/ross.h | 192 -------
arch/sparc/include/asm/shmparam.h | 2 +-
arch/sparc/include/asm/shmparam_32.h | 10 -
arch/sparc/include/asm/swift.h | 107 ----
arch/sparc/include/asm/tsunami.h | 65 ---
arch/sparc/include/asm/turbosparc.h | 126 -----
arch/sparc/include/asm/viking.h | 255 ---------
arch/sparc/kernel/entry.S | 1 -
arch/sparc/mm/Makefile | 1 -
arch/sparc/mm/hypersparc.S | 414 --------------
arch/sparc/mm/io-unit.c | 1 -
arch/sparc/mm/iommu.c | 31 +-
arch/sparc/mm/mm_32.h | 1 -
arch/sparc/mm/srmmu.c | 780 +--------------------------
arch/sparc/mm/swift.S | 256 ---------
arch/sparc/mm/tsunami.S | 132 -----
arch/sparc/mm/viking.S | 284 ----------
18 files changed, 22 insertions(+), 2774 deletions(-)
delete mode 100644 arch/sparc/include/asm/mxcc.h
delete mode 100644 arch/sparc/include/asm/ross.h
delete mode 100644 arch/sparc/include/asm/shmparam_32.h
delete mode 100644 arch/sparc/include/asm/swift.h
delete mode 100644 arch/sparc/include/asm/tsunami.h
delete mode 100644 arch/sparc/include/asm/turbosparc.h
delete mode 100644 arch/sparc/include/asm/viking.h
delete mode 100644 arch/sparc/mm/hypersparc.S
delete mode 100644 arch/sparc/mm/swift.S
delete mode 100644 arch/sparc/mm/tsunami.S
delete mode 100644 arch/sparc/mm/viking.S
diff --git a/arch/sparc/include/asm/mxcc.h b/arch/sparc/include/asm/mxcc.h
deleted file mode 100644
index 3a2561bea4dd..000000000000
--- a/arch/sparc/include/asm/mxcc.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * mxcc.h: Definitions of the Viking MXCC registers
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_MXCC_H
-#define _SPARC_MXCC_H
-
-/* These registers are accessed through ASI 0x2. */
-#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
-#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
-#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
-#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
-#define MXCC_STEST 0x1C00804 /* Internal self-test */
-#define MXCC_CREG 0x1C00A04 /* Control register */
-#define MXCC_SREG 0x1C00B00 /* Status register */
-#define MXCC_RREG 0x1C00C04 /* Reset register */
-#define MXCC_EREG 0x1C00E00 /* Error code register */
-#define MXCC_PREG 0x1C00F04 /* Address port register */
-
-/* Some MXCC constants. */
-#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
-
-/* The MXCC Control Register:
- *
- * ----------------------------------------------------------------------
- * | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
- * ----------------------------------------------------------------------
- * 31 10 9 8-6 5 4 3 2 1-0
- *
- * RRC: Controls what you read from MXCC_RMCOUNT reg.
- * 0=Misses 1=References
- * PRE: Prefetch enable
- * MCE: Multiple Command Enable
- * PARE: Parity enable
- * ECE: External cache enable
- */
-
-#define MXCC_CTL_RRC 0x00000200
-#define MXCC_CTL_PRE 0x00000020
-#define MXCC_CTL_MCE 0x00000010
-#define MXCC_CTL_PARE 0x00000008
-#define MXCC_CTL_ECE 0x00000004
-
-/* The MXCC Error Register:
- *
- * --------------------------------------------------------
- * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
- * --------------------------------------------------------
- * 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
- *
- * ME: Multiple Errors have occurred
- * CE: Cache consistency Error
- * PEW: Parity Error during a Write operation
- * PEE: Parity Error involving the External cache
- * ASE: ASynchronous Error
- * EIV: This register is toast
- * MOPC: MXCC Operation Code for instance causing error
- * ECODE: The Error CODE
- * PRIV: A privileged mode error? 0=no 1=yes
- * HPADDR: High PhysicalADDRess bits (35-32)
- */
-
-#define MXCC_ERR_ME 0x80000000
-#define MXCC_ERR_CE 0x20000000
-#define MXCC_ERR_PEW 0x10000000
-#define MXCC_ERR_PEE 0x08000000
-#define MXCC_ERR_ASE 0x04000000
-#define MXCC_ERR_EIV 0x02000000
-#define MXCC_ERR_MOPC 0x01FF8000
-#define MXCC_ERR_ECODE 0x00007F80
-#define MXCC_ERR_PRIV 0x00000040
-#define MXCC_ERR_HPADDR 0x0000000f
-
-/* The MXCC Port register:
- *
- * -----------------------------------------------------
- * | | MID | |
- * -----------------------------------------------------
- * 31 21 20-18 17 0
- *
- * MID: The moduleID of the cpu your read this from.
- */
-
-#ifndef __ASSEMBLY__
-
-static inline void mxcc_set_stream_src(unsigned long *paddr)
-{
- unsigned long data0 = paddr[0];
- unsigned long data1 = paddr[1];
-
- __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (data0), "r" (data1),
- "r" (MXCC_SRCSTREAM),
- "i" (ASI_M_MXCC) : "g2", "g3");
-}
-
-static inline void mxcc_set_stream_dst(unsigned long *paddr)
-{
- unsigned long data0 = paddr[0];
- unsigned long data1 = paddr[1];
-
- __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
- "or %%g0, %1, %%g3\n\t"
- "stda %%g2, [%2] %3\n\t" : :
- "r" (data0), "r" (data1),
- "r" (MXCC_DESSTREAM),
- "i" (ASI_M_MXCC) : "g2", "g3");
-}
-
-static inline unsigned long mxcc_get_creg(void)
-{
- unsigned long mxcc_control;
-
- __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
- "set 0xffffffff, %%g3\n\t"
- "stda %%g2, [%1] %2\n\t"
- "lda [%3] %2, %0\n\t" :
- "=r" (mxcc_control) :
- "r" (MXCC_EREG), "i" (ASI_M_MXCC),
- "r" (MXCC_CREG) : "g2", "g3");
- return mxcc_control;
-}
-
-static inline void mxcc_set_creg(unsigned long mxcc_control)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
- "r" (mxcc_control), "r" (MXCC_CREG),
- "i" (ASI_M_MXCC));
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_MXCC_H) */
diff --git a/arch/sparc/include/asm/ross.h b/arch/sparc/include/asm/ross.h
deleted file mode 100644
index 79a54d66a2c0..000000000000
--- a/arch/sparc/include/asm/ross.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * ross.h: Ross module specific definitions and defines.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_ROSS_H
-#define _SPARC_ROSS_H
-
-#include <asm/asi.h>
-#include <asm/page.h>
-
-/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
- * field has '1111'.
- */
-
-/* The MMU control register fields on the HyperSparc.
- *
- * -----------------------------------------------------------------
- * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
- * -----------------------------------------------------------------
- * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
- *
- * Phew, lots of fields there ;-)
- *
- * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
- * SE: Snoop Enable, turns on bus snooping for cache activity if one.
- * WBE: Write Buffer Enable, one turns it on.
- * MID: The ModuleID of the chip for MBus transactions.
- * BM: Boot-Mode. One indicates the MMU is in boot mode.
- * C: Indicates whether accesses are cachable while the MMU is
- * disabled.
- * CS: Cache Size -- 0 = 128k, 1 = 256k
- * MR: Memory Reflection, one indicates that the memory bus connected
- * to the MBus supports memory reflection.
- * CM: Cache Mode -- 0 = write-through, 1 = copy-back
- * CE: Cache Enable -- 0 = no caching, 1 = cache is on
- * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
- * 1 = faults from supervisor mode do not generate traps
- * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
- */
-
-#define HYPERSPARC_CWENABLE 0x00200000
-#define HYPERSPARC_SBENABLE 0x00100000
-#define HYPERSPARC_WBENABLE 0x00080000
-#define HYPERSPARC_MIDMASK 0x00078000
-#define HYPERSPARC_BMODE 0x00004000
-#define HYPERSPARC_ACENABLE 0x00002000
-#define HYPERSPARC_CSIZE 0x00001000
-#define HYPERSPARC_MRFLCT 0x00000800
-#define HYPERSPARC_CMODE 0x00000400
-#define HYPERSPARC_CENABLE 0x00000100
-#define HYPERSPARC_NFAULT 0x00000002
-#define HYPERSPARC_MENABLE 0x00000001
-
-
-/* The ICCR instruction cache register on the HyperSparc.
- *
- * -----------------------------------------------
- * | | FTD | ICE |
- * -----------------------------------------------
- * 31 1 0
- *
- * This register is accessed using the V8 'wrasr' and 'rdasr'
- * opcodes, since not all assemblers understand them and those
- * that do use different semantics I will just hard code the
- * instruction with a '.word' statement.
- *
- * FTD: If set to one flush instructions executed during an
- * instruction cache hit occurs, the corresponding line
- * for said cache-hit is invalidated. If FTD is zero,
- * an unimplemented 'flush' trap will occur when any
- * flush is executed by the processor.
- *
- * ICE: If set to one, the instruction cache is enabled. If
- * zero, the cache will not be used for instruction fetches.
- *
- * All other bits are read as zeros, and writes to them have no
- * effect.
- *
- * Wheee, not many assemblers understand the %iccr register nor
- * the generic asr r/w instructions.
- *
- * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
- *
- * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
- *
- * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
- *
- * 0x b f 8 0 6 0 0 0 ! 0xbf806000
- *
- */
-
-#define HYPERSPARC_ICCR_FTD 0x00000002
-#define HYPERSPARC_ICCR_ICE 0x00000001
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned int get_ross_icr(void)
-{
- unsigned int icreg;
-
- __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
- "mov %%g1, %0\n\t"
- : "=r" (icreg)
- : /* no inputs */
- : "g1", "memory");
-
- return icreg;
-}
-
-static inline void put_ross_icr(unsigned int icreg)
-{
- __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
- ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : /* no outputs */
- : "r" (icreg)
- : "g1", "memory");
-
- return;
-}
-
-/* HyperSparc specific cache flushing. */
-
-/* This is for the on-chip instruction cache. */
-static inline void hyper_flush_whole_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_FLUSH_IWHOLE)
- : "memory");
- return;
-}
-
-extern int vac_cache_size;
-extern int vac_line_size;
-
-static inline void hyper_clear_all_tags(void)
-{
- unsigned long addr;
-
- for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void hyper_flush_unconditional_combined(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_CTX)
- : "memory");
-}
-
-static inline void hyper_flush_cache_user(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_USER)
- : "memory");
-}
-
-static inline void hyper_flush_cache_page(unsigned long page)
-{
- unsigned long end;
-
- page &= PAGE_MASK;
- end = page + PAGE_SIZE;
- while (page < end) {
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (page), "i" (ASI_M_FLUSH_PAGE)
- : "memory");
- page += vac_line_size;
- }
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(_SPARC_ROSS_H) */
diff --git a/arch/sparc/include/asm/shmparam.h b/arch/sparc/include/asm/shmparam.h
index 951a4525fa4b..9f55efb80b92 100644
--- a/arch/sparc/include/asm/shmparam.h
+++ b/arch/sparc/include/asm/shmparam.h
@@ -4,6 +4,6 @@
#if defined(__sparc__) && defined(__arch64__)
#include <asm/shmparam_64.h>
#else
-#include <asm/shmparam_32.h>
+#include <asm-generic/shmparam.h>
#endif
#endif
diff --git a/arch/sparc/include/asm/shmparam_32.h b/arch/sparc/include/asm/shmparam_32.h
deleted file mode 100644
index 9767a8b30242..000000000000
--- a/arch/sparc/include/asm/shmparam_32.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASMSPARC_SHMPARAM_H
-#define _ASMSPARC_SHMPARAM_H
-
-#define __ARCH_FORCE_SHMLBA 1
-
-extern int vac_cache_size;
-#define SHMLBA (vac_cache_size ? vac_cache_size : PAGE_SIZE)
-
-#endif /* _ASMSPARC_SHMPARAM_H */
diff --git a/arch/sparc/include/asm/swift.h b/arch/sparc/include/asm/swift.h
deleted file mode 100644
index 96f6526b964e..000000000000
--- a/arch/sparc/include/asm/swift.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* swift.h: Specific definitions for the _broken_ Swift SRMMU
- * MMU module.
- *
- * Copyright (C) 1996 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_SWIFT_H
-#define _SPARC_SWIFT_H
-
-/* Swift is so brain damaged, here is the mmu control register. */
-#define SWIFT_ST 0x00800000 /* SW tablewalk enable */
-#define SWIFT_WP 0x00400000 /* Watchpoint enable */
-
-/* Branch folding (buggy, disable on production systems!) */
-#define SWIFT_BF 0x00200000
-#define SWIFT_PMC 0x00180000 /* Page mode control */
-#define SWIFT_PE 0x00040000 /* Parity enable */
-#define SWIFT_PC 0x00020000 /* Parity control */
-#define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
-#define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
-#define SWIFT_BM 0x00004000 /* Boot mode */
-#define SWIFT_RC 0x00003c00 /* DRAM refresh control */
-#define SWIFT_IE 0x00000200 /* Instruction cache enable */
-#define SWIFT_DE 0x00000100 /* Data cache enable */
-#define SWIFT_SA 0x00000080 /* Store Allocate */
-#define SWIFT_NF 0x00000002 /* No fault mode */
-#define SWIFT_EN 0x00000001 /* MMU enable */
-
-/* Bits [13:5] select one of 512 instruction cache tags */
-static inline void swift_inv_insn_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_TXTC_TAG)
- : "memory");
-}
-
-/* Bits [12:4] select one of 512 data cache tags */
-static inline void swift_inv_data_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void swift_flush_dcache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x2000; addr += 0x10)
- swift_inv_data_tag(addr);
-}
-
-static inline void swift_flush_icache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- swift_inv_insn_tag(addr);
-}
-
-static inline void swift_idflash_clear(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x2000; addr += 0x10) {
- swift_inv_insn_tag(addr<<1);
- swift_inv_data_tag(addr);
- }
-}
-
-/* Swift is so broken, it isn't even safe to use the following. */
-static inline void swift_flush_page(unsigned long page)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (page), "i" (ASI_M_FLUSH_PAGE)
- : "memory");
-}
-
-static inline void swift_flush_segment(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_SEG)
- : "memory");
-}
-
-static inline void swift_flush_region(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_FLUSH_REGION)
- : "memory");
-}
-
-static inline void swift_flush_context(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_FLUSH_CTX)
- : "memory");
-}
-
-#endif /* !(_SPARC_SWIFT_H) */
diff --git a/arch/sparc/include/asm/tsunami.h b/arch/sparc/include/asm/tsunami.h
deleted file mode 100644
index acaf014eff46..000000000000
--- a/arch/sparc/include/asm/tsunami.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-
-#ifndef _SPARC_TSUNAMI_H
-#define _SPARC_TSUNAMI_H
-
-#include <asm/asi.h>
-
-/* The MMU control register on the Tsunami:
- *
- * -----------------------------------------------------------------------
- * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
- * -----------------------------------------------------------------------
- * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
- *
- * SW: Enable Software Table Walks 0=off 1=on
- * AV: Address View bit
- * DV: Data View bit
- * MV: Memory View bit
- * PC: Parity Control
- * ITD: ITBR disable
- * ALC: Alternate Cacheable
- * PE: Parity Enable 0=off 1=on
- * RC: Refresh Control
- * IE: Instruction cache Enable 0=off 1=on
- * DE: Data cache Enable 0=off 1=on
- * NF: No Fault, same as all other SRMMUs
- * ME: MMU Enable, same as all other SRMMUs
- */
-
-#define TSUNAMI_SW 0x00800000
-#define TSUNAMI_AV 0x00400000
-#define TSUNAMI_DV 0x00200000
-#define TSUNAMI_MV 0x00100000
-#define TSUNAMI_PC 0x00020000
-#define TSUNAMI_ITD 0x00010000
-#define TSUNAMI_ALC 0x00008000
-#define TSUNAMI_PE 0x00001000
-#define TSUNAMI_RCMASK 0x00000C00
-#define TSUNAMI_IENAB 0x00000200
-#define TSUNAMI_DENAB 0x00000100
-#define TSUNAMI_NF 0x00000002
-#define TSUNAMI_ME 0x00000001
-
-static inline void tsunami_flush_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void tsunami_flush_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-#endif /* !(_SPARC_TSUNAMI_H) */
diff --git a/arch/sparc/include/asm/turbosparc.h b/arch/sparc/include/asm/turbosparc.h
deleted file mode 100644
index 23df777f9cea..000000000000
--- a/arch/sparc/include/asm/turbosparc.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * turbosparc.h: Defines specific to the TurboSparc module.
- * This is SRMMU stuff.
- *
- * Copyright (C) 1997 Jakub Jelinek ([email protected])
- */
-#ifndef _SPARC_TURBOSPARC_H
-#define _SPARC_TURBOSPARC_H
-
-#include <asm/asi.h>
-#include <asm/pgtsrmmu.h>
-
-/* Bits in the SRMMU control register for TurboSparc modules.
- *
- * -------------------------------------------------------------------
- * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
- * -------------------------------------------------------------------
- * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
- *
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- *
- * This indicates whether the TurboSparc is in boot-mode or not.
- *
- * IC: Instruction Cache -- 0 = off, 1 = on
- * DC: Data Cache -- 0 = off, 1 = 0n
- *
- * These bits enable the on-cpu TurboSparc split I/D caches.
- *
- * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
- * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
- * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
- *
- */
-
-#define TURBOSPARC_MMUENABLE 0x00000001
-#define TURBOSPARC_NOFAULT 0x00000002
-#define TURBOSPARC_ICSNOOP 0x00000004
-#define TURBOSPARC_PSO 0x00000080
-#define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
-#define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
-#define TURBOSPARC_BMODE 0x00004000
-#define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
-#define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
-
-/* Bits in the CPU configuration register for TurboSparc modules.
- *
- * -------------------------------------------------------
- * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
- * -------------------------------------------------------
- * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
- *
- */
-
-#define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
-#define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
-#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
-#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
-
-#ifndef __ASSEMBLY__
-
-/* Bits [13:5] select one of 512 instruction cache tags */
-static inline void turbosparc_inv_insn_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_TXTC_TAG)
- : "memory");
-}
-
-/* Bits [13:5] select one of 512 data cache tags */
-static inline void turbosparc_inv_data_tag(unsigned long addr)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (addr), "i" (ASI_M_DATAC_TAG)
- : "memory");
-}
-
-static inline void turbosparc_flush_icache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- turbosparc_inv_insn_tag(addr);
-}
-
-static inline void turbosparc_flush_dcache(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20)
- turbosparc_inv_data_tag(addr);
-}
-
-static inline void turbosparc_idflash_clear(void)
-{
- unsigned long addr;
-
- for (addr = 0; addr < 0x4000; addr += 0x20) {
- turbosparc_inv_insn_tag(addr);
- turbosparc_inv_data_tag(addr);
- }
-}
-
-static inline void turbosparc_set_ccreg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t"
- : /* no outputs */
- : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
- : "memory");
-}
-
-static inline unsigned long turbosparc_get_ccreg(void)
-{
- unsigned long regval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (regval)
- : "r" (0x600), "i" (ASI_M_MMUREGS));
- return regval;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_TURBOSPARC_H) */
diff --git a/arch/sparc/include/asm/viking.h b/arch/sparc/include/asm/viking.h
deleted file mode 100644
index 08ffc605035f..000000000000
--- a/arch/sparc/include/asm/viking.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * viking.h: Defines specific to the GNU/Viking MBUS module.
- * This is SRMMU stuff.
- *
- * Copyright (C) 1995 David S. Miller ([email protected])
- */
-#ifndef _SPARC_VIKING_H
-#define _SPARC_VIKING_H
-
-#include <asm/asi.h>
-#include <asm/mxcc.h>
-#include <asm/pgtable.h>
-#include <asm/pgtsrmmu.h>
-
-/* Bits in the SRMMU control register for GNU/Viking modules.
- *
- * -----------------------------------------------------------
- * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
- * -----------------------------------------------------------
- * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
- *
- * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
- * 1 = Twalks are cacheable in E-cache
- *
- * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
- * and never caches them internally (or so states the docs). Therefore
- * for machines lacking an E-cache (ie. in MBUS mode) this bit must
- * remain cleared.
- *
- * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
- * 1 = Passthru physical accesses cacheable
- *
- * This indicates whether accesses are cacheable when no cachable bit
- * is present in the pte when the processor is in boot-mode or the
- * access does not need pte's for translation (ie. pass-thru ASI's).
- * "Cachable" is only referring to E-cache (if present) and not the
- * on chip split I/D caches of the GNU/Viking.
- *
- * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
- *
- * This enables snooping on the GNU/Viking bus. This must be on
- * for the hardware cache consistency mechanisms of the GNU/Viking
- * to work at all. On non-mxcc GNU/Viking modules the split I/D
- * caches will snoop regardless of whether they are enabled, this
- * takes care of the case where the I or D or both caches are turned
- * off yet still contain valid data. Note also that this bit does
- * not affect GNU/Viking store-buffer snoops, those happen if the
- * store-buffer is enabled no matter what.
- *
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- *
- * This indicates whether the GNU/Viking is in boot-mode or not,
- * if it is then all instruction fetch physical addresses are
- * computed as 0xff0000000 + low 28 bits of requested address.
- * GNU/Viking boot-mode does not affect data accesses. Also,
- * in boot mode instruction accesses bypass the split on chip I/D
- * caches, they may be cached by the GNU/MXCC if present and enabled.
- *
- * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
- *
- * This indicated the GNU/Viking configuration present. If in
- * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
- * not then the GNU/Viking is on a module VBUS connected directly
- * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
- * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
- *
- * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
- *
- * The GNU/Viking store buffer allows the chip to continue execution
- * after a store even if the data cannot be placed in one of the
- * caches during that cycle. If disabled, all stores operations
- * occur synchronously.
- *
- * IC: Instruction Cache -- 0 = off, 1 = on
- * DC: Data Cache -- 0 = off, 1 = 0n
- *
- * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
- * as mentioned above, these caches will snoop the bus in GNU/MBUS
- * configurations even when disabled to avoid data corruption.
- *
- * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
- * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
- *
- */
-
-#define VIKING_MMUENABLE 0x00000001
-#define VIKING_NOFAULT 0x00000002
-#define VIKING_PSO 0x00000080
-#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
-#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
-#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
-#define VIKING_MMODE 0x00000800 /* MBUS mode */
-#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
-#define VIKING_BMODE 0x00002000
-#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
-#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
-#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
-#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
-
-/*
- * GNU/Viking Breakpoint Action Register fields.
- */
-#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
-
-/*
- * GNU/Viking Cache Tags.
- */
-#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
-#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
-#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
-
-#ifndef __ASSEMBLY__
-
-static inline void viking_flush_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_flush_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
- : /* no outputs */
- : "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_unlock_icache(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_unlock_dcache(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
- : /* no outputs */
- : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
- : "memory");
-}
-
-static inline void viking_set_bpreg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
- : /* no outputs */
- : "r" (regval), "i" (ASI_M_ACTION)
- : "memory");
-}
-
-static inline unsigned long viking_get_bpreg(void)
-{
- unsigned long regval;
-
- __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
- : "=r" (regval)
- : "i" (ASI_M_ACTION));
- return regval;
-}
-
-static inline void viking_get_dcache_ptag(int set, int block,
- unsigned long *data)
-{
- unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
- 0x80000000;
- unsigned long info, page;
-
- __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
- "or %%g0, %%g2, %0\n\t"
- "or %%g0, %%g3, %1\n\t"
- : "=r" (info), "=r" (page)
- : "r" (ptag), "i" (ASI_M_DATAC_TAG)
- : "g2", "g3");
- data[0] = info;
- data[1] = page;
-}
-
-static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
- unsigned long *mxcc_cregp)
-{
- unsigned long mreg = *mregp;
- unsigned long mxcc_creg = *mxcc_cregp;
-
- mreg &= ~(VIKING_PCENABLE);
- mxcc_creg &= ~(MXCC_CTL_PARE);
-
- __asm__ __volatile__ ("set 1f, %%g2\n\t"
- "andcc %%g2, 4, %%g0\n\t"
- "bne 2f\n\t"
- " nop\n"
- "1:\n\t"
- "sta %0, [%%g0] %3\n\t"
- "sta %1, [%2] %4\n\t"
- "b 1f\n\t"
- " nop\n\t"
- "nop\n"
- "2:\n\t"
- "sta %0, [%%g0] %3\n\t"
- "sta %1, [%2] %4\n"
- "1:\n\t"
- : /* no output */
- : "r" (mreg), "r" (mxcc_creg),
- "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
- "i" (ASI_M_MXCC)
- : "g2", "memory", "cc");
- *mregp = mreg;
- *mxcc_cregp = mxcc_creg;
-}
-
-static inline unsigned long viking_hwprobe(unsigned long vaddr)
-{
- unsigned long val;
-
- vaddr &= PAGE_MASK;
- /* Probe all MMU entries. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
- if (!val)
- return 0;
-
- /* Probe region. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
- if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
- vaddr &= ~PGDIR_MASK;
- vaddr >>= PAGE_SHIFT;
- return val | (vaddr << 8);
- }
-
- /* Probe segment. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
- if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
- vaddr &= ~PMD_MASK;
- vaddr >>= PAGE_SHIFT;
- return val | (vaddr << 8);
- }
-
- /* Probe page. */
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- : "=r" (val)
- : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
- return val;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* !(_SPARC_VIKING_H) */
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 13011969e7eb..0f2417ee3f95 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -25,7 +25,6 @@
#include <asm/winmacro.h>
#include <asm/signal.h>
#include <asm/obio.h>
-#include <asm/mxcc.h>
#include <asm/thread_info.h>
#include <asm/param.h>
#include <asm/unistd.h>
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index 809d993f6d88..7b3ff6dd382e 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -9,7 +9,6 @@ obj-y += fault_$(BITS).o
obj-y += init_$(BITS).o
obj-$(CONFIG_SPARC32) += srmmu.o iommu.o io-unit.o
obj-$(CONFIG_SPARC32) += srmmu_access.o
-obj-$(CONFIG_SPARC32) += hypersparc.o viking.o tsunami.o swift.o
obj-$(CONFIG_SPARC32) += leon_mm.o
# Only used by sparc64
diff --git a/arch/sparc/mm/hypersparc.S b/arch/sparc/mm/hypersparc.S
deleted file mode 100644
index 6c2521e85a42..000000000000
--- a/arch/sparc/mm/hypersparc.S
+++ /dev/null
@@ -1,414 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * hypersparc.S: High speed Hypersparc mmu/cache operations.
- *
- * Copyright (C) 1997 David S. Miller ([email protected])
- */
-
-#include <asm/ptrace.h>
-#include <asm/psr.h>
-#include <asm/asm-offsets.h>
-#include <asm/asi.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pgtsrmmu.h>
-#include <linux/init.h>
-
- .text
- .align 4
-
- .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
- .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
- .globl hypersparc_flush_page_to_ram
- .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
- .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
- .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
-
-hypersparc_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
- sethi %hi(vac_cache_size), %g4
- ld [%g4 + %lo(vac_cache_size)], %g5
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %g2
-1:
- subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
- bne 1b
- sta %g0, [%g5] ASI_M_FLUSH_CTX
- retl
- sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
-
- /* We expand the window flush to get maximum performance. */
-hypersparc_flush_cache_mm:
-#ifndef CONFIG_SMP
- ld [%o0 + AOFF_mm_context], %g1
- cmp %g1, -1
- be hypersparc_flush_cache_mm_out
-#endif
- WINDOW_FLUSH(%g4, %g5)
-
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o1
- sethi %hi(vac_cache_size), %g2
- ld [%g2 + %lo(vac_cache_size)], %o0
- add %o1, %o1, %g1
- add %o1, %g1, %g2
- add %o1, %g2, %g3
- add %o1, %g3, %g4
- add %o1, %g4, %g5
- add %o1, %g5, %o4
- add %o1, %o4, %o5
-
- /* BLAMMO! */
-1:
- subcc %o0, %o5, %o0 ! hyper_flush_cache_user
- sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
- sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
- bne 1b
- sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
-hypersparc_flush_cache_mm_out:
- retl
- nop
-
- /* The things we do for performance... */
-hypersparc_flush_cache_range:
- ld [%o0 + VMA_VM_MM], %o0
-#ifndef CONFIG_SMP
- ld [%o0 + AOFF_mm_context], %g1
- cmp %g1, -1
- be hypersparc_flush_cache_range_out
-#endif
- WINDOW_FLUSH(%g4, %g5)
-
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o4
- sethi %hi(vac_cache_size), %g2
- ld [%g2 + %lo(vac_cache_size)], %o3
-
- /* Here comes the fun part... */
- add %o2, (PAGE_SIZE - 1), %o2
- andn %o1, (PAGE_SIZE - 1), %o1
- add %o4, %o4, %o5
- andn %o2, (PAGE_SIZE - 1), %o2
- add %o4, %o5, %g1
- sub %o2, %o1, %g4
- add %o4, %g1, %g2
- sll %o3, 2, %g5
- add %o4, %g2, %g3
- cmp %g4, %g5
- add %o4, %g3, %g4
- blu 0f
- add %o4, %g4, %g5
- add %o4, %g5, %g7
-
- /* Flush entire user space, believe it or not this is quicker
- * than page at a time flushings for range > (cache_size<<2).
- */
-1:
- subcc %o3, %g7, %o3
- sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
- sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
- bne 1b
- sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
- retl
- nop
-
- /* Below our threshold, flush one page at a time. */
-0:
- ld [%o0 + AOFF_mm_context], %o0
- mov SRMMU_CTX_REG, %g7
- lda [%g7] ASI_M_MMUREGS, %o3
- sta %o0, [%g7] ASI_M_MMUREGS
- add %o2, -PAGE_SIZE, %o0
-1:
- or %o0, 0x400, %g7
- lda [%g7] ASI_M_FLUSH_PROBE, %g7
- orcc %g7, 0, %g0
- be,a 3f
- mov %o0, %o2
- add %o4, %g5, %g7
-2:
- sub %o2, %g7, %o2
- sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
- sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
- andcc %o2, 0xffc, %g0
- sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
- bne 2b
- sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
-3:
- cmp %o2, %o1
- bne 1b
- add %o2, -PAGE_SIZE, %o0
- mov SRMMU_FAULT_STATUS, %g5
- lda [%g5] ASI_M_MMUREGS, %g0
- mov SRMMU_CTX_REG, %g7
- sta %o3, [%g7] ASI_M_MMUREGS
-hypersparc_flush_cache_range_out:
- retl
- nop
-
- /* HyperSparc requires a valid mapping where we are about to flush
- * in order to check for a physical tag match during the flush.
- */
- /* Verified, my ass... */
-hypersparc_flush_cache_page:
- ld [%o0 + VMA_VM_MM], %o0
- ld [%o0 + AOFF_mm_context], %g2
-#ifndef CONFIG_SMP
- cmp %g2, -1
- be hypersparc_flush_cache_page_out
-#endif
- WINDOW_FLUSH(%g4, %g5)
-
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o4
- mov SRMMU_CTX_REG, %o3
- andn %o1, (PAGE_SIZE - 1), %o1
- lda [%o3] ASI_M_MMUREGS, %o2
- sta %g2, [%o3] ASI_M_MMUREGS
- or %o1, 0x400, %o5
- lda [%o5] ASI_M_FLUSH_PROBE, %g1
- orcc %g0, %g1, %g0
- be 2f
- add %o4, %o4, %o5
- sub %o1, -PAGE_SIZE, %o1
- add %o4, %o5, %g1
- add %o4, %g1, %g2
- add %o4, %g2, %g3
- add %o4, %g3, %g4
- add %o4, %g4, %g5
- add %o4, %g5, %g7
-
- /* BLAMMO! */
-1:
- sub %o1, %g7, %o1
- sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
- andcc %o1, 0xffc, %g0
- sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
- bne 1b
- sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
-2:
- mov SRMMU_FAULT_STATUS, %g7
- mov SRMMU_CTX_REG, %g4
- lda [%g7] ASI_M_MMUREGS, %g0
- sta %o2, [%g4] ASI_M_MMUREGS
-hypersparc_flush_cache_page_out:
- retl
- nop
-
-hypersparc_flush_sig_insns:
- flush %o1
- retl
- flush %o1 + 4
-
- /* HyperSparc is copy-back. */
-hypersparc_flush_page_to_ram:
- sethi %hi(vac_line_size), %g1
- ld [%g1 + %lo(vac_line_size)], %o4
- andn %o0, (PAGE_SIZE - 1), %o0
- add %o4, %o4, %o5
- or %o0, 0x400, %g7
- lda [%g7] ASI_M_FLUSH_PROBE, %g5
- add %o4, %o5, %g1
- orcc %g5, 0, %g0
- be 2f
- add %o4, %g1, %g2
- add %o4, %g2, %g3
- sub %o0, -PAGE_SIZE, %o0
- add %o4, %g3, %g4
- add %o4, %g4, %g5
- add %o4, %g5, %g7
-
- /* BLAMMO! */
-1:
- sub %o0, %g7, %o0
- sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
- sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
- andcc %o0, 0xffc, %g0
- sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
- bne 1b
- sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
-2:
- mov SRMMU_FAULT_STATUS, %g1
- retl
- lda [%g1] ASI_M_MMUREGS, %g0
-
- /* HyperSparc is IO cache coherent. */
-hypersparc_flush_page_for_dma:
- retl
- nop
-
- /* It was noted that at boot time a TLB flush all in a delay slot
- * can deliver an illegal instruction to the processor if the timing
- * is just right...
- */
-hypersparc_flush_tlb_all:
- mov 0x400, %g1
- sta %g0, [%g1] ASI_M_FLUSH_PROBE
- retl
- nop
-
-hypersparc_flush_tlb_mm:
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o1
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o1, -1
- be hypersparc_flush_tlb_mm_out
-#endif
- mov 0x300, %g2
- sta %o1, [%g1] ASI_M_MMUREGS
- sta %g0, [%g2] ASI_M_FLUSH_PROBE
-hypersparc_flush_tlb_mm_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
-hypersparc_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be hypersparc_flush_tlb_range_out
-#endif
- sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
- sta %o3, [%g1] ASI_M_MMUREGS
- and %o1, %o4, %o1
- add %o1, 0x200, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-1:
- sub %o1, %o4, %o1
- cmp %o1, %o2
- blu,a 1b
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-hypersparc_flush_tlb_range_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
-hypersparc_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- andn %o1, (PAGE_SIZE - 1), %o1
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be hypersparc_flush_tlb_page_out
-#endif
- lda [%g1] ASI_M_MMUREGS, %g5
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-hypersparc_flush_tlb_page_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
- __INIT
-
- /* High speed page clear/copy. */
-hypersparc_bzero_1page:
-/* NOTE: This routine has to be shorter than 40insns --jj */
- clr %g1
- mov 32, %g2
- mov 64, %g3
- mov 96, %g4
- mov 128, %g5
- mov 160, %g7
- mov 192, %o2
- mov 224, %o3
- mov 16, %o1
-1:
- stda %g0, [%o0 + %g0] ASI_M_BFILL
- stda %g0, [%o0 + %g2] ASI_M_BFILL
- stda %g0, [%o0 + %g3] ASI_M_BFILL
- stda %g0, [%o0 + %g4] ASI_M_BFILL
- stda %g0, [%o0 + %g5] ASI_M_BFILL
- stda %g0, [%o0 + %g7] ASI_M_BFILL
- stda %g0, [%o0 + %o2] ASI_M_BFILL
- stda %g0, [%o0 + %o3] ASI_M_BFILL
- subcc %o1, 1, %o1
- bne 1b
- add %o0, 256, %o0
-
- retl
- nop
-
-hypersparc_copy_1page:
-/* NOTE: This routine has to be shorter than 70insns --jj */
- sub %o1, %o0, %o2 ! difference
- mov 16, %g1
-1:
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- add %o0, 32, %o0
- sta %o0, [%o0 + %o2] ASI_M_BCOPY
- subcc %g1, 1, %g1
- bne 1b
- add %o0, 32, %o0
-
- retl
- nop
-
- .globl hypersparc_setup_blockops
-hypersparc_setup_blockops:
- sethi %hi(bzero_1page), %o0
- or %o0, %lo(bzero_1page), %o0
- sethi %hi(hypersparc_bzero_1page), %o1
- or %o1, %lo(hypersparc_bzero_1page), %o1
- sethi %hi(hypersparc_copy_1page), %o2
- or %o2, %lo(hypersparc_copy_1page), %o2
- ld [%o1], %o4
-1:
- add %o1, 4, %o1
- st %o4, [%o0]
- add %o0, 4, %o0
- cmp %o1, %o2
- bne 1b
- ld [%o1], %o4
- sethi %hi(__copy_1page), %o0
- or %o0, %lo(__copy_1page), %o0
- sethi %hi(hypersparc_setup_blockops), %o2
- or %o2, %lo(hypersparc_setup_blockops), %o2
- ld [%o1], %o4
-1:
- add %o1, 4, %o1
- st %o4, [%o0]
- add %o0, 4, %o0
- cmp %o1, %o2
- bne 1b
- ld [%o1], %o4
- sta %g0, [%g0] ASI_M_FLUSH_IWHOLE
- retl
- nop
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
index d94d7868feb9..a2cfa8757795 100644
--- a/arch/sparc/mm/io-unit.c
+++ b/arch/sparc/mm/io-unit.c
@@ -18,7 +18,6 @@
#include <asm/io.h>
#include <asm/io-unit.h>
-#include <asm/mxcc.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index 832e5ff8b663..482e08df7bad 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -18,7 +18,6 @@
#include <linux/platform_device.h>
#include <asm/io.h>
-#include <asm/mxcc.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/bitext.h>
@@ -37,11 +36,6 @@
#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
-static int viking_flush;
-/* viking.S */
-extern void viking_flush_page(unsigned long page);
-extern void viking_mxcc_flush_page(unsigned long page);
-
/*
* Values precomputed according to CPU type.
*/
@@ -156,21 +150,9 @@ static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
start = (unsigned long)iopte;
end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
start &= PAGE_MASK;
- if (viking_mxcc_present) {
- while(start < end) {
- viking_mxcc_flush_page(start);
- start += PAGE_SIZE;
- }
- } else if (viking_flush) {
- while(start < end) {
- viking_flush_page(start);
- start += PAGE_SIZE;
- }
- } else {
- while(start < end) {
- __flush_page_to_ram(start);
- start += PAGE_SIZE;
- }
+ while(start < end) {
+ __flush_page_to_ram(start);
+ start += PAGE_SIZE;
}
}
@@ -344,12 +326,7 @@ static void *sbus_iommu_alloc(struct device *dev, size_t len,
pmd_t *pmdp;
pte_t *ptep;
- if (viking_mxcc_present)
- viking_mxcc_flush_page(page);
- else if (viking_flush)
- viking_flush_page(page);
- else
- __flush_page_to_ram(page);
+ __flush_page_to_ram(page);
pmdp = pmd_off_k(addr);
ptep = pte_offset_kernel(pmdp, addr);
diff --git a/arch/sparc/mm/mm_32.h b/arch/sparc/mm/mm_32.h
index ee55f1080634..2c83b8ce742d 100644
--- a/arch/sparc/mm/mm_32.h
+++ b/arch/sparc/mm/mm_32.h
@@ -9,7 +9,6 @@ void window_ret_fault(struct pt_regs *regs);
/* srmmu.c */
extern char *srmmu_name;
-extern int viking_mxcc_present;
extern int flush_page_for_dma_global;
extern void (*poke_srmmu)(void);
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 3a7e10729a02..0f171194fc16 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -40,20 +40,10 @@
#include <asm/io.h>
/* Now the cpu specific definitions. */
-#include <asm/turbosparc.h>
-#include <asm/tsunami.h>
-#include <asm/viking.h>
-#include <asm/swift.h>
#include <asm/leon.h>
-#include <asm/mxcc.h>
-#include <asm/ross.h>
#include "mm_32.h"
-int vac_cache_size;
-EXPORT_SYMBOL(vac_cache_size);
-int vac_line_size;
-
extern struct resource sparc_iomap;
extern unsigned long last_valid_pfn;
@@ -65,12 +55,6 @@ EXPORT_SYMBOL(sparc32_cachetlb_ops);
#ifdef CONFIG_SMP
const struct sparc32_cachetlb_ops *local_ops;
-
-#define FLUSH_BEGIN(mm)
-#define FLUSH_END
-#else
-#define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
-#define FLUSH_END }
#endif
int flush_page_for_dma_global = 1;
@@ -80,11 +64,8 @@ char *srmmu_name;
ctxd_t *srmmu_ctx_table_phys;
static ctxd_t *srmmu_context_table;
-int viking_mxcc_present;
static DEFINE_SPINLOCK(srmmu_context_spinlock);
-static int is_hypersparc;
-
static int srmmu_cache_pagetables;
/* these will be initialized in srmmu_nocache_calcsize() */
@@ -112,25 +93,6 @@ static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
set_pte((pte_t *)ctxp, pte);
}
-/*
- * Locations of MSI Registers.
- */
-#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
-
-/*
- * Useful bits in the MSI Registers.
- */
-#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
-
-static void msi_set_sync(void)
-{
- __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
- "andn %%g3, %2, %%g3\n\t"
- "sta %%g3, [%0] %1\n\t" : :
- "r" (MSI_MBUS_ARBEN),
- "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
-}
-
void pmd_set(pmd_t *pmdp, pte_t *ptep)
{
unsigned long ptp = __nocache_pa(ptep) >> 4;
@@ -478,11 +440,7 @@ void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
}
- if (sparc_cpu_model == sparc_leon)
- leon_switch_mm();
-
- if (is_hypersparc)
- hyper_flush_whole_icache();
+ leon_switch_mm();
srmmu_set_context(mm->context);
}
@@ -557,110 +515,6 @@ void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
flush_tlb_all();
}
-/* tsunami.S */
-extern void tsunami_flush_cache_all(void);
-extern void tsunami_flush_cache_mm(struct mm_struct *mm);
-extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void tsunami_flush_page_to_ram(unsigned long page);
-extern void tsunami_flush_page_for_dma(unsigned long page);
-extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-extern void tsunami_flush_tlb_all(void);
-extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
-extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-extern void tsunami_setup_blockops(void);
-
-/* swift.S */
-extern void swift_flush_cache_all(void);
-extern void swift_flush_cache_mm(struct mm_struct *mm);
-extern void swift_flush_cache_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void swift_flush_page_to_ram(unsigned long page);
-extern void swift_flush_page_for_dma(unsigned long page);
-extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-extern void swift_flush_tlb_all(void);
-extern void swift_flush_tlb_mm(struct mm_struct *mm);
-extern void swift_flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-
-#if 0 /* P3: deadwood to debug precise flushes on Swift. */
-void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- int cctx, ctx1;
-
- page &= PAGE_MASK;
- if ((ctx1 = vma->vm_mm->context) != -1) {
- cctx = srmmu_get_context();
-/* Is context # ever different from current context? P3 */
- if (cctx != ctx1) {
- printk("flush ctx %02x curr %02x\n", ctx1, cctx);
- srmmu_set_context(ctx1);
- swift_flush_page(page);
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (page), "i" (ASI_M_FLUSH_PROBE));
- srmmu_set_context(cctx);
- } else {
- /* Rm. prot. bits from virt. c. */
- /* swift_flush_cache_all(); */
- /* swift_flush_cache_page(vma, page); */
- swift_flush_page(page);
-
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
- "r" (page), "i" (ASI_M_FLUSH_PROBE));
- /* same as above: srmmu_flush_tlb_page() */
- }
- }
-}
-#endif
-
-/*
- * The following are all MBUS based SRMMU modules, and therefore could
- * be found in a multiprocessor configuration. On the whole, these
- * chips seems to be much more touchy about DVMA and page tables
- * with respect to cache coherency.
- */
-
-/* viking.S */
-extern void viking_flush_cache_all(void);
-extern void viking_flush_cache_mm(struct mm_struct *mm);
-extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void viking_flush_page_to_ram(unsigned long page);
-extern void viking_flush_page_for_dma(unsigned long page);
-extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
-extern void viking_flush_page(unsigned long page);
-extern void viking_mxcc_flush_page(unsigned long page);
-extern void viking_flush_tlb_all(void);
-extern void viking_flush_tlb_mm(struct mm_struct *mm);
-extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-extern void viking_flush_tlb_page(struct vm_area_struct *vma,
- unsigned long page);
-extern void sun4dsmp_flush_tlb_all(void);
-extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
-extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end);
-extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
- unsigned long page);
-
-/* hypersparc.S */
-extern void hypersparc_flush_cache_all(void);
-extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
-extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void hypersparc_flush_page_to_ram(unsigned long page);
-extern void hypersparc_flush_page_for_dma(unsigned long page);
-extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-extern void hypersparc_flush_tlb_all(void);
-extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
-extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
-extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
-extern void hypersparc_setup_blockops(void);
-
/*
* NOTE: All of this startup code assumes the low 16mb (approx.) of
* kernel mappings are done with one single contiguous chunk of
@@ -747,18 +601,7 @@ static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
/* These flush types are not available on all chips... */
static inline unsigned long srmmu_probe(unsigned long vaddr)
{
- unsigned long retval;
-
- if (sparc_cpu_model != sparc_leon) {
-
- vaddr &= PAGE_MASK;
- __asm__ __volatile__("lda [%1] %2, %0\n\t" :
- "=r" (retval) :
- "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
- } else {
- retval = leon_swprobe(vaddr, NULL);
- }
- return retval;
+ return leon_swprobe(vaddr, NULL);
}
/*
@@ -904,20 +747,16 @@ void __init srmmu_paging_init(void)
init_mm.context = (unsigned long) NO_CONTEXT;
sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
- if (sparc_cpu_model == sun4d)
- num_contexts = 65536; /* We know it is Viking */
- else {
- /* Find the number of contexts on the srmmu. */
- cpunode = prom_getchild(prom_root_node);
- num_contexts = 0;
- while (cpunode != 0) {
- prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
- if (!strcmp(node_str, "cpu")) {
- num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
- break;
- }
- cpunode = prom_getsibling(cpunode);
+ /* Find the number of contexts on the srmmu. */
+ cpunode = prom_getchild(prom_root_node);
+ num_contexts = 0;
+ while (cpunode != 0) {
+ prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
+ if (!strcmp(node_str, "cpu")) {
+ num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
+ break;
}
+ cpunode = prom_getsibling(cpunode);
}
if (!num_contexts) {
@@ -1014,577 +853,6 @@ void destroy_context(struct mm_struct *mm)
}
}
-/* Init various srmmu chip types. */
-static void __init srmmu_is_bad(void)
-{
- prom_printf("Could not determine SRMMU chip type.\n");
- prom_halt();
-}
-
-static void __init init_vac_layout(void)
-{
- phandle nd;
- int cache_lines;
- char node_str[128];
-#ifdef CONFIG_SMP
- int cpu = 0;
- unsigned long max_size = 0;
- unsigned long min_line_size = 0x10000000;
-#endif
-
- nd = prom_getchild(prom_root_node);
- while ((nd = prom_getsibling(nd)) != 0) {
- prom_getstring(nd, "device_type", node_str, sizeof(node_str));
- if (!strcmp(node_str, "cpu")) {
- vac_line_size = prom_getint(nd, "cache-line-size");
- if (vac_line_size == -1) {
- prom_printf("can't determine cache-line-size, halting.\n");
- prom_halt();
- }
- cache_lines = prom_getint(nd, "cache-nlines");
- if (cache_lines == -1) {
- prom_printf("can't determine cache-nlines, halting.\n");
- prom_halt();
- }
-
- vac_cache_size = cache_lines * vac_line_size;
-#ifdef CONFIG_SMP
- if (vac_cache_size > max_size)
- max_size = vac_cache_size;
- if (vac_line_size < min_line_size)
- min_line_size = vac_line_size;
- //FIXME: cpus not contiguous!!
- cpu++;
- if (cpu >= nr_cpu_ids || !cpu_online(cpu))
- break;
-#else
- break;
-#endif
- }
- }
- if (nd == 0) {
- prom_printf("No CPU nodes found, halting.\n");
- prom_halt();
- }
-#ifdef CONFIG_SMP
- vac_cache_size = max_size;
- vac_line_size = min_line_size;
-#endif
- printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
- (int)vac_cache_size, (int)vac_line_size);
-}
-
-static void poke_hypersparc(void)
-{
- volatile unsigned long clear;
- unsigned long mreg = srmmu_get_mmureg();
-
- hyper_flush_unconditional_combined();
-
- mreg &= ~(HYPERSPARC_CWENABLE);
- mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
- mreg |= (HYPERSPARC_CMODE);
-
- srmmu_set_mmureg(mreg);
-
-#if 0 /* XXX I think this is bad news... -DaveM */
- hyper_clear_all_tags();
-#endif
-
- put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
- hyper_flush_whole_icache();
- clear = srmmu_get_faddr();
- clear = srmmu_get_fstatus();
-}
-
-static const struct sparc32_cachetlb_ops hypersparc_ops = {
- .cache_all = hypersparc_flush_cache_all,
- .cache_mm = hypersparc_flush_cache_mm,
- .cache_page = hypersparc_flush_cache_page,
- .cache_range = hypersparc_flush_cache_range,
- .tlb_all = hypersparc_flush_tlb_all,
- .tlb_mm = hypersparc_flush_tlb_mm,
- .tlb_page = hypersparc_flush_tlb_page,
- .tlb_range = hypersparc_flush_tlb_range,
- .page_to_ram = hypersparc_flush_page_to_ram,
- .sig_insns = hypersparc_flush_sig_insns,
- .page_for_dma = hypersparc_flush_page_for_dma,
-};
-
-static void __init init_hypersparc(void)
-{
- srmmu_name = "ROSS HyperSparc";
-
- init_vac_layout();
-
- is_hypersparc = 1;
- sparc32_cachetlb_ops = &hypersparc_ops;
-
- poke_srmmu = poke_hypersparc;
-
- hypersparc_setup_blockops();
-}
-
-static void poke_swift(void)
-{
- unsigned long mreg;
-
- /* Clear any crap from the cache or else... */
- swift_flush_cache_all();
-
- /* Enable I & D caches */
- mreg = srmmu_get_mmureg();
- mreg |= (SWIFT_IE | SWIFT_DE);
- /*
- * The Swift branch folding logic is completely broken. At
- * trap time, if things are just right, if can mistakenly
- * think that a trap is coming from kernel mode when in fact
- * it is coming from user mode (it mis-executes the branch in
- * the trap code). So you see things like crashme completely
- * hosing your machine which is completely unacceptable. Turn
- * this shit off... nice job Fujitsu.
- */
- mreg &= ~(SWIFT_BF);
- srmmu_set_mmureg(mreg);
-}
-
-static const struct sparc32_cachetlb_ops swift_ops = {
- .cache_all = swift_flush_cache_all,
- .cache_mm = swift_flush_cache_mm,
- .cache_page = swift_flush_cache_page,
- .cache_range = swift_flush_cache_range,
- .tlb_all = swift_flush_tlb_all,
- .tlb_mm = swift_flush_tlb_mm,
- .tlb_page = swift_flush_tlb_page,
- .tlb_range = swift_flush_tlb_range,
- .page_to_ram = swift_flush_page_to_ram,
- .sig_insns = swift_flush_sig_insns,
- .page_for_dma = swift_flush_page_for_dma,
-};
-
-#define SWIFT_MASKID_ADDR 0x10003018
-static void __init init_swift(void)
-{
- unsigned long swift_rev;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t"
- "srl %0, 0x18, %0\n\t" :
- "=r" (swift_rev) :
- "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
- srmmu_name = "Fujitsu Swift";
-
- sparc32_cachetlb_ops = &swift_ops;
- flush_page_for_dma_global = 0;
-
- /*
- * Are you now convinced that the Swift is one of the
- * biggest VLSI abortions of all time? Bravo Fujitsu!
- * Fujitsu, the !#?!%$'d up processor people. I bet if
- * you examined the microcode of the Swift you'd find
- * XXX's all over the place.
- */
- poke_srmmu = poke_swift;
-}
-
-static void turbosparc_flush_cache_all(void)
-{
- flush_user_windows();
- turbosparc_idflash_clear();
-}
-
-static void turbosparc_flush_cache_mm(struct mm_struct *mm)
-{
- FLUSH_BEGIN(mm)
- flush_user_windows();
- turbosparc_idflash_clear();
- FLUSH_END
-}
-
-static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
- FLUSH_BEGIN(vma->vm_mm)
- flush_user_windows();
- turbosparc_idflash_clear();
- FLUSH_END
-}
-
-static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
-{
- FLUSH_BEGIN(vma->vm_mm)
- flush_user_windows();
- if (vma->vm_flags & VM_EXEC)
- turbosparc_flush_icache();
- turbosparc_flush_dcache();
- FLUSH_END
-}
-
-/* TurboSparc is copy-back, if we turn it on, but this does not work. */
-static void turbosparc_flush_page_to_ram(unsigned long page)
-{
-#ifdef TURBOSPARC_WRITEBACK
- volatile unsigned long clear;
-
- if (srmmu_probe(page))
- turbosparc_flush_page_cache(page);
- clear = srmmu_get_fstatus();
-#endif
-}
-
-static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
-{
-}
-
-static void turbosparc_flush_page_for_dma(unsigned long page)
-{
- turbosparc_flush_dcache();
-}
-
-static void turbosparc_flush_tlb_all(void)
-{
- srmmu_flush_whole_tlb();
-}
-
-static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
-{
- FLUSH_BEGIN(mm)
- srmmu_flush_whole_tlb();
- FLUSH_END
-}
-
-static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
- FLUSH_BEGIN(vma->vm_mm)
- srmmu_flush_whole_tlb();
- FLUSH_END
-}
-
-static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- FLUSH_BEGIN(vma->vm_mm)
- srmmu_flush_whole_tlb();
- FLUSH_END
-}
-
-
-static void poke_turbosparc(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
- unsigned long ccreg;
-
- /* Clear any crap from the cache or else... */
- turbosparc_flush_cache_all();
- /* Temporarily disable I & D caches */
- mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
- mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
- srmmu_set_mmureg(mreg);
-
- ccreg = turbosparc_get_ccreg();
-
-#ifdef TURBOSPARC_WRITEBACK
- ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
- ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
- /* Write-back D-cache, emulate VLSI
- * abortion number three, not number one */
-#else
- /* For now let's play safe, optimize later */
- ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
- /* Do DVMA snooping in Dcache, Write-thru D-cache */
- ccreg &= ~(TURBOSPARC_uS2);
- /* Emulate VLSI abortion number three, not number one */
-#endif
-
- switch (ccreg & 7) {
- case 0: /* No SE cache */
- case 7: /* Test mode */
- break;
- default:
- ccreg |= (TURBOSPARC_SCENABLE);
- }
- turbosparc_set_ccreg(ccreg);
-
- mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
- mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
- srmmu_set_mmureg(mreg);
-}
-
-static const struct sparc32_cachetlb_ops turbosparc_ops = {
- .cache_all = turbosparc_flush_cache_all,
- .cache_mm = turbosparc_flush_cache_mm,
- .cache_page = turbosparc_flush_cache_page,
- .cache_range = turbosparc_flush_cache_range,
- .tlb_all = turbosparc_flush_tlb_all,
- .tlb_mm = turbosparc_flush_tlb_mm,
- .tlb_page = turbosparc_flush_tlb_page,
- .tlb_range = turbosparc_flush_tlb_range,
- .page_to_ram = turbosparc_flush_page_to_ram,
- .sig_insns = turbosparc_flush_sig_insns,
- .page_for_dma = turbosparc_flush_page_for_dma,
-};
-
-static void __init init_turbosparc(void)
-{
- srmmu_name = "Fujitsu TurboSparc";
- sparc32_cachetlb_ops = &turbosparc_ops;
- poke_srmmu = poke_turbosparc;
-}
-
-static void poke_tsunami(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
-
- tsunami_flush_icache();
- tsunami_flush_dcache();
- mreg &= ~TSUNAMI_ITD;
- mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
- srmmu_set_mmureg(mreg);
-}
-
-static const struct sparc32_cachetlb_ops tsunami_ops = {
- .cache_all = tsunami_flush_cache_all,
- .cache_mm = tsunami_flush_cache_mm,
- .cache_page = tsunami_flush_cache_page,
- .cache_range = tsunami_flush_cache_range,
- .tlb_all = tsunami_flush_tlb_all,
- .tlb_mm = tsunami_flush_tlb_mm,
- .tlb_page = tsunami_flush_tlb_page,
- .tlb_range = tsunami_flush_tlb_range,
- .page_to_ram = tsunami_flush_page_to_ram,
- .sig_insns = tsunami_flush_sig_insns,
- .page_for_dma = tsunami_flush_page_for_dma,
-};
-
-static void __init init_tsunami(void)
-{
- /*
- * Tsunami's pretty sane, Sun and TI actually got it
- * somewhat right this time. Fujitsu should have
- * taken some lessons from them.
- */
-
- srmmu_name = "TI Tsunami";
- sparc32_cachetlb_ops = &tsunami_ops;
- poke_srmmu = poke_tsunami;
-
- tsunami_setup_blockops();
-}
-
-static void poke_viking(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
- static int smp_catch;
-
- if (viking_mxcc_present) {
- unsigned long mxcc_control = mxcc_get_creg();
-
- mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
- mxcc_control &= ~(MXCC_CTL_RRC);
- mxcc_set_creg(mxcc_control);
-
- /*
- * We don't need memory parity checks.
- * XXX This is a mess, have to dig out later. ecd.
- viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
- */
-
- /* We do cache ptables on MXCC. */
- mreg |= VIKING_TCENABLE;
- } else {
- unsigned long bpreg;
-
- mreg &= ~(VIKING_TCENABLE);
- if (smp_catch++) {
- /* Must disable mixed-cmd mode here for other cpu's. */
- bpreg = viking_get_bpreg();
- bpreg &= ~(VIKING_ACTION_MIX);
- viking_set_bpreg(bpreg);
-
- /* Just in case PROM does something funny. */
- msi_set_sync();
- }
- }
-
- mreg |= VIKING_SPENABLE;
- mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
- mreg |= VIKING_SBENABLE;
- mreg &= ~(VIKING_ACENABLE);
- srmmu_set_mmureg(mreg);
-}
-
-static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
- .cache_all = viking_flush_cache_all,
- .cache_mm = viking_flush_cache_mm,
- .cache_page = viking_flush_cache_page,
- .cache_range = viking_flush_cache_range,
- .tlb_all = viking_flush_tlb_all,
- .tlb_mm = viking_flush_tlb_mm,
- .tlb_page = viking_flush_tlb_page,
- .tlb_range = viking_flush_tlb_range,
- .page_to_ram = viking_flush_page_to_ram,
- .sig_insns = viking_flush_sig_insns,
- .page_for_dma = viking_flush_page_for_dma,
-};
-
-#ifdef CONFIG_SMP
-/* On sun4d the cpu broadcasts local TLB flushes, so we can just
- * perform the local TLB flush and all the other cpus will see it.
- * But, unfortunately, there is a bug in the sun4d XBUS backplane
- * that requires that we add some synchronization to these flushes.
- *
- * The bug is that the fifo which keeps track of all the pending TLB
- * broadcasts in the system is an entry or two too small, so if we
- * have too many going at once we'll overflow that fifo and lose a TLB
- * flush resulting in corruption.
- *
- * Our workaround is to take a global spinlock around the TLB flushes,
- * which guarentees we won't ever have too many pending. It's a big
- * hammer, but a semaphore like system to make sure we only have N TLB
- * flushes going at once will require SMP locking anyways so there's
- * no real value in trying any harder than this.
- */
-static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
- .cache_all = viking_flush_cache_all,
- .cache_mm = viking_flush_cache_mm,
- .cache_page = viking_flush_cache_page,
- .cache_range = viking_flush_cache_range,
- .tlb_all = sun4dsmp_flush_tlb_all,
- .tlb_mm = sun4dsmp_flush_tlb_mm,
- .tlb_page = sun4dsmp_flush_tlb_page,
- .tlb_range = sun4dsmp_flush_tlb_range,
- .page_to_ram = viking_flush_page_to_ram,
- .sig_insns = viking_flush_sig_insns,
- .page_for_dma = viking_flush_page_for_dma,
-};
-#endif
-
-static void __init init_viking(void)
-{
- unsigned long mreg = srmmu_get_mmureg();
-
- /* Ahhh, the viking. SRMMU VLSI abortion number two... */
- if (mreg & VIKING_MMODE) {
- srmmu_name = "TI Viking";
- viking_mxcc_present = 0;
- msi_set_sync();
-
- /*
- * We need this to make sure old viking takes no hits
- * on its cache for dma snoops to workaround the
- * "load from non-cacheable memory" interrupt bug.
- * This is only necessary because of the new way in
- * which we use the IOMMU.
- */
- viking_ops.page_for_dma = viking_flush_page;
-#ifdef CONFIG_SMP
- viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
-#endif
- flush_page_for_dma_global = 0;
- } else {
- srmmu_name = "TI Viking/MXCC";
- viking_mxcc_present = 1;
- srmmu_cache_pagetables = 1;
- }
-
- sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
- &viking_ops;
-#ifdef CONFIG_SMP
- if (sparc_cpu_model == sun4d)
- sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
- &viking_sun4d_smp_ops;
-#endif
-
- poke_srmmu = poke_viking;
-}
-
-/* Probe for the srmmu chip version. */
-static void __init get_srmmu_type(void)
-{
- unsigned long mreg, psr;
- unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
-
- mreg = srmmu_get_mmureg(); psr = get_psr();
- mod_typ = (mreg & 0xf0000000) >> 28;
- mod_rev = (mreg & 0x0f000000) >> 24;
- psr_typ = (psr >> 28) & 0xf;
- psr_vers = (psr >> 24) & 0xf;
-
- /* First, check for sparc-leon. */
- if (sparc_cpu_model == sparc_leon) {
- init_leon();
- return;
- }
-
- /* Second, check for HyperSparc or Cypress. */
- if (mod_typ == 1) {
- switch (mod_rev) {
- case 7:
- /* UP or MP Hypersparc */
- init_hypersparc();
- break;
- case 0:
- case 2:
- case 10:
- case 11:
- case 12:
- case 13:
- case 14:
- case 15:
- default:
- prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
- prom_halt();
- break;
- }
- return;
- }
-
- /* Now Fujitsu TurboSparc. It might happen that it is
- * in Swift emulation mode, so we will check later...
- */
- if (psr_typ == 0 && psr_vers == 5) {
- init_turbosparc();
- return;
- }
-
- /* Next check for Fujitsu Swift. */
- if (psr_typ == 0 && psr_vers == 4) {
- phandle cpunode;
- char node_str[128];
-
- /* Look if it is not a TurboSparc emulating Swift... */
- cpunode = prom_getchild(prom_root_node);
- while ((cpunode = prom_getsibling(cpunode)) != 0) {
- prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
- if (!strcmp(node_str, "cpu")) {
- if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
- prom_getintdefault(cpunode, "psr-version", 1) == 5) {
- init_turbosparc();
- return;
- }
- break;
- }
- }
-
- init_swift();
- return;
- }
-
- /* Now the Viking family of srmmu. */
- if (psr_typ == 4 &&
- ((psr_vers == 0) ||
- ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
- init_viking();
- return;
- }
-
- /* Finally the Tsunami. */
- if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
- init_tsunami();
- return;
- }
-
- /* Oh well */
- srmmu_is_bad();
-}
-
#ifdef CONFIG_SMP
/* Local cross-calls. */
static void smp_flush_page_for_dma(unsigned long page)
@@ -1734,34 +1002,20 @@ static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
};
#endif
-/* Load up routines and constants for sun4m and sun4d mmu */
+/* Load up routines and constants for mmu */
void __init load_mmu(void)
{
/* Functions */
- get_srmmu_type();
+ init_leon();
#ifdef CONFIG_SMP
/* El switcheroo... */
local_ops = sparc32_cachetlb_ops;
- if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
- smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
- smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
- smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
- smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
- }
-
- if (poke_srmmu == poke_viking) {
- /* Avoid unnecessary cross calls. */
- smp_cachetlb_ops.cache_all = local_ops->cache_all;
- smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
- smp_cachetlb_ops.cache_range = local_ops->cache_range;
- smp_cachetlb_ops.cache_page = local_ops->cache_page;
-
- smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
- smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
- smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
- }
+ smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
+ smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
+ smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
+ smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
/* It really is const after this point. */
sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
diff --git a/arch/sparc/mm/swift.S b/arch/sparc/mm/swift.S
deleted file mode 100644
index f414bfd8d899..000000000000
--- a/arch/sparc/mm/swift.S
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * swift.S: MicroSparc-II mmu/cache operations.
- *
- * Copyright (C) 1999 David S. Miller ([email protected])
- */
-
-#include <asm/psr.h>
-#include <asm/asi.h>
-#include <asm/page.h>
-#include <asm/pgtsrmmu.h>
-#include <asm/asm-offsets.h>
-
- .text
- .align 4
-
-#if 1 /* XXX screw this, I can't get the VAC flushes working
- * XXX reliably... -DaveM
- */
- .globl swift_flush_cache_all, swift_flush_cache_mm
- .globl swift_flush_cache_range, swift_flush_cache_page
- .globl swift_flush_page_for_dma
- .globl swift_flush_page_to_ram
-
-swift_flush_cache_all:
-swift_flush_cache_mm:
-swift_flush_cache_range:
-swift_flush_cache_page:
-swift_flush_page_for_dma:
-swift_flush_page_to_ram:
- sethi %hi(0x2000), %o0
-1: subcc %o0, 0x10, %o0
- add %o0, %o0, %o1
- sta %g0, [%o0] ASI_M_DATAC_TAG
- bne 1b
- sta %g0, [%o1] ASI_M_TXTC_TAG
- retl
- nop
-#else
-
- .globl swift_flush_cache_all
-swift_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
-
- /* Just clear out all the tags. */
- sethi %hi(16 * 1024), %o0
-1: subcc %o0, 16, %o0
- sta %g0, [%o0] ASI_M_TXTC_TAG
- bne 1b
- sta %g0, [%o0] ASI_M_DATAC_TAG
- retl
- nop
-
- .globl swift_flush_cache_mm
-swift_flush_cache_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be swift_flush_cache_mm_out
- WINDOW_FLUSH(%g4, %g5)
- rd %psr, %g1
- andn %g1, PSR_ET, %g3
- wr %g3, 0x0, %psr
- nop
- nop
- mov SRMMU_CTX_REG, %g7
- lda [%g7] ASI_M_MMUREGS, %g5
- sta %g2, [%g7] ASI_M_MMUREGS
-
-#if 1
- sethi %hi(0x2000), %o0
-1: subcc %o0, 0x10, %o0
- sta %g0, [%o0] ASI_M_FLUSH_CTX
- bne 1b
- nop
-#else
- clr %o0
- or %g0, 2048, %g7
- or %g0, 2048, %o1
- add %o1, 2048, %o2
- add %o2, 2048, %o3
- mov 16, %o4
- add %o4, 2048, %o5
- add %o5, 2048, %g2
- add %g2, 2048, %g3
-1: sta %g0, [%o0 ] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
- sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
- subcc %g7, 32, %g7
- bne 1b
- add %o0, 32, %o0
-#endif
-
- mov SRMMU_CTX_REG, %g7
- sta %g5, [%g7] ASI_M_MMUREGS
- wr %g1, 0x0, %psr
- nop
- nop
-swift_flush_cache_mm_out:
- retl
- nop
-
- .globl swift_flush_cache_range
-swift_flush_cache_range:
- ld [%o0 + VMA_VM_MM], %o0
- sub %o2, %o1, %o2
- sethi %hi(4096), %o3
- cmp %o2, %o3
- bgu swift_flush_cache_mm
- nop
- b 70f
- nop
-
- .globl swift_flush_cache_page
-swift_flush_cache_page:
- ld [%o0 + VMA_VM_MM], %o0
-70:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be swift_flush_cache_page_out
- WINDOW_FLUSH(%g4, %g5)
- rd %psr, %g1
- andn %g1, PSR_ET, %g3
- wr %g3, 0x0, %psr
- nop
- nop
- mov SRMMU_CTX_REG, %g7
- lda [%g7] ASI_M_MMUREGS, %g5
- sta %g2, [%g7] ASI_M_MMUREGS
-
- andn %o1, (PAGE_SIZE - 1), %o1
-#if 1
- sethi %hi(0x1000), %o0
-1: subcc %o0, 0x10, %o0
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- bne 1b
- nop
-#else
- or %g0, 512, %g7
- or %g0, 512, %o0
- add %o0, 512, %o2
- add %o2, 512, %o3
- add %o3, 512, %o4
- add %o4, 512, %o5
- add %o5, 512, %g3
- add %g3, 512, %g4
-1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
- subcc %g7, 16, %g7
- bne 1b
- add %o1, 16, %o1
-#endif
-
- mov SRMMU_CTX_REG, %g7
- sta %g5, [%g7] ASI_M_MMUREGS
- wr %g1, 0x0, %psr
- nop
- nop
-swift_flush_cache_page_out:
- retl
- nop
-
- /* Swift is write-thru, however it is not
- * I/O nor TLB-walk coherent. Also it has
- * caches which are virtually indexed and tagged.
- */
- .globl swift_flush_page_for_dma
- .globl swift_flush_page_to_ram
-swift_flush_page_for_dma:
-swift_flush_page_to_ram:
- andn %o0, (PAGE_SIZE - 1), %o1
-#if 1
- sethi %hi(0x1000), %o0
-1: subcc %o0, 0x10, %o0
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- bne 1b
- nop
-#else
- or %g0, 512, %g7
- or %g0, 512, %o0
- add %o0, 512, %o2
- add %o2, 512, %o3
- add %o3, 512, %o4
- add %o4, 512, %o5
- add %o5, 512, %g3
- add %g3, 512, %g4
-1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
- sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
- subcc %g7, 16, %g7
- bne 1b
- add %o1, 16, %o1
-#endif
- retl
- nop
-#endif
-
- .globl swift_flush_sig_insns
-swift_flush_sig_insns:
- flush %o1
- retl
- flush %o1 + 4
-
- .globl swift_flush_tlb_mm
- .globl swift_flush_tlb_range
- .globl swift_flush_tlb_all
-swift_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
-swift_flush_tlb_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be swift_flush_tlb_all_out
-swift_flush_tlb_all:
- mov 0x400, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-swift_flush_tlb_all_out:
- retl
- nop
-
- .globl swift_flush_tlb_page
-swift_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- andn %o1, (PAGE_SIZE - 1), %o1
- cmp %o3, -1
- be swift_flush_tlb_page_out
- nop
-#if 1
- mov 0x400, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-#else
- lda [%g1] ASI_M_MMUREGS, %g5
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
-#endif
-swift_flush_tlb_page_out:
- retl
- nop
diff --git a/arch/sparc/mm/tsunami.S b/arch/sparc/mm/tsunami.S
deleted file mode 100644
index 62b742df65dc..000000000000
--- a/arch/sparc/mm/tsunami.S
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * tsunami.S: High speed MicroSparc-I mmu/cache operations.
- *
- * Copyright (C) 1997 David S. Miller ([email protected])
- */
-
-#include <asm/ptrace.h>
-#include <asm/asm-offsets.h>
-#include <asm/psr.h>
-#include <asm/asi.h>
-#include <asm/page.h>
-#include <asm/pgtsrmmu.h>
-
- .text
- .align 4
-
- .globl tsunami_flush_cache_all, tsunami_flush_cache_mm
- .globl tsunami_flush_cache_range, tsunami_flush_cache_page
- .globl tsunami_flush_page_to_ram, tsunami_flush_page_for_dma
- .globl tsunami_flush_sig_insns
- .globl tsunami_flush_tlb_all, tsunami_flush_tlb_mm
- .globl tsunami_flush_tlb_range, tsunami_flush_tlb_page
-
- /* Sliiick... */
-tsunami_flush_cache_page:
-tsunami_flush_cache_range:
- ld [%o0 + VMA_VM_MM], %o0
-tsunami_flush_cache_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be tsunami_flush_cache_out
-tsunami_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
-tsunami_flush_page_for_dma:
- sta %g0, [%g0] ASI_M_IC_FLCLEAR
- sta %g0, [%g0] ASI_M_DC_FLCLEAR
-tsunami_flush_cache_out:
-tsunami_flush_page_to_ram:
- retl
- nop
-
-tsunami_flush_sig_insns:
- flush %o1
- retl
- flush %o1 + 4
-
- /* More slick stuff... */
-tsunami_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
-tsunami_flush_tlb_mm:
- ld [%o0 + AOFF_mm_context], %g2
- cmp %g2, -1
- be tsunami_flush_tlb_out
-tsunami_flush_tlb_all:
- mov 0x400, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- nop
- nop
- nop
- nop
- nop
-tsunami_flush_tlb_out:
- retl
- nop
-
- /* This one can be done in a fine grained manner... */
-tsunami_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- andn %o1, (PAGE_SIZE - 1), %o1
- cmp %o3, -1
- be tsunami_flush_tlb_page_out
- lda [%g1] ASI_M_MMUREGS, %g5
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- nop
- nop
- nop
- nop
- nop
-tsunami_flush_tlb_page_out:
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-
-#define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \
- ldd [src + offset + 0x18], t0; \
- std t0, [dst + offset + 0x18]; \
- ldd [src + offset + 0x10], t2; \
- std t2, [dst + offset + 0x10]; \
- ldd [src + offset + 0x08], t0; \
- std t0, [dst + offset + 0x08]; \
- ldd [src + offset + 0x00], t2; \
- std t2, [dst + offset + 0x00];
-
-tsunami_copy_1page:
-/* NOTE: This routine has to be shorter than 70insns --jj */
- or %g0, (PAGE_SIZE >> 8), %g1
-1:
- MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5)
- MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5)
- subcc %g1, 1, %g1
- add %o0, 0x100, %o0
- bne 1b
- add %o1, 0x100, %o1
-
- .globl tsunami_setup_blockops
-tsunami_setup_blockops:
- sethi %hi(__copy_1page), %o0
- or %o0, %lo(__copy_1page), %o0
- sethi %hi(tsunami_copy_1page), %o1
- or %o1, %lo(tsunami_copy_1page), %o1
- sethi %hi(tsunami_setup_blockops), %o2
- or %o2, %lo(tsunami_setup_blockops), %o2
- ld [%o1], %o4
-1: add %o1, 4, %o1
- st %o4, [%o0]
- add %o0, 4, %o0
- cmp %o1, %o2
- bne 1b
- ld [%o1], %o4
- sta %g0, [%g0] ASI_M_IC_FLCLEAR
- sta %g0, [%g0] ASI_M_DC_FLCLEAR
- retl
- nop
diff --git a/arch/sparc/mm/viking.S b/arch/sparc/mm/viking.S
deleted file mode 100644
index 48f062de7a7f..000000000000
--- a/arch/sparc/mm/viking.S
+++ /dev/null
@@ -1,284 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * viking.S: High speed Viking cache/mmu operations
- *
- * Copyright (C) 1997 Eddie C. Dost ([email protected])
- * Copyright (C) 1997,1998,1999 Jakub Jelinek ([email protected])
- * Copyright (C) 1999 Pavel Semerad ([email protected])
- */
-
-#include <asm/ptrace.h>
-#include <asm/psr.h>
-#include <asm/asm-offsets.h>
-#include <asm/asi.h>
-#include <asm/mxcc.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pgtsrmmu.h>
-#include <asm/viking.h>
-
-#ifdef CONFIG_SMP
- .data
- .align 4
-sun4dsmp_flush_tlb_spin:
- .word 0
-#endif
-
- .text
- .align 4
-
- .globl viking_flush_cache_all, viking_flush_cache_mm
- .globl viking_flush_cache_range, viking_flush_cache_page
- .globl viking_flush_page, viking_mxcc_flush_page
- .globl viking_flush_page_for_dma, viking_flush_page_to_ram
- .globl viking_flush_sig_insns
- .globl viking_flush_tlb_all, viking_flush_tlb_mm
- .globl viking_flush_tlb_range, viking_flush_tlb_page
-
-viking_flush_page:
- sethi %hi(PAGE_OFFSET), %g2
- sub %o0, %g2, %g3
- srl %g3, 12, %g1 ! ppage >> 12
-
- clr %o1 ! set counter, 0 - 127
- sethi %hi(PAGE_OFFSET + PAGE_SIZE - 0x80000000), %o3
- sethi %hi(0x80000000), %o4
- sethi %hi(VIKING_PTAG_VALID), %o5
- sethi %hi(2*PAGE_SIZE), %o0
- sethi %hi(PAGE_SIZE), %g7
- clr %o2 ! block counter, 0 - 3
-5:
- sll %o1, 5, %g4
- or %g4, %o4, %g4 ! 0x80000000 | (set << 5)
-
- sll %o2, 26, %g5 ! block << 26
-6:
- or %g5, %g4, %g5
- ldda [%g5] ASI_M_DATAC_TAG, %g2
- cmp %g3, %g1 ! ptag == ppage?
- bne 7f
- inc %o2
-
- andcc %g2, %o5, %g0 ! ptag VALID?
- be 7f
- add %g4, %o3, %g2 ! (PAGE_OFFSET + PAGE_SIZE) | (set << 5)
- ld [%g2], %g3
- ld [%g2 + %g7], %g3
- add %g2, %o0, %g2
- ld [%g2], %g3
- ld [%g2 + %g7], %g3
- add %g2, %o0, %g2
- ld [%g2], %g3
- ld [%g2 + %g7], %g3
- add %g2, %o0, %g2
- ld [%g2], %g3
- b 8f
- ld [%g2 + %g7], %g3
-
-7:
- cmp %o2, 3
- ble 6b
- sll %o2, 26, %g5 ! block << 26
-
-8: inc %o1
- cmp %o1, 0x7f
- ble 5b
- clr %o2
-
-9: retl
- nop
-
-viking_mxcc_flush_page:
- sethi %hi(PAGE_OFFSET), %g2
- sub %o0, %g2, %g3
- sub %g3, -PAGE_SIZE, %g3 ! ppage + PAGE_SIZE
- sethi %hi(MXCC_SRCSTREAM), %o3 ! assume %hi(MXCC_SRCSTREAM) == %hi(MXCC_DESTSTREAM)
- mov 0x10, %g2 ! set cacheable bit
- or %o3, %lo(MXCC_SRCSTREAM), %o2
- or %o3, %lo(MXCC_DESSTREAM), %o3
- sub %g3, MXCC_STREAM_SIZE, %g3
-6:
- stda %g2, [%o2] ASI_M_MXCC
- stda %g2, [%o3] ASI_M_MXCC
- andncc %g3, PAGE_MASK, %g0
- bne 6b
- sub %g3, MXCC_STREAM_SIZE, %g3
-
-9: retl
- nop
-
-viking_flush_cache_page:
-viking_flush_cache_range:
-#ifndef CONFIG_SMP
- ld [%o0 + VMA_VM_MM], %o0
-#endif
-viking_flush_cache_mm:
-#ifndef CONFIG_SMP
- ld [%o0 + AOFF_mm_context], %g1
- cmp %g1, -1
- bne viking_flush_cache_all
- nop
- b,a viking_flush_cache_out
-#endif
-viking_flush_cache_all:
- WINDOW_FLUSH(%g4, %g5)
-viking_flush_cache_out:
- retl
- nop
-
-viking_flush_tlb_all:
- mov 0x400, %g1
- retl
- sta %g0, [%g1] ASI_M_FLUSH_PROBE
-
-viking_flush_tlb_mm:
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o1
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o1, -1
- be 1f
-#endif
- mov 0x300, %g2
- sta %o1, [%g1] ASI_M_MMUREGS
- sta %g0, [%g2] ASI_M_FLUSH_PROBE
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-#ifndef CONFIG_SMP
-1: retl
- nop
-#endif
-
-viking_flush_tlb_range:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be 2f
-#endif
- sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
- sta %o3, [%g1] ASI_M_MMUREGS
- and %o1, %o4, %o1
- add %o1, 0x200, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-1: sub %o1, %o4, %o1
- cmp %o1, %o2
- blu,a 1b
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-#ifndef CONFIG_SMP
-2: retl
- nop
-#endif
-
-viking_flush_tlb_page:
- ld [%o0 + VMA_VM_MM], %o0
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
-#ifndef CONFIG_SMP
- cmp %o3, -1
- be 1f
-#endif
- and %o1, PAGE_MASK, %o1
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- retl
- sta %g5, [%g1] ASI_M_MMUREGS
-#ifndef CONFIG_SMP
-1: retl
- nop
-#endif
-
-viking_flush_page_to_ram:
-viking_flush_page_for_dma:
-viking_flush_sig_insns:
- retl
- nop
-
-#ifdef CONFIG_SMP
- .globl sun4dsmp_flush_tlb_all, sun4dsmp_flush_tlb_mm
- .globl sun4dsmp_flush_tlb_range, sun4dsmp_flush_tlb_page
-sun4dsmp_flush_tlb_all:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 2f
- mov 0x400, %g1
- sta %g0, [%g1] ASI_M_FLUSH_PROBE
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-2: tst %g5
- bne,a 2b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
-
-sun4dsmp_flush_tlb_mm:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 2f
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + AOFF_mm_context], %o1
- lda [%g1] ASI_M_MMUREGS, %g5
- mov 0x300, %g2
- sta %o1, [%g1] ASI_M_MMUREGS
- sta %g0, [%g2] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-2: tst %g5
- bne,a 2b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
-
-sun4dsmp_flush_tlb_range:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 3f
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + VMA_VM_MM], %o0
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
- sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
- sta %o3, [%g1] ASI_M_MMUREGS
- and %o1, %o4, %o1
- add %o1, 0x200, %o1
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
-2: sub %o1, %o4, %o1
- cmp %o1, %o2
- blu,a 2b
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-3: tst %g5
- bne,a 3b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
-
-sun4dsmp_flush_tlb_page:
- sethi %hi(sun4dsmp_flush_tlb_spin), %g3
-1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- tst %g5
- bne 2f
- mov SRMMU_CTX_REG, %g1
- ld [%o0 + VMA_VM_MM], %o0
- ld [%o0 + AOFF_mm_context], %o3
- lda [%g1] ASI_M_MMUREGS, %g5
- and %o1, PAGE_MASK, %o1
- sta %o3, [%g1] ASI_M_MMUREGS
- sta %g0, [%o1] ASI_M_FLUSH_PROBE
- sta %g5, [%g1] ASI_M_MMUREGS
- retl
- stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
-2: tst %g5
- bne,a 2b
- ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
- b,a 1b
- nop
-#endif
--
2.34.1
Hi Andreas,
On Sat, Mar 09, 2024 at 07:15:21PM +0100, Sam Ravnborg via B4 Relay wrote:
> This is the second attempt to sunset sun4m and sun4d.
> See [1] for the inital attempt.
>
> The sun4m and sun4d parts of the kernel have seen no real interest
> for several years now. Last time a few people surfaced, but it was
> either due to a personal project or for nostalgic reasons.
> It is time to let go and drop the parts of sparc32 that in reality
> are not in use.
>
> LEON from Frontgrade Gaisler is the only real user of sparc32,
> and this patchset reduces sparc32 to what is required by LEON.
>
> The defconfig is first adapted to the one used by Gaisler.
> Then the patches removes sun4m and sun4d specific
> implementations such as small drivers, SMP support, IRQ suppor etc.
>
> Removing sun4m and sun4d support allowed removal of the run time
> patching of the code as well as a lot of assembler code.
> The result is a much cleaner assembler code that is easier to
> understand and thus maintain and extend.
>
> Changes in v2:
> - Rebased on top of Andreas' for-next branch
> - Collected ack's
> - Added patch to remove cpuid patching (Andreas)
> - Run-time testing using qemu (Andreas, Mark Cave-Ayland)
Please let me know if you expect me to rebase this on for-next.
I have not yet tried if there are merge conflicts but can take a look in
a some days if required.
That is assuming you agree with the sunset of the sun platforms...
Sam
On 2024-04-23 20:02, Sam Ravnborg wrote:
> Please let me know if you expect me to rebase this on for-next.
> I have not yet tried if there are merge conflicts but can take a look in
> a some days if required.
My local testing branch for this patchset rebased with trivial fixups,
so no immediate rebase and resubmission is needed. I do run into some
strange problems on SMP with this patchset plus your CAS patchset, that
I do not get when I rebase the Linux patches from our kernel release
that has my CAS patchset. With no CAS at all these things fails even
worse, so do I need one or the other for these tests.
I will need to dig deeper into figuring out the problems seems to be due
to something in any of your two patchsets in themselves or if it is
something else. I do need some additional fixes from our kernel release
for SMP to work properly, so it could also be that there is something
with my combination of your patches and my patches adapted on top of
yours.
There are also some needed fixes for LEON that relies upon code removed
in this patchset. Maybe the best solution for that would be if I submit
those and you then rebase upon them.
> That is assuming you agree with the sunset of the sun platforms...
I do agree with the idea in general, but being busy with other things I
have had little time to dig into this lately.
Thanks,
Andreas
Hi Andreas.
On Fri, Apr 26, 2024 at 06:31:12PM +0200, Andreas Larsson wrote:
> On 2024-04-23 20:02, Sam Ravnborg wrote:
> > Please let me know if you expect me to rebase this on for-next.
> > I have not yet tried if there are merge conflicts but can take a look in
> > a some days if required.
>
> My local testing branch for this patchset rebased with trivial fixups,
> so no immediate rebase and resubmission is needed. I do run into some
> strange problems on SMP with this patchset plus your CAS patchset, that
> I do not get when I rebase the Linux patches from our kernel release
> that has my CAS patchset. With no CAS at all these things fails even
> worse, so do I need one or the other for these tests.
:-(
>
> I will need to dig deeper into figuring out the problems seems to be due
> to something in any of your two patchsets in themselves or if it is
> something else. I do need some additional fixes from our kernel release
> for SMP to work properly, so it could also be that there is something
> with my combination of your patches and my patches adapted on top of
> yours.
>
> There are also some needed fixes for LEON that relies upon code removed
> in this patchset. Maybe the best solution for that would be if I submit
> those and you then rebase upon them.
If you can make LEON stable before starting the code removal that would
be the best way forward. Then it should be easier to identify when
the removal patches breaks things.
With all the surgery I had to do to remove stuff it would have been a
big surprise if it just worked - so it goes as expected. qemu only
verify so much - the real target (and SMP) is way better.
> > That is assuming you agree with the sunset of the sun platforms...
>
> I do agree with the idea in general, but being busy with other things I
> have had little time to dig into this lately.
If this round could be used to stabilize LEON and apply other more
trivial stuff, then I am happy to rebase the "sunset" patchset sometimes
after next -rc1.
I have accumulated a bit more on top of what I already posted, and I
will include a few more patches in the next round.
In other words - take your time!
Sam