The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
Signed-off-by: Neil Armstrong <[email protected]>
---
Neil Armstrong (7):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs
phy: qcom: qmp-pcie: refactor clock register code
phy: qcom: qmp-pcie: register second optional PHY AUX clock
phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY
arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 -
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 -
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +--
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 -
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 -
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 +--
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 104 ++++++++++++++++++---
include/dt-bindings/phy/phy-qcom-qmp.h | 4 +
11 files changed, 129 insertions(+), 64 deletions(-)
---
base-commit: 2e93f143ca010a5013528e1cfdc895f024fe8c21
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <[email protected]>
On Tue, 19 Mar 2024 11:44:26 +0100, Neil Armstrong wrote:
> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
> is muxed & gated then returned to the PHY as an input.
>
> Document the clock IDs to select the PIPE clock or the AUX clock,
> also enforce a second clock-output-names and a #clock-cells value of 1
> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
>
> The PHY driver needs a light refactoring to support a second clock,
> and finally the DT is changed to connect the PHY second clock to the
> corresponding GCC input then drop the dummy fixed rate clock.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> Neil Armstrong (7):
> dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs
> phy: qcom: qmp-pcie: refactor clock register code
> phy: qcom: qmp-pcie: register second optional PHY AUX clock
> phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY
> arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>
> .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++-
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 +-
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 -
> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 -
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +--
> arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 -
> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 -
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 +--
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 104 ++++++++++++++++++---
> include/dt-bindings/phy/phy-qcom-qmp.h | 4 +
> 11 files changed, 129 insertions(+), 64 deletions(-)
> ---
> base-commit: 2e93f143ca010a5013528e1cfdc895f024fe8c21
> change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
>
> Best regards,
> --
> Neil Armstrong <[email protected]>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/sm8550-hdk.dtb qcom/sm8550-mtp.dtb qcom/sm8550-qrd.dtb qcom/sm8650-mtp.dtb qcom/sm8650-qrd.dtb' for 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org:
arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: clocks: [[41], [42], [43], [44, 0], [45, 0], [45, 1], [45, 2], [46, 0]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#