Since CannonLake, we've been using the XTAL oscillator as the link clock
source, but since MeteorLake the hardware offers two additional sources:
the audio cardinal clock and the internal audio PLL.
This series adds support for link clock source selection.
Pierre-Louis Bossart (7):
soundwire: cadence: show the bus frequency and frame shape
soundwire: bus: extend base clock checks to 96 MHz
soundwire: intel: add more values for SYNCPRD
soundwire: intel: add support for MeteorLake additional clocks
soundwire: intel_ace2x: move and extend clock selection
soundwire: intel_ace2.x: power-up first before setting SYNCPRD
soundwire: intel_ace2x: set the clock source
drivers/soundwire/bus.c | 12 +++----
drivers/soundwire/cadence_master.c | 6 ++++
drivers/soundwire/intel.c | 43 +++++++++++++++++++----
drivers/soundwire/intel_ace2x.c | 53 +++++++++++++++++++++--------
include/linux/soundwire/sdw_intel.h | 11 ++++--
5 files changed, 96 insertions(+), 29 deletions(-)
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
Starting with MeteorLake, the input frequency to the SoundWire IP can
be 96MHz. The existing code is limited to 24MHz, change accordingly
and move branch after the 32MHz case to avoid issues.
While we're at it, reorder the frequencies by increasing order.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/bus.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c
index 05b2db00d9cd..191e6cc6f962 100644
--- a/drivers/soundwire/bus.c
+++ b/drivers/soundwire/bus.c
@@ -1312,18 +1312,18 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
if (!(19200000 % mclk_freq)) {
mclk_freq = 19200000;
base = SDW_SCP_BASE_CLOCK_19200000_HZ;
- } else if (!(24000000 % mclk_freq)) {
- mclk_freq = 24000000;
- base = SDW_SCP_BASE_CLOCK_24000000_HZ;
- } else if (!(24576000 % mclk_freq)) {
- mclk_freq = 24576000;
- base = SDW_SCP_BASE_CLOCK_24576000_HZ;
} else if (!(22579200 % mclk_freq)) {
mclk_freq = 22579200;
base = SDW_SCP_BASE_CLOCK_22579200_HZ;
+ } else if (!(24576000 % mclk_freq)) {
+ mclk_freq = 24576000;
+ base = SDW_SCP_BASE_CLOCK_24576000_HZ;
} else if (!(32000000 % mclk_freq)) {
mclk_freq = 32000000;
base = SDW_SCP_BASE_CLOCK_32000000_HZ;
+ } else if (!(96000000 % mclk_freq)) {
+ mclk_freq = 24000000;
+ base = SDW_SCP_BASE_CLOCK_24000000_HZ;
} else {
dev_err(&slave->dev,
"Unsupported clock base, mclk %d\n",
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
Starting with MeteorLake, the input to the SoundWire IP can be 24.576
MHz (aka Audio Cardinal Clock) or 96 MHz (Audio PLL).
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
include/linux/soundwire/sdw_intel.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index 00bb22d96ae5..fa40b85d5019 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -34,8 +34,10 @@
/* SYNC */
#define SDW_SHIM_SYNC 0xC
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 (24576 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
+#define SDW_SHIM_SYNC_SYNCPRD_VAL_96 (96000 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
The input clock to the SoundWire IP can be
38.4 MHz (xtal clock source)
24.576 MHz (audio cardinal clock)
96 MHz (internal Audio PLL)
This patch moves the clock selection outside the mutex and add the new
choices for 24.576 and 96 MHz, but doesn't add any functionality.
Follow-up patches will add support for clock selection.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/intel_ace2x.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2x.c
index 8280baa3254b..abdd651a185c 100644
--- a/drivers/soundwire/intel_ace2x.c
+++ b/drivers/soundwire/intel_ace2x.c
@@ -74,20 +74,29 @@ static int intel_link_power_up(struct sdw_intel *sdw)
struct sdw_master_prop *prop = &bus->prop;
u32 *shim_mask = sdw->link_res->shim_mask;
unsigned int link_id = sdw->instance;
+ u32 clock_source;
u32 syncprd;
int ret;
+ if (prop->mclk_freq % 6000000) {
+ if (prop->mclk_freq % 2400000) {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576;
+ clock_source = SDW_SHIM2_MLCS_CARDINAL_CLK;
+ } else {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
+ clock_source = SDW_SHIM2_MLCS_XTAL_CLK;
+ }
+ } else {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96;
+ clock_source = SDW_SHIM2_MLCS_AUDIO_PLL_CLK;
+ }
+
mutex_lock(sdw->link_res->shim_lock);
if (!*shim_mask) {
/* we first need to program the SyncPRD/CPU registers */
dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
- if (prop->mclk_freq % 6000000)
- syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
- else
- syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
-
ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd);
if (ret < 0) {
dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n",
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
In the MeteorLake hardware, the SoundWire link clock can be selected
from the Xtal, audio cardinal clock (24.576 MHz) or the 96 MHz audio
PLL.
This patches add the clock selection in a backwards-compatible manner,
using the ACPI firmware as the source of information and checking its
compatibility with hardware capabilities.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/intel.c | 43 +++++++++++++++++++++++++----
include/linux/soundwire/sdw_intel.h | 5 ++++
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index 1287a325c435..e15666962fe4 100644
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -345,8 +345,10 @@ static int intel_link_power_up(struct sdw_intel *sdw)
u32 spa_mask, cpa_mask;
u32 link_control;
int ret = 0;
+ u32 clock_source;
u32 syncprd;
u32 sync_reg;
+ bool lcap_mlcs;
mutex_lock(sdw->link_res->shim_lock);
@@ -358,12 +360,35 @@ static int intel_link_power_up(struct sdw_intel *sdw)
* is only dependent on the oscillator clock provided to
* the IP, so adjust based on _DSD properties reported in DSDT
* tables. The values reported are based on either 24MHz
- * (CNL/CML) or 38.4 MHz (ICL/TGL+).
+ * (CNL/CML) or 38.4 MHz (ICL/TGL+). On MeteorLake additional
+ * frequencies are available with the MLCS clock source selection.
*/
- if (prop->mclk_freq % 6000000)
- syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
- else
- syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
+ lcap_mlcs = intel_readl(shim, SDW_SHIM_LCAP) & SDW_SHIM_LCAP_MLCS_MASK;
+
+ if (prop->mclk_freq % 6000000) {
+ if (prop->mclk_freq % 2400000) {
+ if (lcap_mlcs) {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576;
+ clock_source = SDW_SHIM_MLCS_CARDINAL_CLK;
+ } else {
+ dev_err(sdw->cdns.dev, "%s: invalid clock configuration, mclk %d lcap_mlcs %d\n",
+ __func__, prop->mclk_freq, lcap_mlcs);
+ ret = -EINVAL;
+ goto out;
+ }
+ } else {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
+ clock_source = SDW_SHIM_MLCS_XTAL_CLK;
+ }
+ } else {
+ if (lcap_mlcs) {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96;
+ clock_source = SDW_SHIM_MLCS_AUDIO_PLL_CLK;
+ } else {
+ syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
+ clock_source = SDW_SHIM_MLCS_XTAL_CLK;
+ }
+ }
if (!*shim_mask) {
dev_dbg(sdw->cdns.dev, "powering up all links\n");
@@ -403,6 +428,13 @@ static int intel_link_power_up(struct sdw_intel *sdw)
"Failed to set SHIM_SYNC: %d\n", ret);
goto out;
}
+
+ /* update link clock if needed */
+ if (lcap_mlcs) {
+ link_control = intel_readl(shim, SDW_SHIM_LCTL);
+ u32p_replace_bits(&link_control, clock_source, SDW_SHIM_LCTL_MLCS_MASK);
+ intel_writel(shim, SDW_SHIM_LCTL, link_control);
+ }
}
*shim_mask |= BIT(link_id);
@@ -1062,4 +1094,3 @@ const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops = {
.sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
};
EXPORT_SYMBOL_NS(sdw_intel_cnl_hw_ops, SOUNDWIRE_INTEL);
-
diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h
index fa40b85d5019..8e78417156e3 100644
--- a/include/linux/soundwire/sdw_intel.h
+++ b/include/linux/soundwire/sdw_intel.h
@@ -22,6 +22,7 @@
/* LCAP */
#define SDW_SHIM_LCAP 0x0
#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
+#define SDW_SHIM_LCAP_MLCS_MASK BIT(8)
/* LCTL */
#define SDW_SHIM_LCTL 0x4
@@ -30,6 +31,10 @@
#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
#define SDW_SHIM_LCTL_CPA BIT(8)
#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
+#define SDW_SHIM_LCTL_MLCS_MASK GENMASK(29, 27)
+#define SDW_SHIM_MLCS_XTAL_CLK 0x0
+#define SDW_SHIM_MLCS_CARDINAL_CLK 0x1
+#define SDW_SHIM_MLCS_AUDIO_PLL_CLK 0x2
/* SYNC */
#define SDW_SHIM_SYNC 0xC
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
The existing sequence is fine if we want to only use the xtal
clock. However if we want to select the clock, we first need to
power-up, then select the clock and last set the SYNCPRD.
This patch first modifies the order, we will add the clock selection
as a follow-up.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/intel_ace2x.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2x.c
index abdd651a185c..d8ae05cf3d57 100644
--- a/drivers/soundwire/intel_ace2x.c
+++ b/drivers/soundwire/intel_ace2x.c
@@ -93,6 +93,13 @@ static int intel_link_power_up(struct sdw_intel *sdw)
mutex_lock(sdw->link_res->shim_lock);
+ ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id);
+ if (ret < 0) {
+ dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n",
+ __func__, ret);
+ goto out;
+ }
+
if (!*shim_mask) {
/* we first need to program the SyncPRD/CPU registers */
dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
@@ -103,16 +110,7 @@ static int intel_link_power_up(struct sdw_intel *sdw)
__func__, ret);
goto out;
}
- }
- ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id);
- if (ret < 0) {
- dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n",
- __func__, ret);
- goto out;
- }
-
- if (!*shim_mask) {
/* SYNCPU will change once link is active */
ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus);
if (ret < 0) {
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
Insert clock setup after power-up and before setting up the SYNCPRD,
per hardware recommendations.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/intel_ace2x.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2x.c
index d8ae05cf3d57..43a348db83bf 100644
--- a/drivers/soundwire/intel_ace2x.c
+++ b/drivers/soundwire/intel_ace2x.c
@@ -33,6 +33,20 @@ static void intel_shim_vs_init(struct sdw_intel *sdw)
usleep_range(10, 15);
}
+static void intel_shim_vs_set_clock_source(struct sdw_intel *sdw, u32 source)
+{
+ void __iomem *shim_vs = sdw->link_res->shim_vs;
+ u32 val;
+
+ val = intel_readl(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL);
+
+ u32p_replace_bits(&val, source, SDW_SHIM2_INTEL_VS_LVSCTL_MLCS);
+
+ intel_writel(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL, val);
+
+ dev_dbg(sdw->cdns.dev, "clock source %d LVSCTL %#x\n", source, val);
+}
+
static int intel_shim_check_wake(struct sdw_intel *sdw)
{
void __iomem *shim_vs;
@@ -100,6 +114,8 @@ static int intel_link_power_up(struct sdw_intel *sdw)
goto out;
}
+ intel_shim_vs_set_clock_source(sdw, clock_source);
+
if (!*shim_mask) {
/* we first need to program the SyncPRD/CPU registers */
dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n");
--
2.34.1
From: Pierre-Louis Bossart <[email protected]>
This log is useful when trying different configurations, specifically
to make sure ACPI initrd overrides have been taken into account.
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Reviewed-by: Rander Wang <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
---
drivers/soundwire/cadence_master.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c
index c2c1463a5c53..74da99034dab 100644
--- a/drivers/soundwire/cadence_master.c
+++ b/drivers/soundwire/cadence_master.c
@@ -1319,6 +1319,12 @@ static void cdns_init_clock_ctrl(struct sdw_cdns *cdns)
u32 ssp_interval;
int divider;
+ dev_dbg(cdns->dev, "mclk %d max %d row %d col %d\n",
+ prop->mclk_freq,
+ prop->max_clk_freq,
+ prop->default_row,
+ prop->default_col);
+
/* Set clock divider */
divider = (prop->mclk_freq / prop->max_clk_freq) - 1;
--
2.34.1
On Tue, 26 Mar 2024 09:20:23 +0000, Bard Liao wrote:
> Since CannonLake, we've been using the XTAL oscillator as the link clock
> source, but since MeteorLake the hardware offers two additional sources:
> the audio cardinal clock and the internal audio PLL.
>
> This series adds support for link clock source selection.
>
> Pierre-Louis Bossart (7):
> soundwire: cadence: show the bus frequency and frame shape
> soundwire: bus: extend base clock checks to 96 MHz
> soundwire: intel: add more values for SYNCPRD
> soundwire: intel: add support for MeteorLake additional clocks
> soundwire: intel_ace2x: move and extend clock selection
> soundwire: intel_ace2.x: power-up first before setting SYNCPRD
> soundwire: intel_ace2x: set the clock source
>
> [...]
Applied, thanks!
[1/7] soundwire: cadence: show the bus frequency and frame shape
commit: 8292c815bbb71ea9f86331c3d07d2b9530b93565
[2/7] soundwire: bus: extend base clock checks to 96 MHz
commit: 7eca9c722eed80f76cd272a52d9fa98f89322e7e
[3/7] soundwire: intel: add more values for SYNCPRD
commit: d0a69cd0369a390cc1c100e52e78a273695a170c
[4/7] soundwire: intel: add support for MeteorLake additional clocks
commit: 09ee49e3de6bcecc57028682c673d180ec2d436b
[5/7] soundwire: intel_ace2x: move and extend clock selection
commit: 769d69812b42f0fc710bdf16b9f3979c959910b7
[6/7] soundwire: intel_ace2.x: power-up first before setting SYNCPRD
commit: a206d2e3409f58733c9097523e5f62ebb920fbbf
[7/7] soundwire: intel_ace2x: set the clock source
commit: 5b3f661b244973374626f7cc798cea91345786e8
Best regards,
--
~Vinod