2024-04-03 20:11:30

by Prabhakar

Subject: [PATCH] clk: renesas: r9a07g043: Add clock and reset entry for PLIC

From: Lad Prabhakar <[email protected]>

Add the missing clock and reset entry for PLIC. Also add
R9A07G043_NCEPLIC_ACLK to critical clocks list.

Fixes: b3e77da00f1b ("riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC")
Signed-off-by: Lad Prabhakar <[email protected]>
---
drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index e36d2ec2c0f5..16acc95f3c62 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -280,6 +280,10 @@ static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x5a8, 1),
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
0x5ac, 0),
+#ifdef CONFIG_RISCV
+ DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
+ 0x608, 0),
+#endif
};

static const struct rzg2l_reset r9a07g043_resets[] = {
@@ -338,6 +342,10 @@ static const struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
+#ifdef CONFIG_RISCV
+ DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),
+#endif
+
};

static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
@@ -347,6 +355,7 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
#endif
#ifdef CONFIG_RISCV
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
+ MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,
#endif
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
};
--
2.34.1

2024-04-18 14:57:12

by Geert Uytterhoeven

Subject: Re: [PATCH] clk: renesas: r9a07g043: Add clock and reset entry for PLIC

Hi Prabhakar,

On Thu, Apr 18, 2024 at 4:53 PM Geert Uytterhoeven <[email protected]> wrote:
> On Wed, Apr 3, 2024 at 10:11 PM Prabhakar <prabhakar.csengg@gmailcom> wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Add the missing clock and reset entry for PLIC. Also add
> > R9A07G043_NCEPLIC_ACLK to critical clocks list.
> >
> > Fixes: b3e77da00f1b ("riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC")

That is not the correct commit, I'll replace it by
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
while applying.

> > Signed-off-by: Lad Prabhakar <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> i.e. will queue in renesas-clk for v6.10.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2024-04-18 15:23:55

by Geert Uytterhoeven

Subject: Re: [PATCH] clk: renesas: r9a07g043: Add clock and reset entry for PLIC

On Wed, Apr 3, 2024 at 10:11 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Add the missing clock and reset entry for PLIC. Also add
> R9A07G043_NCEPLIC_ACLK to critical clocks list.
>
> Fixes: b3e77da00f1b ("riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC")
> Signed-off-by: Lad Prabhakar <[email protected]>

Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-clk for v6.10.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds