The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver. This adds the define for it.
Signed-off-by: Sascha Hauer <[email protected]>
---
include/dt-bindings/clock/rk3568-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
index d29890865150d..5263085c5b238 100644
--- a/include/dt-bindings/clock/rk3568-cru.h
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -78,6 +78,7 @@
#define CPLL_333M 9
#define ARMCLK 10
#define USB480M 11
+#define USB480M_PHY 12
#define ACLK_CORE_NIU2BUS 18
#define CLK_CORE_PVTM 19
#define CLK_CORE_PVTM_CORE 20
--
2.39.2
On 05/04/2024 09:38, Sascha Hauer wrote:
> The USB480M clock can source from a MUX that selects the clock to come
> from either of the USB-phy internal 480MHz PLLs. These clocks are
> provided by the USB phy driver. This adds the define for it.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> include/dt-bindings/clock/rk3568-cru.h | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof