2024-04-08 13:43:05

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 0/9] Add multiport support for DWC3 controllers

Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.

This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.

Changes have been tested on QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).

Changes in v20:
Modified return check in get_num_ports call.
Code re-verified internally and added Bjorn.A RB Tag in patch (2/9)
from internal review.

Changes in v19:
Replaced IS_ERR(ptr) with a NULL check.
Modified name of function reading the port num in core file.

Changes in v18:
Updated variable names in patch-7 for setup_port_irq and
find_num_ports calls.

Changes in v17:
Modified DT handling patch by checking if dp_hs_phy_1 is present
or not and then going for DT parsing.

Changes in v16:
Removing ACPI has simplified the interrupt reading in wrapper. Also
the logic to find number of ports is based on dp_hs_phy interrupt check
in DT. Enabling and disabling interrupts is now done per port. Added
info on power event irq in commit message.

Changes in v15:
Added minItems property in qcom,dwc3 bindings as suggested by Rob.
Retained all RB's/ACK's got in v14.

Changes in v14:
Moved wrapper binding update to 5th patch in the series as it deals
with only wakeup and not enumeration. The first part of the series
deals with enumeration and the next part deals with wakeup.
Updated commit text for wrapper driver patches.
Added error checks in get_port_index and setup_irq call which were
missing in v13.
Added SOB and CDB tags appropriately for the patches.
Rebased code on top of latest usb next.
DT changes have been removed and will be sent as a separate series.

Changes in v13:
This series is a subset of patches in v11 as the first 3 patches in v11
have been mereged into usb-next.
Moved dr_mode property from platform specific files to common sc8280xp DT.
Fixed function call wrapping, added comments and replaced #defines with
enum in dwc3-qcom for identifying IRQ index appropriately.
Fixed nitpicks pointed out in v11 for suspend-resume handling.
Added reported-by tag for phy refactoring patch as a compile error was
found by kernel test bot [1].
Removed reviewed-by tag of maintainer for phy refactoring patch as a minor
change of increasing phy-names array size by 2-bytes was done to fix
compilation issue mentioned in [1].

Changes in v12:
Pushed as a subset of acked but no-yet-merged patches of v11 with intent
of making rebase of other patches easy. Active reviewers from community
suggested that it would be better to push the whole series in one go as it
would give good clarity and context for all the patches in the series.
So pushed v13 for the same addressing comments received in v11.

Changes in v11:
Implemented port_count calculation by reading interrupt-names from DT.
Refactored IRQ handling in dwc3-qcom.
Moving of macros to xhci-ext-caps.h made as a separate patch.
Names of interrupts to be displayed on /proc/interrupts set to the ones
present in DT.

Changes in v10:
Refactored phy init/exit/power-on/off functions in dwc3 core
Refactored dwc3-qcom irq registration and handling
Implemented wakeup for multiport irq's
Moved few macros from xhci.h to xhci-ext-caps.h
Fixed nits pointed out in v9
Fixed Co-developed by and SOB tags in patches 5 and 11

Changes in v9:
Added IRQ support for DP/DM/SS MP Irq's of SC8280
Refactored code to read port count by accessing xhci registers

Changes in v8:
Reorganised code in patch-5
Fixed nitpicks in code according to comments received on v7
Fixed indentation in DT patches
Added drive strength for pinctrl nodes in SA8295 DT

Changes in v7:
Added power event irq's for Multiport controller.
Udpated commit text for patch-9 (adding DT changes for enabling first
port of multiport controller on sa8540-ride).
Fixed check-patch warnings for driver code.
Fixed DT binding errors for changes in snps,dwc3.yaml
Reabsed code on top of usb-next

Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.

Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.

Changes in RFC v4:
Added DT support for SA8295p.

Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.

Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy
and num_usb3_phy.
Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.
In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.

Tested enumeration interrupt registration on Tertiary controller of
SA8295 ADP:

/ # lsusb
Bus 001 Device 001: ID 1d6b:0002
Bus 002 Device 001: ID 1d6b:0003
Bus 001 Device 002: ID 046d:c06a
/ #
/ # dmesg | grep ports
[ 0.066250] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.154668] dwc3 a400000.usb: K: hs-ports: 4 ss-ports: 2
[ 0.223137] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.1 Enhanced SuperSpeed
[ 0.227795] hub 1-0:1.0: 4 ports detected
[ 0.233724] hub 2-0:1.0: 2 ports detected

Tested interrupt registration for all 4 ports of SA8295 ADP:

/ # cat /proc/interrupts |grep phy
162: 0 0 0 0 0 0 0 0 PDC 127 Edge dp_hs_phy_1
163: 0 0 0 0 0 0 0 0 PDC 129 Edge dp_hs_phy_2
164: 0 0 0 0 0 0 0 0 PDC 131 Edge dp_hs_phy_3
165: 0 0 0 0 0 0 0 0 PDC 133 Edge dp_hs_phy_4
166: 0 0 0 0 0 0 0 0 PDC 126 Edge dm_hs_phy_1
167: 0 0 0 0 0 0 0 0 PDC 16 Level ss_phy_1
168: 0 0 0 0 0 0 0 0 PDC 128 Edge dm_hs_phy_2
169: 0 0 0 0 0 0 0 0 PDC 17 Level ss_phy_2
170: 0 0 0 0 0 0 0 0 PDC 130 Edge dm_hs_phy_3
171: 0 0 0 0 0 0 0 0 PDC 132 Edge dm_hs_phy_4
173: 0 0 0 0 0 0 0 0 PDC 14 Edge dp_hs_phy_irq
174: 0 0 0 0 0 0 0 0 PDC 15 Edge dm_hs_phy_irq
175: 0 0 0 0 0 0 0 0 PDC 138 Level ss_phy_irq

Tested working of ADB on SM8550 MTP.

Links to previous versions:
Link to v19: https://lore.kernel.org/all/[email protected]/
Link to v18: https://lore.kernel.org/all/[email protected]/
Link to v17: https://lore.kernel.org/all/[email protected]/
Link to v16: https://lore.kernel.org/all/[email protected]/
Link to v15: https://lore.kernel.org/all/[email protected]/
Link to v14: https://lore.kernel.org/all/[email protected]/
Link to v13: https://lore.kernel.org/all/[email protected]/
Link to v12: https://lore.kernel.org/all/[email protected]/
Link to v11: https://lore.kernel.org/all/[email protected]/
Link to v10: https://lore.kernel.org/all/[email protected]/
Link to v9: https://lore.kernel.org/all/[email protected]/
Link to v8: https://lore.kernel.org/all/[email protected]/
Link to v7: https://lore.kernel.org/all/[email protected]/
Link to v6: https://lore.kernel.org/all/[email protected]/
Link to v5: https://lore.kernel.org/all/[email protected]/
Link to RFC v4: https://lore.kernel.org/all/[email protected]/
Link to RFC v3: https://lore.kernel.org/all/[email protected]/#r
Link to RFC v2: https://lore.kernel.org/all/[email protected]/#r

Krishna Kurapati (9):
dt-bindings: usb: Add bindings for multiport properties on DWC3
controller
usb: dwc3: core: Access XHCI address space temporarily to read port
info
usb: dwc3: core: Skip setting event buffers for host only controllers
usb: dwc3: core: Refactor PHY logic to support Multiport Controller
dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
usb: dwc3: qcom: Add helper function to request wakeup interrupts
usb: dwc3: qcom: Refactor IRQ handling in glue driver
usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
usb: dwc3: qcom: Add multiport suspend/resume support for wrapper

.../devicetree/bindings/usb/qcom,dwc3.yaml | 34 ++
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
drivers/usb/dwc3/core.c | 325 +++++++++++++-----
drivers/usb/dwc3/core.h | 19 +-
drivers/usb/dwc3/drd.c | 15 +-
drivers/usb/dwc3/dwc3-qcom.c | 251 +++++++++-----
6 files changed, 482 insertions(+), 175 deletions(-)

--
2.34.1



2024-04-08 14:04:38

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 3/9] usb: dwc3: core: Skip setting event buffers for host only controllers

On some SoC's like SA8295P where the tertiary controller is host-only
capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
Trying to access them leads to a crash.

For DRD/Peripheral supported controllers, event buffer setup is done
again in gadget_pullup. Skip setup or cleanup of event buffers if
controller is host-only capable.

Suggested-by: Johan Hovold <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
Acked-by: Thinh Nguyen <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
---
drivers/usb/dwc3/core.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ddab30531f8a..1a3d8a9beea8 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -486,6 +486,13 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc)
static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
{
struct dwc3_event_buffer *evt;
+ unsigned int hw_mode;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ dwc->ev_buf = NULL;
+ return 0;
+ }

evt = dwc3_alloc_one_event_buffer(dwc, length);
if (IS_ERR(evt)) {
@@ -507,6 +514,9 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc)
{
struct dwc3_event_buffer *evt;

+ if (!dwc->ev_buf)
+ return 0;
+
evt = dwc->ev_buf;
evt->lpos = 0;
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
@@ -524,6 +534,9 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
struct dwc3_event_buffer *evt;

+ if (!dwc->ev_buf)
+ return;
+
evt = dwc->ev_buf;

evt->lpos = 0;
--
2.34.1


2024-04-08 14:07:15

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 1/9] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller

Add bindings to indicate properties required to support multiport
on Synopsys DWC3 controller.

Signed-off-by: Krishna Kurapati <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index 203a1eb66691..bfac0a37d0e4 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -85,15 +85,16 @@ properties:

phys:
minItems: 1
- maxItems: 2
+ maxItems: 8

phy-names:
minItems: 1
- maxItems: 2
- items:
- enum:
- - usb2-phy
- - usb3-phy
+ maxItems: 8
+ oneOf:
+ - items:
+ enum: [ usb2-phy, usb3-phy ]
+ - items:
+ pattern: "^usb[23]-[0-3]$"

power-domains:
description:
--
2.34.1


2024-04-08 14:08:44

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 2/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

All DWC3 Multi Port controllers that exist today only support host mode.
Temporarily map XHCI address space for host-only controllers and parse
XHCI Extended Capabilities registers to read number of usb2 ports and
usb3 ports present on multiport controller. Each USB Port is at least HS
capable.

The port info for usb2 and usb3 phy are identified as num_usb2_ports
and num_usb3_ports. The intention is as follows:

Wherever we need to perform phy operations like:

LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}

If number of usb2 ports is 3, loop can go from index 0-2 for
usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
if the first 2 ports are SS capable or some other ports like (2 and 3)
are SS capable. So instead, num_usb2_ports is used to loop around all
phy's (both hs and ss) for performing phy operations. If any
usb3_generic_phy turns out to be NULL, phy operation just bails out.
num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.

Signed-off-by: Krishna Kurapati <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
---
drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 5 ++++
2 files changed, 66 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 31684cdaaae3..ddab30531f8a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -39,6 +39,7 @@
#include "io.h"

#include "debug.h"
+#include "../host/xhci-ext-caps.h"

#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */

@@ -1881,10 +1882,56 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
return 0;
}

+static int dwc3_get_num_ports(struct dwc3 *dwc)
+{
+ void __iomem *base;
+ u8 major_revision;
+ u32 offset;
+ u32 val;
+
+ /*
+ * Remap xHCI address space to access XHCI ext cap regs since it is
+ * needed to get information on number of ports present.
+ */
+ base = ioremap(dwc->xhci_resources[0].start,
+ resource_size(&dwc->xhci_resources[0]));
+ if (!base)
+ return -ENOMEM;
+
+ offset = 0;
+ do {
+ offset = xhci_find_next_ext_cap(base, offset,
+ XHCI_EXT_CAPS_PROTOCOL);
+ if (!offset)
+ break;
+
+ val = readl(base + offset);
+ major_revision = XHCI_EXT_PORT_MAJOR(val);
+
+ val = readl(base + offset + 0x08);
+ if (major_revision == 0x03) {
+ dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
+ } else if (major_revision <= 0x02) {
+ dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
+ } else {
+ dev_warn(dwc->dev, "unrecognized port major revision %d\n",
+ major_revision);
+ }
+ } while (1);
+
+ dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
+ dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+ iounmap(base);
+
+ return 0;
+}
+
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res, dwc_res;
+ unsigned int hw_mode;
void __iomem *regs;
struct dwc3 *dwc;
int ret;
@@ -1968,6 +2015,20 @@ static int dwc3_probe(struct platform_device *pdev)
goto err_disable_clks;
}

+ /*
+ * Currently only DWC3 controllers that are host-only capable
+ * can have more than one port.
+ */
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_get_num_ports(dwc);
+ if (ret)
+ goto err_disable_clks;
+ } else {
+ dwc->num_usb2_ports = 1;
+ dwc->num_usb3_ports = 1;
+ }
+
spin_lock_init(&dwc->lock);
mutex_init(&dwc->mutex);

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7e80dd3d466b..341e4c73cb2e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1039,6 +1039,8 @@ struct dwc3_scratchpad_array {
* @usb3_phy: pointer to USB3 PHY
* @usb2_generic_phy: pointer to USB2 PHY
* @usb3_generic_phy: pointer to USB3 PHY
+ * @num_usb2_ports: number of USB2 ports
+ * @num_usb3_ports: number of USB3 ports
* @phys_ready: flag to indicate that PHYs are ready
* @ulpi: pointer to ulpi interface
* @ulpi_ready: flag to indicate that ULPI is initialized
@@ -1187,6 +1189,9 @@ struct dwc3 {
struct phy *usb2_generic_phy;
struct phy *usb3_generic_phy;

+ u8 num_usb2_ports;
+ u8 num_usb3_ports;
+
bool phys_ready;

struct ulpi *ulpi;
--
2.34.1


2024-04-08 14:09:53

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 4/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

Currently the DWC3 driver supports only single port controller
which requires at least one HS PHY and at most one SS PHY.

But the DWC3 USB controller can be connected to multiple ports and
each port can have their own PHYs. Each port of the multiport
controller can either be HS+SS capable or HS only capable
Proper quantification of them is required to modify GUSB2PHYCFG
and GUSB3PIPECTL registers appropriately.

Add support for detecting, obtaining and configuring PHYs supported
by a multiport controller. Limit support to multiport controllers
with up to four ports for now (e.g. as needed for SC8280XP).

Signed-off-by: Krishna Kurapati <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---
drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------
drivers/usb/dwc3/core.h | 14 ++-
drivers/usb/dwc3/drd.c | 15 ++-
3 files changed, 193 insertions(+), 87 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 1a3d8a9beea8..1f4f228c970b 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -124,6 +124,7 @@ static void __dwc3_set_mode(struct work_struct *work)
int ret;
u32 reg;
u32 desired_dr_role;
+ int i;

mutex_lock(&dwc->mutex);
spin_lock_irqsave(&dwc->lock, flags);
@@ -201,8 +202,10 @@ static void __dwc3_set_mode(struct work_struct *work)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }
if (dwc->dis_split_quirk) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
reg |= DWC3_GUCTL3_SPLITDISABLE;
@@ -217,8 +220,8 @@ static void __dwc3_set_mode(struct work_struct *work)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);

ret = dwc3_gadget_init(dwc);
if (ret)
@@ -589,22 +592,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
return ret;
}

-/**
- * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- *
- * Returns 0 on success. The USB PHY interfaces are configured but not
- * initialized. The PHY interfaces and the PHYs get initialized together with
- * the core in dwc3_core_init.
- */
-static int dwc3_phy_setup(struct dwc3 *dwc)
+static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
{
unsigned int hw_mode;
u32 reg;

hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);

- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));

/*
* Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -659,9 +654,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_del_phy_power_chg_quirk)
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;

- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);

- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ return 0;
+}
+
+static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
+{
+ unsigned int hw_mode;
+ u32 reg;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));

/* Select the HS PHY interface */
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -673,7 +678,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
} else if (dwc->hsphy_interface &&
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
} else {
/* Relying on default value. */
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
@@ -740,7 +745,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->ulpi_ext_vbus_drv)
reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;

- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
+
+ return 0;
+}
+
+/**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ *
+ * Returns 0 on success. The USB PHY interfaces are configured but not
+ * initialized. The PHY interfaces and the PHYs get initialized together with
+ * the core in dwc3_core_init.
+ */
+static int dwc3_phy_setup(struct dwc3 *dwc)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ ret = dwc3_ss_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = dwc3_hs_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }

return 0;
}
@@ -748,23 +781,32 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
static int dwc3_phy_init(struct dwc3 *dwc)
{
int ret;
+ int i;
+ int j;

usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);

- ret = phy_init(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err_shutdown_usb3_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_init(dwc->usb2_generic_phy[i]);
+ if (ret < 0)
+ goto err_exit_phy;

- ret = phy_init(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err_exit_usb2_phy;
+ ret = phy_init(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ phy_exit(dwc->usb2_generic_phy[i]);
+ goto err_exit_phy;
+ }
+ }

return 0;

-err_exit_usb2_phy:
- phy_exit(dwc->usb2_generic_phy);
-err_shutdown_usb3_phy:
+err_exit_phy:
+ for (j = i - 1; j >= 0; j--) {
+ phy_exit(dwc->usb3_generic_phy[j]);
+ phy_exit(dwc->usb2_generic_phy[j]);
+ }
+
usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);

@@ -773,8 +815,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)

static void dwc3_phy_exit(struct dwc3 *dwc)
{
- phy_exit(dwc->usb3_generic_phy);
- phy_exit(dwc->usb2_generic_phy);
+ int i;
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_exit(dwc->usb3_generic_phy[i]);
+ phy_exit(dwc->usb2_generic_phy[i]);
+ }

usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);
@@ -783,23 +829,32 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
static int dwc3_phy_power_on(struct dwc3 *dwc)
{
int ret;
+ int i;
+ int j;

usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);

- ret = phy_power_on(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err_suspend_usb3_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_power_on(dwc->usb2_generic_phy[i]);
+ if (ret < 0)
+ goto err_power_off_phy;

- ret = phy_power_on(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err_power_off_usb2_phy;
+ ret = phy_power_on(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ goto err_power_off_phy;
+ }
+ }

return 0;

-err_power_off_usb2_phy:
- phy_power_off(dwc->usb2_generic_phy);
-err_suspend_usb3_phy:
+err_power_off_phy:
+ for (j = i - 1; j >= 0; j--) {
+ phy_power_off(dwc->usb3_generic_phy[j]);
+ phy_power_off(dwc->usb2_generic_phy[j]);
+ }
+
usb_phy_set_suspend(dwc->usb3_phy, 1);
usb_phy_set_suspend(dwc->usb2_phy, 1);

@@ -808,8 +863,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)

static void dwc3_phy_power_off(struct dwc3 *dwc)
{
- phy_power_off(dwc->usb3_generic_phy);
- phy_power_off(dwc->usb2_generic_phy);
+ int i;
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_power_off(dwc->usb3_generic_phy[i]);
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ }

usb_phy_set_suspend(dwc->usb3_phy, 1);
usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -1201,6 +1260,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
unsigned int hw_mode;
u32 reg;
int ret;
+ int i;

hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);

@@ -1244,15 +1304,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
if (!dwc->dis_u3_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
- reg |= DWC3_GUSB3PIPECTL_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
+ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
+ }
}

if (!dwc->dis_u2_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
}
}

@@ -1372,7 +1436,9 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
struct device_node *node = dev->of_node;
+ char phy_name[9];
int ret;
+ int i;

if (node) {
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
@@ -1398,22 +1464,36 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
return dev_err_probe(dev, ret, "no usb3 phy configured\n");
}

- dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(dwc->usb2_generic_phy)) {
- ret = PTR_ERR(dwc->usb2_generic_phy);
- if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb2_generic_phy = NULL;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ if (dwc->num_usb2_ports == 1)
+ sprintf(phy_name, "usb2-phy");
else
- return dev_err_probe(dev, ret, "no usb2 phy configured\n");
- }
+ sprintf(phy_name, "usb2-%d", i);
+
+ dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb2_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb2_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb2_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
+ phy_name);
+ }

- dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
- if (IS_ERR(dwc->usb3_generic_phy)) {
- ret = PTR_ERR(dwc->usb3_generic_phy);
- if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb3_generic_phy = NULL;
+ if (dwc->num_usb2_ports == 1)
+ sprintf(phy_name, "usb3-phy");
else
- return dev_err_probe(dev, ret, "no usb3 phy configured\n");
+ sprintf(phy_name, "usb3-%d", i);
+
+ dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb3_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb3_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb3_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
+ phy_name);
+ }
}

return 0;
@@ -1423,6 +1503,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
int ret;
+ int i;

switch (dwc->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
@@ -1430,8 +1511,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);

ret = dwc3_gadget_init(dwc);
if (ret)
@@ -1442,8 +1523,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }

ret = dwc3_host_init(dwc);
if (ret)
@@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc)

iounmap(base);

+ if (dwc->num_usb2_ports > DWC3_MAX_PORTS ||
+ dwc->num_usb3_ports > DWC3_MAX_PORTS)
+ return -ENOMEM;
+
return 0;
}

@@ -2174,6 +2261,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
{
unsigned long flags;
u32 reg;
+ int i;

switch (dwc->current_dr_role) {
case DWC3_GCTL_PRTCAP_DEVICE:
@@ -2192,17 +2280,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
/* Let controller to suspend HSPHY before PHY driver suspends */
if (dwc->dis_u2_susphy_quirk ||
dwc->dis_enblslpm_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
- DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
+ DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }

/* Give some time for USB2 PHY to suspend */
usleep_range(5000, 6000);
}

- phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* do nothing during runtime_suspend */
@@ -2232,6 +2324,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
unsigned long flags;
int ret;
u32 reg;
+ int i;

switch (dwc->current_dr_role) {
case DWC3_GCTL_PRTCAP_DEVICE:
@@ -2251,17 +2344,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
break;
}
/* Restore GUSB2PHYCFG bits that were modified in suspend */
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- if (dwc->dis_u2_susphy_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ if (dwc->dis_u2_susphy_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

- if (dwc->dis_enblslpm_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+ if (dwc->dis_enblslpm_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }

- phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* nothing to do on runtime_resume */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 341e4c73cb2e..df2e111aa848 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -33,6 +33,12 @@

#include <linux/power_supply.h>

+/*
+ * Maximum number of ports currently supported for multiport
+ * controllers.
+ */
+#define DWC3_MAX_PORTS 4
+
#define DWC3_MSG_MAX 500

/* Global constants */
@@ -1037,8 +1043,8 @@ struct dwc3_scratchpad_array {
* @usb_psy: pointer to power supply interface.
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
- * @usb2_generic_phy: pointer to USB2 PHY
- * @usb3_generic_phy: pointer to USB3 PHY
+ * @usb2_generic_phy: pointer to array of USB2 PHYs
+ * @usb3_generic_phy: pointer to array of USB3 PHYs
* @num_usb2_ports: number of USB2 ports
* @num_usb3_ports: number of USB3 ports
* @phys_ready: flag to indicate that PHYs are ready
@@ -1186,8 +1192,8 @@ struct dwc3 {
struct usb_phy *usb2_phy;
struct usb_phy *usb3_phy;

- struct phy *usb2_generic_phy;
- struct phy *usb3_generic_phy;
+ struct phy *usb2_generic_phy[DWC3_MAX_PORTS];
+ struct phy *usb3_generic_phy[DWC3_MAX_PORTS];

u8 num_usb2_ports;
u8 num_usb3_ports;
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 57ddd2e43022..d76ae676783c 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -331,6 +331,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
u32 reg;
int id;
unsigned long flags;
+ int i;

if (dwc->dr_mode != USB_DR_MODE_OTG)
return;
@@ -386,9 +387,12 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
- PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ if (dwc->usb2_generic_phy[i]) {
+ phy_set_mode(dwc->usb2_generic_phy[i],
+ PHY_MODE_USB_HOST);
+ }
+ }
}
break;
case DWC3_OTG_ROLE_DEVICE:
@@ -400,9 +404,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
- PHY_MODE_USB_DEVICE);
+ if (dwc->usb2_generic_phy[0])
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
dev_err(dwc->dev, "failed to initialize peripheral\n");
--
2.34.1


2024-04-08 14:10:12

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 7/9] usb: dwc3: qcom: Refactor IRQ handling in glue driver

On multiport supported controllers, each port has its own DP/DM
and SS (if super speed capable) interrupts. As per the bindings,
their interrupt names differ from standard ones having "_x" added
as suffix (x indicates port number). Identify from the interrupt
names whether the controller is a multiport controller or not.
Refactor dwc3_qcom_setup_irq() call to parse multiport interrupts
along with non-multiport ones accordingly..

Signed-off-by: Krishna Kurapati <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---
drivers/usb/dwc3/dwc3-qcom.c | 137 ++++++++++++++++++++++++++---------
1 file changed, 103 insertions(+), 34 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index cae5dab8fcfc..35eb338514bc 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -52,6 +52,13 @@
#define APPS_USB_AVG_BW 0
#define APPS_USB_PEAK_BW MBps_to_icc(40)

+struct dwc3_qcom_port {
+ int qusb2_phy_irq;
+ int dp_hs_phy_irq;
+ int dm_hs_phy_irq;
+ int ss_phy_irq;
+};
+
struct dwc3_qcom {
struct device *dev;
void __iomem *qscratch_base;
@@ -59,11 +66,8 @@ struct dwc3_qcom {
struct clk **clks;
int num_clocks;
struct reset_control *resets;
-
- int qusb2_phy_irq;
- int dp_hs_phy_irq;
- int dm_hs_phy_irq;
- int ss_phy_irq;
+ struct dwc3_qcom_port ports[DWC3_MAX_PORTS];
+ u8 num_ports;
enum usb_device_speed usb2_speed;

struct extcon_dev *edev;
@@ -354,24 +358,24 @@ static void dwc3_qcom_disable_wakeup_irq(int irq)

static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
{
- dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->ports[0].qusb2_phy_irq);

if (qcom->usb2_speed == USB_SPEED_LOW) {
- dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq);
} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
(qcom->usb2_speed == USB_SPEED_FULL)) {
- dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq);
} else {
- dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
- dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq);
}

- dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
+ dwc3_qcom_disable_wakeup_irq(qcom->ports[0].ss_phy_irq);
}

static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
{
- dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0);
+ dwc3_qcom_enable_wakeup_irq(qcom->ports[0].qusb2_phy_irq, 0);

/*
* Configure DP/DM line interrupts based on the USB2 device attached to
@@ -383,20 +387,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
*/

if (qcom->usb2_speed == USB_SPEED_LOW) {
- dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
- IRQ_TYPE_EDGE_FALLING);
+ dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq,
+ IRQ_TYPE_EDGE_FALLING);
} else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
(qcom->usb2_speed == USB_SPEED_FULL)) {
- dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
- IRQ_TYPE_EDGE_FALLING);
+ dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq,
+ IRQ_TYPE_EDGE_FALLING);
} else {
- dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
- IRQ_TYPE_EDGE_RISING);
- dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
- IRQ_TYPE_EDGE_RISING);
+ dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq,
+ IRQ_TYPE_EDGE_RISING);
+ dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq,
+ IRQ_TYPE_EDGE_RISING);
}

- dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
+ dwc3_qcom_enable_wakeup_irq(qcom->ports[0].ss_phy_irq, 0);
}

static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
@@ -517,42 +521,107 @@ static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq,
return ret;
}

-static int dwc3_qcom_setup_irq(struct platform_device *pdev)
+static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port_index, bool is_multiport)
{
struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
+ const char *irq_name;
int irq;
int ret;

- irq = platform_get_irq_byname_optional(pdev, "qusb2_phy");
+ if (is_multiport)
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port_index + 1);
+ else
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq");
+ if (!irq_name)
+ return -ENOMEM;
+
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
if (irq > 0) {
- ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy");
+ ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
if (ret)
return ret;
- qcom->qusb2_phy_irq = irq;
+ qcom->ports[port_index].dp_hs_phy_irq = irq;
}

- irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_irq");
+ if (is_multiport)
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port_index + 1);
+ else
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq");
+ if (!irq_name)
+ return -ENOMEM;
+
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
if (irq > 0) {
- ret = dwc3_qcom_request_irq(qcom, irq, "dp_hs_phy_irq");
+ ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
if (ret)
return ret;
- qcom->dp_hs_phy_irq = irq;
+ qcom->ports[port_index].dm_hs_phy_irq = irq;
}

- irq = platform_get_irq_byname_optional(pdev, "dm_hs_phy_irq");
+ if (is_multiport)
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_index + 1);
+ else
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq");
+ if (!irq_name)
+ return -ENOMEM;
+
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
if (irq > 0) {
- ret = dwc3_qcom_request_irq(qcom, irq, "dm_hs_phy_irq");
+ ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
if (ret)
return ret;
- qcom->dm_hs_phy_irq = irq;
+ qcom->ports[port_index].ss_phy_irq = irq;
}

- irq = platform_get_irq_byname_optional(pdev, "ss_phy_irq");
+ if (is_multiport)
+ return 0;
+
+ irq = platform_get_irq_byname_optional(pdev, "qusb2_phy");
if (irq > 0) {
- ret = dwc3_qcom_request_irq(qcom, irq, "ss_phy_irq");
+ ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy");
+ if (ret)
+ return ret;
+ qcom->ports[port_index].qusb2_phy_irq = irq;
+ }
+
+ return 0;
+}
+
+static int dwc3_qcom_find_num_ports(struct platform_device *pdev)
+{
+ char irq_name[14];
+ int port_num;
+ int irq;
+
+ irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1");
+ if (irq <= 0)
+ return 1;
+
+ for (port_num = 2; port_num <= DWC3_MAX_PORTS; port_num++) {
+ sprintf(irq_name, "dp_hs_phy_%d", port_num);
+
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
+ if (irq <= 0)
+ return port_num - 1;
+ }
+
+ return DWC3_MAX_PORTS;
+}
+
+static int dwc3_qcom_setup_irq(struct platform_device *pdev)
+{
+ struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
+ bool is_multiport;
+ int ret;
+ int i;
+
+ qcom->num_ports = dwc3_qcom_find_num_ports(pdev);
+ is_multiport = (qcom->num_ports > 1);
+
+ for (i = 0; i < qcom->num_ports; i++) {
+ ret = dwc3_qcom_setup_port_irq(pdev, i, is_multiport);
if (ret)
return ret;
- qcom->ss_phy_irq = irq;
}

return 0;
--
2.34.1


2024-04-08 14:10:26

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v20 5/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

Add the compatible string for SC8280 Multiport USB controller from
Qualcomm.

There are 4 power event irq interrupts supported by this controller
(one for each port of multiport). Added all the 4 as non-optional
interrupts for SC8280XP-MP

Also each port of multiport has one DP and oen DM IRQ. Add all DP/DM
IRQ's related to 4 ports of SC8280XP Teritiary controller.

Also added ss phy irq for both SS Ports.

Signed-off-by: Krishna Kurapati <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 38a3404ec71b..f55f601c0329 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
- qcom,sc8280xp-dwc3
+ - qcom,sc8280xp-dwc3-mp
- qcom,sdm660-dwc3
- qcom,sdm670-dwc3
- qcom,sdm845-dwc3
@@ -282,6 +283,7 @@ allOf:
contains:
enum:
- qcom,sc8280xp-dwc3
+ - qcom,sc8280xp-dwc3-mp
- qcom,x1e80100-dwc3
then:
properties:
@@ -470,6 +472,38 @@ allOf:
- const: dm_hs_phy_irq
- const: ss_phy_irq

+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8280xp-dwc3-mp
+ then:
+ properties:
+ interrupts:
+ minItems: 18
+ maxItems: 18
+ interrupt-names:
+ items:
+ - const: pwr_event_1
+ - const: pwr_event_2
+ - const: pwr_event_3
+ - const: pwr_event_4
+ - const: hs_phy_1
+ - const: hs_phy_2
+ - const: hs_phy_3
+ - const: hs_phy_4
+ - const: dp_hs_phy_1
+ - const: dm_hs_phy_1
+ - const: dp_hs_phy_2
+ - const: dm_hs_phy_2
+ - const: dp_hs_phy_3
+ - const: dm_hs_phy_3
+ - const: dp_hs_phy_4
+ - const: dm_hs_phy_4
+ - const: ss_phy_1
+ - const: ss_phy_2
+
additionalProperties: false

examples:
--
2.34.1


2024-04-09 00:29:17

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v20 2/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

On Mon, Apr 08, 2024, Krishna Kurapati wrote:
> All DWC3 Multi Port controllers that exist today only support host mode.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
>
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
>
> Wherever we need to perform phy operations like:
>
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
>
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> Reviewed-by: Bjorn Andersson <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 5 ++++
> 2 files changed, 66 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 31684cdaaae3..ddab30531f8a 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -39,6 +39,7 @@
> #include "io.h"
>
> #include "debug.h"
> +#include "../host/xhci-ext-caps.h"
>
> #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
>
> @@ -1881,10 +1882,56 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> return 0;
> }
>
> +static int dwc3_get_num_ports(struct dwc3 *dwc)
> +{
> + void __iomem *base;
> + u8 major_revision;
> + u32 offset;
> + u32 val;
> +
> + /*
> + * Remap xHCI address space to access XHCI ext cap regs since it is
> + * needed to get information on number of ports present.
> + */
> + base = ioremap(dwc->xhci_resources[0].start,
> + resource_size(&dwc->xhci_resources[0]));
> + if (!base)
> + return -ENOMEM;
> +
> + offset = 0;
> + do {
> + offset = xhci_find_next_ext_cap(base, offset,
> + XHCI_EXT_CAPS_PROTOCOL);
> + if (!offset)
> + break;
> +
> + val = readl(base + offset);
> + major_revision = XHCI_EXT_PORT_MAJOR(val);
> +
> + val = readl(base + offset + 0x08);
> + if (major_revision == 0x03) {
> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
> + } else if (major_revision <= 0x02) {
> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
> + } else {
> + dev_warn(dwc->dev, "unrecognized port major revision %d\n",
> + major_revision);
> + }
> + } while (1);
> +
> + dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
> + dwc->num_usb2_ports, dwc->num_usb3_ports);
> +
> + iounmap(base);
> +
> + return 0;
> +}
> +
> static int dwc3_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct resource *res, dwc_res;
> + unsigned int hw_mode;
> void __iomem *regs;
> struct dwc3 *dwc;
> int ret;
> @@ -1968,6 +2015,20 @@ static int dwc3_probe(struct platform_device *pdev)
> goto err_disable_clks;
> }
>
> + /*
> + * Currently only DWC3 controllers that are host-only capable
> + * can have more than one port.
> + */
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> + ret = dwc3_get_num_ports(dwc);
> + if (ret)
> + goto err_disable_clks;
> + } else {
> + dwc->num_usb2_ports = 1;
> + dwc->num_usb3_ports = 1;
> + }
> +
> spin_lock_init(&dwc->lock);
> mutex_init(&dwc->mutex);
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 7e80dd3d466b..341e4c73cb2e 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -1039,6 +1039,8 @@ struct dwc3_scratchpad_array {
> * @usb3_phy: pointer to USB3 PHY
> * @usb2_generic_phy: pointer to USB2 PHY
> * @usb3_generic_phy: pointer to USB3 PHY
> + * @num_usb2_ports: number of USB2 ports
> + * @num_usb3_ports: number of USB3 ports
> * @phys_ready: flag to indicate that PHYs are ready
> * @ulpi: pointer to ulpi interface
> * @ulpi_ready: flag to indicate that ULPI is initialized
> @@ -1187,6 +1189,9 @@ struct dwc3 {
> struct phy *usb2_generic_phy;
> struct phy *usb3_generic_phy;
>
> + u8 num_usb2_ports;
> + u8 num_usb3_ports;
> +
> bool phys_ready;
>
> struct ulpi *ulpi;
> --
> 2.34.1
>

Acked-by: Thinh Nguyen <[email protected]>

Thanks,
Thinh

2024-04-09 01:11:31

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v20 4/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Mon, Apr 08, 2024, Krishna Kurapati wrote:
> Currently the DWC3 driver supports only single port controller
> which requires at least one HS PHY and at most one SS PHY.
>
> But the DWC3 USB controller can be connected to multiple ports and
> each port can have their own PHYs. Each port of the multiport
> controller can either be HS+SS capable or HS only capable
> Proper quantification of them is required to modify GUSB2PHYCFG
> and GUSB3PIPECTL registers appropriately.
>
> Add support for detecting, obtaining and configuring PHYs supported
> by a multiport controller. Limit support to multiport controllers
> with up to four ports for now (e.g. as needed for SC8280XP).
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> Reviewed-by: Johan Hovold <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------
> drivers/usb/dwc3/core.h | 14 ++-
> drivers/usb/dwc3/drd.c | 15 ++-
> 3 files changed, 193 insertions(+), 87 deletions(-)
>

<snip>

> @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc)
>
> iounmap(base);
>
> + if (dwc->num_usb2_ports > DWC3_MAX_PORTS ||
> + dwc->num_usb3_ports > DWC3_MAX_PORTS)
> + return -ENOMEM;

This should be -EINVAL.

> +
> return 0;
> }

<snip>

> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 341e4c73cb2e..df2e111aa848 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -33,6 +33,12 @@
>
> #include <linux/power_supply.h>
>
> +/*
> + * Maximum number of ports currently supported for multiport
> + * controllers.

This macro here is being used per USB2 vs USB3 ports rather than USB2 +
USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and
rename the macro to avoid any confusion. You can also create 2 separate
macros for number of USB2 and USB3 ports even if they share the same
value.

As noted[*], we support have different max number of usb2 ports vs usb3
ports. I would suggest splitting the macros.

[*] https://lore.kernel.org/linux-usb/[email protected]/

> + */
> +#define DWC3_MAX_PORTS 4
> +
>

But it's not a big issue whether you decided to push a new version or a
create a separate patch for the comments above. Here's my Ack:

Acked-by: Thinh Nguyen <[email protected]>

Thanks,
Thinh

2024-04-09 01:15:08

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v20 7/9] usb: dwc3: qcom: Refactor IRQ handling in glue driver

On Mon, Apr 08, 2024, Krishna Kurapati wrote:
> On multiport supported controllers, each port has its own DP/DM
> and SS (if super speed capable) interrupts. As per the bindings,
> their interrupt names differ from standard ones having "_x" added
> as suffix (x indicates port number). Identify from the interrupt
> names whether the controller is a multiport controller or not.
> Refactor dwc3_qcom_setup_irq() call to parse multiport interrupts
> along with non-multiport ones accordingly..
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> Reviewed-by: Johan Hovold <[email protected]>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 137 ++++++++++++++++++++++++++---------
> 1 file changed, 103 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index cae5dab8fcfc..35eb338514bc 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -52,6 +52,13 @@
> #define APPS_USB_AVG_BW 0
> #define APPS_USB_PEAK_BW MBps_to_icc(40)
>
> +struct dwc3_qcom_port {
> + int qusb2_phy_irq;
> + int dp_hs_phy_irq;
> + int dm_hs_phy_irq;
> + int ss_phy_irq;
> +};
> +
> struct dwc3_qcom {
> struct device *dev;
> void __iomem *qscratch_base;
> @@ -59,11 +66,8 @@ struct dwc3_qcom {
> struct clk **clks;
> int num_clocks;
> struct reset_control *resets;
> -
> - int qusb2_phy_irq;
> - int dp_hs_phy_irq;
> - int dm_hs_phy_irq;
> - int ss_phy_irq;
> + struct dwc3_qcom_port ports[DWC3_MAX_PORTS];
> + u8 num_ports;
> enum usb_device_speed usb2_speed;
>
> struct extcon_dev *edev;
> @@ -354,24 +358,24 @@ static void dwc3_qcom_disable_wakeup_irq(int irq)
>
> static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
> {
> - dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq);
> + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].qusb2_phy_irq);
>
> if (qcom->usb2_speed == USB_SPEED_LOW) {
> - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
> + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq);
> } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
> (qcom->usb2_speed == USB_SPEED_FULL)) {
> - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
> + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq);
> } else {
> - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
> - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
> + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq);
> + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq);
> }
>
> - dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
> + dwc3_qcom_disable_wakeup_irq(qcom->ports[0].ss_phy_irq);
> }
>
> static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
> {
> - dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0);
> + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].qusb2_phy_irq, 0);
>
> /*
> * Configure DP/DM line interrupts based on the USB2 device attached to
> @@ -383,20 +387,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
> */
>
> if (qcom->usb2_speed == USB_SPEED_LOW) {
> - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
> - IRQ_TYPE_EDGE_FALLING);
> + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq,
> + IRQ_TYPE_EDGE_FALLING);
> } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
> (qcom->usb2_speed == USB_SPEED_FULL)) {
> - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
> - IRQ_TYPE_EDGE_FALLING);
> + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq,
> + IRQ_TYPE_EDGE_FALLING);
> } else {
> - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
> - IRQ_TYPE_EDGE_RISING);
> - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
> - IRQ_TYPE_EDGE_RISING);
> + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dp_hs_phy_irq,
> + IRQ_TYPE_EDGE_RISING);
> + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].dm_hs_phy_irq,
> + IRQ_TYPE_EDGE_RISING);
> }
>
> - dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
> + dwc3_qcom_enable_wakeup_irq(qcom->ports[0].ss_phy_irq, 0);
> }
>
> static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> @@ -517,42 +521,107 @@ static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq,
> return ret;
> }
>
> -static int dwc3_qcom_setup_irq(struct platform_device *pdev)
> +static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port_index, bool is_multiport)
> {
> struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
> + const char *irq_name;
> int irq;
> int ret;
>
> - irq = platform_get_irq_byname_optional(pdev, "qusb2_phy");
> + if (is_multiport)
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port_index + 1);
> + else
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq");
> + if (!irq_name)
> + return -ENOMEM;
> +
> + irq = platform_get_irq_byname_optional(pdev, irq_name);
> if (irq > 0) {
> - ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy");
> + ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
> if (ret)
> return ret;
> - qcom->qusb2_phy_irq = irq;
> + qcom->ports[port_index].dp_hs_phy_irq = irq;
> }
>
> - irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_irq");
> + if (is_multiport)
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port_index + 1);
> + else
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq");
> + if (!irq_name)
> + return -ENOMEM;
> +
> + irq = platform_get_irq_byname_optional(pdev, irq_name);
> if (irq > 0) {
> - ret = dwc3_qcom_request_irq(qcom, irq, "dp_hs_phy_irq");
> + ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
> if (ret)
> return ret;
> - qcom->dp_hs_phy_irq = irq;
> + qcom->ports[port_index].dm_hs_phy_irq = irq;
> }
>
> - irq = platform_get_irq_byname_optional(pdev, "dm_hs_phy_irq");
> + if (is_multiport)
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_index + 1);
> + else
> + irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq");
> + if (!irq_name)
> + return -ENOMEM;
> +
> + irq = platform_get_irq_byname_optional(pdev, irq_name);
> if (irq > 0) {
> - ret = dwc3_qcom_request_irq(qcom, irq, "dm_hs_phy_irq");
> + ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
> if (ret)
> return ret;
> - qcom->dm_hs_phy_irq = irq;
> + qcom->ports[port_index].ss_phy_irq = irq;
> }
>
> - irq = platform_get_irq_byname_optional(pdev, "ss_phy_irq");
> + if (is_multiport)
> + return 0;
> +
> + irq = platform_get_irq_byname_optional(pdev, "qusb2_phy");
> if (irq > 0) {
> - ret = dwc3_qcom_request_irq(qcom, irq, "ss_phy_irq");
> + ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy");
> + if (ret)
> + return ret;
> + qcom->ports[port_index].qusb2_phy_irq = irq;
> + }
> +
> + return 0;
> +}
> +
> +static int dwc3_qcom_find_num_ports(struct platform_device *pdev)
> +{
> + char irq_name[14];
> + int port_num;
> + int irq;
> +
> + irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1");
> + if (irq <= 0)
> + return 1;
> +
> + for (port_num = 2; port_num <= DWC3_MAX_PORTS; port_num++) {
> + sprintf(irq_name, "dp_hs_phy_%d", port_num);
> +
> + irq = platform_get_irq_byname_optional(pdev, irq_name);
> + if (irq <= 0)
> + return port_num - 1;
> + }
> +
> + return DWC3_MAX_PORTS;
> +}
> +
> +static int dwc3_qcom_setup_irq(struct platform_device *pdev)
> +{
> + struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
> + bool is_multiport;
> + int ret;
> + int i;
> +
> + qcom->num_ports = dwc3_qcom_find_num_ports(pdev);
> + is_multiport = (qcom->num_ports > 1);
> +
> + for (i = 0; i < qcom->num_ports; i++) {
> + ret = dwc3_qcom_setup_port_irq(pdev, i, is_multiport);
> if (ret)
> return ret;
> - qcom->ss_phy_irq = irq;
> }
>
> return 0;
> --
> 2.34.1
>

Acked-by: Thinh Nguyen <[email protected]>

Thanks,
Thinh

2024-04-09 18:14:42

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v20 4/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Tue, Apr 09, 2024, Krishna Kurapati PSSNV wrote:
>
>
> On 4/9/2024 6:41 AM, Thinh Nguyen wrote:
> > On Mon, Apr 08, 2024, Krishna Kurapati wrote:
> > > Currently the DWC3 driver supports only single port controller
> > > which requires at least one HS PHY and at most one SS PHY.
> > >
> > > But the DWC3 USB controller can be connected to multiple ports and
> > > each port can have their own PHYs. Each port of the multiport
> > > controller can either be HS+SS capable or HS only capable
> > > Proper quantification of them is required to modify GUSB2PHYCFG
> > > and GUSB3PIPECTL registers appropriately.
> > >
> > > Add support for detecting, obtaining and configuring PHYs supported
> > > by a multiport controller. Limit support to multiport controllers
> > > with up to four ports for now (e.g. as needed for SC8280XP).
> > >
> > > Signed-off-by: Krishna Kurapati <[email protected]>
> > > Reviewed-by: Johan Hovold <[email protected]>
> > > ---
> > > drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------
> > > drivers/usb/dwc3/core.h | 14 ++-
> > > drivers/usb/dwc3/drd.c | 15 ++-
> > > 3 files changed, 193 insertions(+), 87 deletions(-)
> > >
> >
> > <snip>
> >
> > > @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc)
> > > iounmap(base);
> > > + if (dwc->num_usb2_ports > DWC3_MAX_PORTS ||
> > > + dwc->num_usb3_ports > DWC3_MAX_PORTS)
> > > + return -ENOMEM;
> >
> > This should be -EINVAL.
> >
> > > +
> > > return 0;
> > > }
> >
> > <snip>
> >
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > index 341e4c73cb2e..df2e111aa848 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -33,6 +33,12 @@
> > > #include <linux/power_supply.h>
> > > +/*
> > > + * Maximum number of ports currently supported for multiport
> > > + * controllers.
> >
> > This macro here is being used per USB2 vs USB3 ports rather than USB2 +
> > USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and
> > rename the macro to avoid any confusion. You can also create 2 separate
> > macros for number of USB2 and USB3 ports even if they share the same
> > value.
> >
> > As noted[*], we support have different max number of usb2 ports vs usb3
> > ports. I would suggest splitting the macros.
> >
>
> Hi Thinh,
>
> This macro was intended only to identify how many USB2 (or USB3) Phy's were
> serviced/operated by this driver, not how many logical ports present (like

That's not what you described in the comment right above the macro...

> in xHCI). I don't think it would be confusing currently given that it is
> only used to identify number of generic phy instances to allocate and not
> used for any other purpose. Once the num_usb2_ports and num_usb3_ports are
> read by get_num_ports(...) call, they directly indicate how many ports are

Those fields are clear. But for DWC3_MAX_PORTS, based on the name and
comment of the macro, it's not clear.

> HS and SS respectively. Keeping the same in mind, I returned ENOMEM above
> (as you mentioned) because we don't allocate more than DWC3_MAX_PORTS and if
> the number of hs or ss ports is more than that, we simply return ENOMEM
> saying the driver doesn't support operating those many phy's.

The error code -ENOMEM indicates out of memory failure. The check
condition dwc->num_usb2_ports > DWC3_MAX_PORTS indicates invalid config.
There's no allocation in that check.

>
> > [*] https://urldefense.com/v3/__https://lore.kernel.org/linux-usb/[email protected]/__;!!A4F2R9G_pg!azHqgm92ENkFQrpv6Fhs6PCe210VGOAIrsuGFhrgmfaor8N_kWLu6rxkPpbeCBTLL4NbUpOWlQ0ufmP9DFwO9iFc0XdSEg$
> >
> > > + */
> > > +#define DWC3_MAX_PORTS 4
> > > +
> > >
> >
> > But it's not a big issue whether you decided to push a new version or a
> > create a separate patch for the comments above. Here's my Ack:
> >
>
> Since this is not a bug, I would prefer to make a separate patch to rename
> the macros. (If that is fine).
>

That is fine with me. Thanks for your effort pursuing and continue
working on this series.

BR,
Thinh

2024-04-09 18:22:16

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v20 4/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller



On 4/9/2024 6:41 AM, Thinh Nguyen wrote:
> On Mon, Apr 08, 2024, Krishna Kurapati wrote:
>> Currently the DWC3 driver supports only single port controller
>> which requires at least one HS PHY and at most one SS PHY.
>>
>> But the DWC3 USB controller can be connected to multiple ports and
>> each port can have their own PHYs. Each port of the multiport
>> controller can either be HS+SS capable or HS only capable
>> Proper quantification of them is required to modify GUSB2PHYCFG
>> and GUSB3PIPECTL registers appropriately.
>>
>> Add support for detecting, obtaining and configuring PHYs supported
>> by a multiport controller. Limit support to multiport controllers
>> with up to four ports for now (e.g. as needed for SC8280XP).
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> Reviewed-by: Johan Hovold <[email protected]>
>> ---
>> drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------
>> drivers/usb/dwc3/core.h | 14 ++-
>> drivers/usb/dwc3/drd.c | 15 ++-
>> 3 files changed, 193 insertions(+), 87 deletions(-)
>>
>
> <snip>
>
>> @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc)
>>
>> iounmap(base);
>>
>> + if (dwc->num_usb2_ports > DWC3_MAX_PORTS ||
>> + dwc->num_usb3_ports > DWC3_MAX_PORTS)
>> + return -ENOMEM;
>
> This should be -EINVAL.
>
>> +
>> return 0;
>> }
>
> <snip>
>
>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index 341e4c73cb2e..df2e111aa848 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -33,6 +33,12 @@
>>
>> #include <linux/power_supply.h>
>>
>> +/*
>> + * Maximum number of ports currently supported for multiport
>> + * controllers.
>
> This macro here is being used per USB2 vs USB3 ports rather than USB2 +
> USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and
> rename the macro to avoid any confusion. You can also create 2 separate
> macros for number of USB2 and USB3 ports even if they share the same
> value.
>
> As noted[*], we support have different max number of usb2 ports vs usb3
> ports. I would suggest splitting the macros.
>

Hi Thinh,

This macro was intended only to identify how many USB2 (or USB3) Phy's
were serviced/operated by this driver, not how many logical ports
present (like in xHCI). I don't think it would be confusing currently
given that it is only used to identify number of generic phy instances
to allocate and not used for any other purpose. Once the num_usb2_ports
and num_usb3_ports are read by get_num_ports(...) call, they directly
indicate how many ports are HS and SS respectively. Keeping the same in
mind, I returned ENOMEM above (as you mentioned) because we don't
allocate more than DWC3_MAX_PORTS and if the number of hs or ss ports is
more than that, we simply return ENOMEM saying the driver doesn't
support operating those many phy's.

> [*] https://lore.kernel.org/linux-usb/[email protected]/
>
>> + */
>> +#define DWC3_MAX_PORTS 4
>> +
>>
>
> But it's not a big issue whether you decided to push a new version or a
> create a separate patch for the comments above. Here's my Ack:
>

Since this is not a bug, I would prefer to make a separate patch to
rename the macros. (If that is fine).

> Acked-by: Thinh Nguyen <[email protected]>
>
> Thanks,
> Thinh

2024-04-10 04:41:39

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v20 4/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller



On 4/9/2024 11:43 PM, Thinh Nguyen wrote:
> On Tue, Apr 09, 2024, Krishna Kurapati PSSNV wrote:
>>
>>
>> On 4/9/2024 6:41 AM, Thinh Nguyen wrote:
>>> On Mon, Apr 08, 2024, Krishna Kurapati wrote:
>>>> Currently the DWC3 driver supports only single port controller
>>>> which requires at least one HS PHY and at most one SS PHY.
>>>>
>>>> But the DWC3 USB controller can be connected to multiple ports and
>>>> each port can have their own PHYs. Each port of the multiport
>>>> controller can either be HS+SS capable or HS only capable
>>>> Proper quantification of them is required to modify GUSB2PHYCFG
>>>> and GUSB3PIPECTL registers appropriately.
>>>>
>>>> Add support for detecting, obtaining and configuring PHYs supported
>>>> by a multiport controller. Limit support to multiport controllers
>>>> with up to four ports for now (e.g. as needed for SC8280XP).
>>>>
>>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>>> Reviewed-by: Johan Hovold <[email protected]>
>>>> ---
>>>> drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------
>>>> drivers/usb/dwc3/core.h | 14 ++-
>>>> drivers/usb/dwc3/drd.c | 15 ++-
>>>> 3 files changed, 193 insertions(+), 87 deletions(-)
>>>>
>>>
>>> <snip>
>>>
>>>> @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc)
>>>> iounmap(base);
>>>> + if (dwc->num_usb2_ports > DWC3_MAX_PORTS ||
>>>> + dwc->num_usb3_ports > DWC3_MAX_PORTS)
>>>> + return -ENOMEM;
>>>
>>> This should be -EINVAL.
>>>
>>>> +
>>>> return 0;
>>>> }
>>>
>>> <snip>
>>>
>>>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>>>> index 341e4c73cb2e..df2e111aa848 100644
>>>> --- a/drivers/usb/dwc3/core.h
>>>> +++ b/drivers/usb/dwc3/core.h
>>>> @@ -33,6 +33,12 @@
>>>> #include <linux/power_supply.h>
>>>> +/*
>>>> + * Maximum number of ports currently supported for multiport
>>>> + * controllers.
>>>
>>> This macro here is being used per USB2 vs USB3 ports rather than USB2 +
>>> USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and
>>> rename the macro to avoid any confusion. You can also create 2 separate
>>> macros for number of USB2 and USB3 ports even if they share the same
>>> value.
>>>
>>> As noted[*], we support have different max number of usb2 ports vs usb3
>>> ports. I would suggest splitting the macros.
>>>
>>
>> Hi Thinh,
>>
>> This macro was intended only to identify how many USB2 (or USB3) Phy's were
>> serviced/operated by this driver, not how many logical ports present (like
>
> That's not what you described in the comment right above the macro...
>
>> in xHCI). I don't think it would be confusing currently given that it is
>> only used to identify number of generic phy instances to allocate and not
>> used for any other purpose. Once the num_usb2_ports and num_usb3_ports are
>> read by get_num_ports(...) call, they directly indicate how many ports are
>
> Those fields are clear. But for DWC3_MAX_PORTS, based on the name and
> comment of the macro, it's not clear.
>
>> HS and SS respectively. Keeping the same in mind, I returned ENOMEM above
>> (as you mentioned) because we don't allocate more than DWC3_MAX_PORTS and if
>> the number of hs or ss ports is more than that, we simply return ENOMEM
>> saying the driver doesn't support operating those many phy's.
>
> The error code -ENOMEM indicates out of memory failure. The check
> condition dwc->num_usb2_ports > DWC3_MAX_PORTS indicates invalid config.
> There's no allocation in that check.
>
>>
>>> [*] https://urldefense.com/v3/__https://lore.kernel.org/linux-usb/[email protected]/__;!!A4F2R9G_pg!azHqgm92ENkFQrpv6Fhs6PCe210VGOAIrsuGFhrgmfaor8N_kWLu6rxkPpbeCBTLL4NbUpOWlQ0ufmP9DFwO9iFc0XdSEg$
>>>
>>>> + */
>>>> +#define DWC3_MAX_PORTS 4
>>>> +
>>>>
>>>
>>> But it's not a big issue whether you decided to push a new version or a
>>> create a separate patch for the comments above. Here's my Ack:
>>>
>>
>> Since this is not a bug, I would prefer to make a separate patch to rename
>> the macros. (If that is fine).
>>
>
> That is fine with me. Thanks for your effort pursuing and continue
> working on this series.
>

Thanks Thinh. If there are no other issues, I will wait till Greg picks
the series up. Thanks for the reviews throughout the series.

Regards,
Krishna,

2024-04-11 12:20:35

by Greg KH

[permalink] [raw]
Subject: Re: [PATCH v20 4/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Wed, Apr 10, 2024 at 10:10:54AM +0530, Krishna Kurapati PSSNV wrote:
>
>
> On 4/9/2024 11:43 PM, Thinh Nguyen wrote:
> > On Tue, Apr 09, 2024, Krishna Kurapati PSSNV wrote:
> > >
> > >
> > > On 4/9/2024 6:41 AM, Thinh Nguyen wrote:
> > > > On Mon, Apr 08, 2024, Krishna Kurapati wrote:
> > > > > Currently the DWC3 driver supports only single port controller
> > > > > which requires at least one HS PHY and at most one SS PHY.
> > > > >
> > > > > But the DWC3 USB controller can be connected to multiple ports and
> > > > > each port can have their own PHYs. Each port of the multiport
> > > > > controller can either be HS+SS capable or HS only capable
> > > > > Proper quantification of them is required to modify GUSB2PHYCFG
> > > > > and GUSB3PIPECTL registers appropriately.
> > > > >
> > > > > Add support for detecting, obtaining and configuring PHYs supported
> > > > > by a multiport controller. Limit support to multiport controllers
> > > > > with up to four ports for now (e.g. as needed for SC8280XP).
> > > > >
> > > > > Signed-off-by: Krishna Kurapati <[email protected]>
> > > > > Reviewed-by: Johan Hovold <[email protected]>
> > > > > ---
> > > > > drivers/usb/dwc3/core.c | 251 ++++++++++++++++++++++++++++------------
> > > > > drivers/usb/dwc3/core.h | 14 ++-
> > > > > drivers/usb/dwc3/drd.c | 15 ++-
> > > > > 3 files changed, 193 insertions(+), 87 deletions(-)
> > > > >
> > > >
> > > > <snip>
> > > >
> > > > > @@ -1937,6 +2020,10 @@ static int dwc3_get_num_ports(struct dwc3 *dwc)
> > > > > iounmap(base);
> > > > > + if (dwc->num_usb2_ports > DWC3_MAX_PORTS ||
> > > > > + dwc->num_usb3_ports > DWC3_MAX_PORTS)
> > > > > + return -ENOMEM;
> > > >
> > > > This should be -EINVAL.
> > > >
> > > > > +
> > > > > return 0;
> > > > > }
> > > >
> > > > <snip>
> > > >
> > > > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > > > index 341e4c73cb2e..df2e111aa848 100644
> > > > > --- a/drivers/usb/dwc3/core.h
> > > > > +++ b/drivers/usb/dwc3/core.h
> > > > > @@ -33,6 +33,12 @@
> > > > > #include <linux/power_supply.h>
> > > > > +/*
> > > > > + * Maximum number of ports currently supported for multiport
> > > > > + * controllers.
> > > >
> > > > This macro here is being used per USB2 vs USB3 ports rather than USB2 +
> > > > USB3, unlike the xHCI MAXPORTS. You can clarify in the comment and
> > > > rename the macro to avoid any confusion. You can also create 2 separate
> > > > macros for number of USB2 and USB3 ports even if they share the same
> > > > value.
> > > >
> > > > As noted[*], we support have different max number of usb2 ports vs usb3
> > > > ports. I would suggest splitting the macros.
> > > >
> > >
> > > Hi Thinh,
> > >
> > > This macro was intended only to identify how many USB2 (or USB3) Phy's were
> > > serviced/operated by this driver, not how many logical ports present (like
> >
> > That's not what you described in the comment right above the macro...
> >
> > > in xHCI). I don't think it would be confusing currently given that it is
> > > only used to identify number of generic phy instances to allocate and not
> > > used for any other purpose. Once the num_usb2_ports and num_usb3_ports are
> > > read by get_num_ports(...) call, they directly indicate how many ports are
> >
> > Those fields are clear. But for DWC3_MAX_PORTS, based on the name and
> > comment of the macro, it's not clear.
> >
> > > HS and SS respectively. Keeping the same in mind, I returned ENOMEM above
> > > (as you mentioned) because we don't allocate more than DWC3_MAX_PORTS and if
> > > the number of hs or ss ports is more than that, we simply return ENOMEM
> > > saying the driver doesn't support operating those many phy's.
> >
> > The error code -ENOMEM indicates out of memory failure. The check
> > condition dwc->num_usb2_ports > DWC3_MAX_PORTS indicates invalid config.
> > There's no allocation in that check.
> >
> > >
> > > > [*] https://urldefense.com/v3/__https://lore.kernel.org/linux-usb/[email protected]/__;!!A4F2R9G_pg!azHqgm92ENkFQrpv6Fhs6PCe210VGOAIrsuGFhrgmfaor8N_kWLu6rxkPpbeCBTLL4NbUpOWlQ0ufmP9DFwO9iFc0XdSEg$
> > > >
> > > > > + */
> > > > > +#define DWC3_MAX_PORTS 4
> > > > > +
> > > > >
> > > >
> > > > But it's not a big issue whether you decided to push a new version or a
> > > > create a separate patch for the comments above. Here's my Ack:
> > > >
> > >
> > > Since this is not a bug, I would prefer to make a separate patch to rename
> > > the macros. (If that is fine).
> > >
> >
> > That is fine with me. Thanks for your effort pursuing and continue
> > working on this series.
> >
>
> Thanks Thinh. If there are no other issues, I will wait till Greg picks the
> series up. Thanks for the reviews throughout the series.

I can't take it yet, based on the review of this patch, so I'll wait for
a new version of the series.

thanks,

greg k-h