During the review of [1] Abhinav pointed out that mdp_rgb_formats and
mdp_rgb_yuv_formats arrays from patch 1 are directly based on the struct
mdp_format formats array. This was true, because MDP4 / MDP5 drivers
used their own (small) list of supported formats. The DPU driver,
supporting more formats, had larger database of the formats and their
properties. While we don't have plans to expand MDP5 formats support, it
make sense to merge these two databases into a common dataset.
[1] https://patchwork.freedesktop.org/series/120377/
--
Changes in v2:
- Rebased on top of msm-next
- Moved all formats data to the new header mdp_formats.h (Abhinav)
- Dropped the alpha_enable flag changes (Abhinav)
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Dmitry Baryshkov (9):
drm/msm/dpu: use format-related definitions from mdp_common.xml.h
drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
drm/msm/dpu: in dpu_format replace bitmap with unsigned long field
drm/msm/dpu: pull format flag definitions to mdp_format.h
drm/msm: merge dpu_format and mdp_format in struct msm_format
drm/msm: convert msm_format::unpack_tight to the flag
drm/msm: convert msm_format::unpack_align_msb to the flag
drm/msm: merge dpu format database to MDP formats
drm/msm: drop msm_kms_funcs::get_format() callback
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 658 +--------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 27 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 124 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 40 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 14 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 22 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 75 +--
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 86 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 95 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 630 +++++++++++++++++---
drivers/gpu/drm/msm/disp/mdp_format.h | 77 +++
drivers/gpu/drm/msm/disp/mdp_kms.h | 18 +-
drivers/gpu/drm/msm/msm_drv.h | 4 +-
drivers/gpu/drm/msm/msm_fb.c | 2 +-
drivers/gpu/drm/msm/msm_kms.h | 4 -
34 files changed, 913 insertions(+), 1075 deletions(-)
---
base-commit: a35e92ef04c07bd473404b9b73d489aea19a60a8
change-id: 20240420-dpu-format-d655c60875df
Best regards,
--
Dmitry Baryshkov <[email protected]>
MDP4 and MDP5 drivers enumerate supported formats each time the plane is
created. In preparation to merger of MDP DPU format databases, define
precise formats list, so that changes to the database do not cause the
driver to add unsupported format to the list.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 +++++++++++++++++++++++++++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 ++++++++++++++-----
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ---------------
drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
4 files changed, 80 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index b689b618da78..cebe20c82a54 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+const uint32_t mdp4_rgb_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+};
+
+const uint32_t mdp4_rgb_yuv_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
enum mdp4_pipe pipe_id, bool private_plane)
@@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
struct mdp4_plane *mdp4_plane;
int ret;
enum drm_plane_type type;
+ const uint32_t *formats;
+ unsigned int nformats;
mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
if (!mdp4_plane) {
@@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
mdp4_plane->name = pipe_names[pipe_id];
mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
- mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
- ARRAY_SIZE(mdp4_plane->formats),
- !pipe_supports_yuv(mdp4_plane->caps));
-
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
+
+ if (pipe_supports_yuv(mdp4_plane->caps)) {
+ formats = mdp4_rgb_yuv_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
+ } else {
+ formats = mdp4_rgb_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_formats);
+ }
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
- mdp4_plane->formats, mdp4_plane->nformats,
+ formats, nformats,
supported_format_modifiers, type, NULL);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 0d5ff03cb091..aa8342d93393 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -17,9 +17,6 @@
struct mdp5_plane {
struct drm_plane base;
-
- uint32_t nformats;
- uint32_t formats[32];
};
#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
@@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
return mask;
}
+const uint32_t mdp5_plane_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
enum drm_plane_type type)
@@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
plane = &mdp5_plane->base;
- mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
- ARRAY_SIZE(mdp5_plane->formats), false);
-
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
- mdp5_plane->formats, mdp5_plane->nformats,
- NULL, type, NULL);
+ mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
+ NULL, type, NULL);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 025595336f26..69ab5bcff1a9 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -80,10 +80,6 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
#define BPC0A 0
-/*
- * Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
- * mdp_get_rgb_formats()'s implementation.
- */
static const struct mdp_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
@@ -138,30 +134,6 @@ static const struct mdp_format formats[] = {
MDP_PLANE_PLANAR, CHROMA_420, true),
};
-/*
- * Note:
- * @rgb_only must be set to true, when requesting
- * supported formats for RGB pipes.
- */
-uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats,
- bool rgb_only)
-{
- uint32_t i;
- for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct mdp_format *f = &formats[i];
-
- if (i == max_formats)
- break;
-
- if (rgb_only && MDP_FORMAT_IS_YUV(f))
- break;
-
- pixel_formats[i] = f->base.pixel_format;
- }
-
- return i;
-}
-
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
uint64_t modifier)
{
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index b0286d5d5130..d0718c16de3e 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -91,7 +91,6 @@ struct mdp_format {
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
-uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
/* MDP capabilities */
--
2.39.2
Using bitmap for the flags results in a clumsy syntax on test_bit,
replace it with unsigned long type and simple binary ops.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 18 +++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 16 +++++++---------
2 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 87fa14fc5dd0..caf536788ece 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -45,7 +45,7 @@ bp, flg, fm, np) \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -64,7 +64,7 @@ alpha, bp, flg, fm, np, th) \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -84,7 +84,7 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -102,7 +102,7 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -121,7 +121,7 @@ flg, fm, np, th) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -139,7 +139,7 @@ flg, fm, np, th) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -158,7 +158,7 @@ flg, fm, np, th) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -178,7 +178,7 @@ flg, fm, np) \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -1047,7 +1047,7 @@ const struct dpu_format *dpu_get_dpu_format_ext(
DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
(char *)&format, modifier);
else
- DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
+ DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
(char *)&format, modifier,
DPU_FORMAT_IS_UBWC(fmt),
DPU_FORMAT_IS_YUV(fmt));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 31f97f535ce9..ed5206652413 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -40,23 +40,21 @@ enum dpu_format_flags {
DPU_FORMAT_FLAG_YUV_BIT,
DPU_FORMAT_FLAG_DX_BIT,
DPU_FORMAT_FLAG_COMPRESSED_BIT,
- DPU_FORMAT_FLAG_BIT_MAX,
};
#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
-#define DPU_FORMAT_IS_YUV(X) \
- (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
-#define DPU_FORMAT_IS_DX(X) \
- (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
+
+#define DPU_FORMAT_IS_YUV(X) ((X)->flags & DPU_FORMAT_FLAG_YUV)
+#define DPU_FORMAT_IS_DX(X) ((X)->flags & DPU_FORMAT_FLAG_DX)
#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
#define DPU_FORMAT_IS_TILE(X) \
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
- !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
+ !((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
#define DPU_FORMAT_IS_UBWC(X) \
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
- test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
+ ((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
@@ -334,7 +332,7 @@ enum dpu_3d_blend_mode {
* @alpha_enable: whether the format has an alpha channel
* @num_planes: number of planes (including meta data planes)
* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
- * @flag: usage bit flags
+ * @flags: usage bit flags
* @tile_width: format tile width
* @tile_height: format tile height
*/
@@ -351,7 +349,7 @@ struct dpu_format {
u8 alpha_enable;
u8 num_planes;
enum mdp_fetch_mode fetch_mode;
- DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
+ unsigned long flags;
u16 tile_width;
u16 tile_height;
};
--
2.39.2
Instead of having DPU-specific defines, switch to the definitions from
the mdp_common.xml.h file. This is the preparation for merged of DPU and
MDP format tables.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 290 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 64 +----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
8 files changed, 169 insertions(+), 219 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index aa1e68379d9f..43431cb55421 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2223,19 +2223,19 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
/* enable 10 bit logic */
switch (cdm_cfg->output_fmt->chroma_sample) {
- case DPU_CHROMA_RGB:
+ case CHROMA_FULL:
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
- case DPU_CHROMA_H2V1:
+ case CHROMA_H2V1:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
- case DPU_CHROMA_420:
+ case CHROMA_420:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
break;
- case DPU_CHROMA_H1V2:
+ case CHROMA_H1V2:
default:
DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
DRMID(phys_enc->parent));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 9dbb8ddcddec..ff41493147ab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 95e6e58b1a21..87fa14fc5dd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -35,11 +35,11 @@
bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
+ .fetch_planes = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
@@ -54,11 +54,11 @@ bp, flg, fm, np) \
alpha, bp, flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
+ .fetch_planes = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
@@ -74,7 +74,7 @@ alpha, bp, flg, fm, np, th) \
alpha, chroma, count, bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
+ .fetch_planes = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
.bits = { g, b, r, a }, \
@@ -92,7 +92,7 @@ alpha, chroma, count, bp, flg, fm, np) \
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -111,7 +111,7 @@ alpha, chroma, count, bp, flg, fm, np) \
flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -129,7 +129,7 @@ flg, fm, np, th) \
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -148,7 +148,7 @@ flg, fm, np, th) \
flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -168,7 +168,7 @@ flg, fm, np, th) \
flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PLANAR, \
+ .fetch_planes = MDP_PLANE_PLANAR, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
.bits = { g, b, r, a }, \
@@ -195,286 +195,286 @@ struct dpu_media_color_map {
static const struct dpu_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(ARGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB888,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 3, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR888,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 3, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+ 0, BPC5, BPC6, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+ 0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
PSEUDO_YUV_FMT(NV12,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV21,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV16,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV61,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(VYUY,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(UYVY,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YUYV,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YVYU,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PLANAR_YUV_FMT(YUV420,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 3),
+ false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
PLANAR_YUV_FMT(YVU420,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 3),
+ false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
};
/*
@@ -485,88 +485,88 @@ static const struct dpu_format dpu_format_map[] = {
*/
static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+ 0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* ARGB8888 and ABGR8888 purposely have the same color
* ordering. The hardware only supports ABGR8888 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* XRGB2101010 and ARGB2101010 purposely have the same color
* ordering. The hardware only supports ARGB2101010 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
+ CHROMA_420, DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
+ MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
+ CHROMA_420, DPU_FORMAT_FLAG_DX |
DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
};
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
* Note: Not using the drm_format_*_subsampling since we have formats
*/
static void _dpu_get_v_h_subsample_rate(
- enum dpu_chroma_samp_type chroma_sample,
+ enum mdp_chroma_samp_type chroma_sample,
uint32_t *v_sample,
uint32_t *h_sample)
{
@@ -574,15 +574,15 @@ static void _dpu_get_v_h_subsample_rate(
return;
switch (chroma_sample) {
- case DPU_CHROMA_H2V1:
+ case CHROMA_H2V1:
*v_sample = 1;
*h_sample = 2;
break;
- case DPU_CHROMA_H1V2:
+ case CHROMA_H1V2:
*v_sample = 2;
*h_sample = 1;
break;
- case DPU_CHROMA_420:
+ case CHROMA_420:
*v_sample = 2;
*h_sample = 2;
break;
@@ -724,7 +724,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->num_planes = fmt->num_planes;
/* Due to memset above, only need to set planes of interest */
- if (fmt->fetch_planes == DPU_PLANE_INTERLEAVED) {
+ if (fmt->fetch_planes == MDP_PLANE_INTERLEAVED) {
layout->num_planes = 1;
layout->plane_size[0] = width * height * layout->format->bpp;
layout->plane_pitch[0] = width * layout->format->bpp;
@@ -751,7 +751,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->plane_size[1] = layout->plane_pitch[1] *
(height / v_subsample);
- if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
layout->num_planes = 2;
layout->plane_size[1] *= 2;
layout->plane_pitch[1] *= 2;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
index 9016b3ade6bc..3602cbda793e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
@@ -186,7 +186,7 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
dpu_hw_cdm_setup_cdwn(ctx, cdm);
if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
- if (fmt->chroma_sample == DPU_CHROMA_H1V2)
+ if (fmt->chroma_sample == CHROMA_H1V2)
return -EINVAL; /*unsupported format */
opmode = CDM_HDMI_PACK_OP_MODE_EN;
opmode |= (fmt->chroma_sample << 1);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 965692ef7892..55c7e941e163 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -201,9 +201,9 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
(0x21 << 8));
else
/* Interface treats all the pixel data in RGB888 format */
- panel_format = (COLOR_8BIT |
- (COLOR_8BIT << 2) |
- (COLOR_8BIT << 4) |
+ panel_format = (BPC8 |
+ (BPC8 << 2) |
+ (BPC8 << 4) |
(0x21 << 8));
DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 5df545904057..31f97f535ce9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -9,6 +9,7 @@
#include <linux/err.h>
#include "msm_drv.h"
+#include "mdp_common.xml.h"
#define DPU_DBG_NAME "dpu"
@@ -49,12 +50,12 @@ enum dpu_format_flags {
(test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
#define DPU_FORMAT_IS_DX(X) \
(test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
-#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
+#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
#define DPU_FORMAT_IS_TILE(X) \
- (((X)->fetch_mode == DPU_FETCH_UBWC) && \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
!test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
#define DPU_FORMAT_IS_UBWC(X) \
- (((X)->fetch_mode == DPU_FETCH_UBWC) && \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
@@ -300,57 +301,6 @@ enum {
C3_ALPHA = 3
};
-/**
- * enum dpu_plane_type - defines how the color component pixel packing
- * @DPU_PLANE_INTERLEAVED : Color components in single plane
- * @DPU_PLANE_PLANAR : Color component in separate planes
- * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
- */
-enum dpu_plane_type {
- DPU_PLANE_INTERLEAVED,
- DPU_PLANE_PLANAR,
- DPU_PLANE_PSEUDO_PLANAR,
-};
-
-/**
- * enum dpu_chroma_samp_type - chroma sub-samplng type
- * @DPU_CHROMA_RGB : No chroma subsampling
- * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
- * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
- * @DPU_CHROMA_420 : 420 subsampling
- */
-enum dpu_chroma_samp_type {
- DPU_CHROMA_RGB,
- DPU_CHROMA_H2V1,
- DPU_CHROMA_H1V2,
- DPU_CHROMA_420
-};
-
-/**
- * dpu_fetch_type - Defines How DPU HW fetches data
- * @DPU_FETCH_LINEAR : fetch is line by line
- * @DPU_FETCH_TILE : fetches data in Z order from a tile
- * @DPU_FETCH_UBWC : fetch and decompress data
- */
-enum dpu_fetch_type {
- DPU_FETCH_LINEAR,
- DPU_FETCH_TILE,
- DPU_FETCH_UBWC
-};
-
-/**
- * Value of enum chosen to fit the number of bits
- * expected by the HW programming.
- */
-enum {
- COLOR_ALPHA_1BIT = 0,
- COLOR_ALPHA_4BIT = 1,
- COLOR_4BIT = 0,
- COLOR_5BIT = 1, /* No 5-bit Alpha */
- COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
- COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
-};
-
/**
* enum dpu_3d_blend_mode
* Desribes how the 3d data is blended
@@ -390,17 +340,17 @@ enum dpu_3d_blend_mode {
*/
struct dpu_format {
struct msm_format base;
- enum dpu_plane_type fetch_planes;
+ enum mdp_fetch_type fetch_planes;
u8 element[DPU_MAX_PLANES];
u8 bits[DPU_MAX_PLANES];
- enum dpu_chroma_samp_type chroma_sample;
+ enum mdp_chroma_samp_type chroma_sample;
u8 unpack_align_msb;
u8 unpack_tight;
u8 unpack_count;
u8 bpp;
u8 alpha_enable;
u8 num_planes;
- enum dpu_fetch_type fetch_mode;
+ enum mdp_fetch_mode fetch_mode;
DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
u16 tile_width;
u16 tile_height;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 0bf8a83e8df3..896fb576f5b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -241,10 +241,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
chroma_samp = fmt->chroma_sample;
if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
- if (chroma_samp == DPU_CHROMA_H2V1)
- chroma_samp = DPU_CHROMA_H1V2;
- else if (chroma_samp == DPU_CHROMA_H1V2)
- chroma_samp = DPU_CHROMA_H2V1;
+ if (chroma_samp == CHROMA_H2V1)
+ chroma_samp = CHROMA_H1V2;
+ else if (chroma_samp == CHROMA_H1V2)
+ chroma_samp = CHROMA_H2V1;
}
src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
@@ -254,7 +254,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
- if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
+ if (fmt->alpha_enable && fmt->fetch_planes == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@@ -267,7 +267,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
- if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
+ if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
if (DPU_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index ff4ac4daaeca..daaf6fe7e904 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -214,8 +214,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/* FIXME: in multirect case account for the src_width of all the planes */
- if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
- if (fmt->chroma_sample == DPU_CHROMA_420) {
+ if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->chroma_sample == CHROMA_420) {
/* NV12 */
total_fl = (fixed_buff_size / 2) /
((src_width + 32) * fmt->bpp);
--
2.39.2
Instead of having a u8 or bool field unpack_align_msb, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12 ++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.h | 4 ++--
4 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 705b91582b0f..2bb1584920c6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -43,7 +43,6 @@ bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_align_msb = 0, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -64,7 +63,6 @@ alpha, bp, flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_align_msb = 0, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -86,7 +84,6 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -106,7 +103,6 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -127,7 +123,6 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -147,11 +142,10 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -168,11 +162,10 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -190,7 +183,6 @@ flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index d411d70b8cd8..f4b4cd084282 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -264,7 +264,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
- (fmt->unpack_align_msb << 18) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->bpp - 1) << 9);
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 19163634855f..93ff01c889b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -97,7 +97,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[1] << 8) |
(fmt->element[0] << 0);
- dst_format |= (fmt->unpack_align_msb << 18) |
+ dst_format |= ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
index 18b2822dd552..d17f63c045a7 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.h
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -15,12 +15,14 @@ enum msm_format_flags {
MSM_FORMAT_FLAG_DX_BIT,
MSM_FORMAT_FLAG_COMPRESSED_BIT,
MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
+ MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT,
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
/**
* struct msm_format: defines the format configuration
@@ -29,7 +31,6 @@ enum msm_format_flags {
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
* @alpha_enable: whether the format has an alpha channel
- * @unpack_align_msb: unpack aligned to LSB or MSB
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
* @flags: usage bit flags
@@ -45,7 +46,6 @@ struct msm_format {
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool alpha_enable;
- u8 unpack_align_msb;
u8 unpack_count;
u8 bpp;
unsigned long flags;
--
2.39.2
Instead of having a u8 or bool field unpack_tight, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 22 ++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 52 ++++++++++++++---------------
drivers/gpu/drm/msm/disp/mdp_format.h | 4 +--
7 files changed, 41 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 855f0d29c387..705b91582b0f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -44,11 +44,10 @@ bp, flg, fm, np) \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -66,11 +65,10 @@ alpha, bp, flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -89,11 +87,10 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -110,11 +107,10 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -132,11 +128,10 @@ flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -153,7 +148,6 @@ flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
- .unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -175,7 +169,6 @@ flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
- .unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -198,11 +191,10 @@ flg, fm, np) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -636,7 +628,7 @@ static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
if (fmt->pixel_format == DRM_FORMAT_NV12 ||
fmt->pixel_format == DRM_FORMAT_P010) {
if (MSM_FORMAT_IS_DX(fmt)) {
- if (fmt->unpack_tight)
+ if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
else
color_fmt = COLOR_FMT_P010_UBWC;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index fdd77dc51776..d411d70b8cd8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -263,7 +263,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
- (fmt->unpack_tight << 17) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 2fdf1b703042..19163634855f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -98,7 +98,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[0] << 0);
dst_format |= (fmt->unpack_align_msb << 18) |
- (fmt->unpack_tight << 17) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index 0bae90d3f21e..ef7e525c3bd2 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -325,7 +325,8 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
- COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
+ COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
+ MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 3b7c3eac8eda..cc0dc451dc2e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -801,7 +801,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
- COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
+ COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
+ MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 5fc55f41e74f..b9f0b13d25d5 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -62,7 +62,7 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
};
-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
+#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, c, cnt, fp, cs, yuv) { \
.pixel_format = DRM_FORMAT_ ## name, \
.bpc_a = BPC ## a ## A, \
.bpc_r_cr = BPC ## r, \
@@ -72,65 +72,65 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.fetch_type = fp, \
.chroma_sample = cs, \
.alpha_enable = alpha, \
- .unpack_tight = tight, \
.unpack_count = cnt, \
.bpp = c, \
- .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (yuv ? MSM_FORMAT_FLAG_YUV : 0), \
}
#define BPC0A 0
static const struct msm_format formats[] = {
- /* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
- FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
+ /* name a r g b e0 e1 e2 e3 alpha cpp cnt ... */
+ FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
+ FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
+ FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
+ FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
+ FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
+ FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
+ FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
+ FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
+ FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, 3, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 3, 3,
+ FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, 3, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, true, 2, 3,
+ FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, 2, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, true, 2, 3,
+ FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, 2, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
/* --- RGB formats above / YUV formats below this line --- */
/* 2 plane YUV */
- FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
+ FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
+ FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
+ FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
- FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
+ FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
/* 1 plane YUV */
- FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 2, 4,
+ FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 2, 4,
+ FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, true, 2, 4,
+ FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, true, 2, 4,
+ FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
/* 3 plane YUV */
- FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 1, 1,
+ FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, 1, 1,
MDP_PLANE_PLANAR, CHROMA_420, true),
- FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 1, 1,
+ FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, 1, 1,
MDP_PLANE_PLANAR, CHROMA_420, true),
};
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
index 6443d53954ee..18b2822dd552 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.h
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -14,11 +14,13 @@ enum msm_format_flags {
MSM_FORMAT_FLAG_YUV_BIT,
MSM_FORMAT_FLAG_DX_BIT,
MSM_FORMAT_FLAG_COMPRESSED_BIT,
+ MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
/**
* struct msm_format: defines the format configuration
@@ -27,7 +29,6 @@ enum msm_format_flags {
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
* @alpha_enable: whether the format has an alpha channel
- * @unpack_tight: whether to use tight or loose unpack
* @unpack_align_msb: unpack aligned to LSB or MSB
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
@@ -44,7 +45,6 @@ struct msm_format {
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool alpha_enable;
- u8 unpack_tight;
u8 unpack_align_msb;
u8 unpack_count;
u8 bpp;
--
2.39.2
In preparation to merger of formats databases, pull format flag
definitions to mdp_format.h header, so that they are visibile to both
dpu and mdp drivers.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++++++++++++++---------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 31 +++------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +--
drivers/gpu/drm/msm/disp/mdp_format.c | 6 +-
drivers/gpu/drm/msm/disp/mdp_format.h | 39 ++++++++++++
drivers/gpu/drm/msm/disp/mdp_kms.h | 4 +-
drivers/gpu/drm/msm/msm_drv.h | 4 --
9 files changed, 109 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index caf536788ece..0c2afded0e56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -44,8 +44,8 @@ bp, flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -63,8 +63,8 @@ alpha, bp, flg, fm, np, th) \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -83,8 +83,8 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -101,8 +101,8 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -120,8 +120,8 @@ flg, fm, np, th) \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -138,8 +138,8 @@ flg, fm, np, th) \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -157,8 +157,8 @@ flg, fm, np, th) \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -177,8 +177,8 @@ flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -365,115 +365,115 @@ static const struct dpu_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(BGRA1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
PSEUDO_YUV_FMT(NV12,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV21,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV16,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV61,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
+ CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(VYUY,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(UYVY,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YUYV,
0, BPC8, BPC8, BPC8,
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YVYU,
0, BPC8, BPC8, BPC8,
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PLANAR_YUV_FMT(YUV420,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 3),
PLANAR_YUV_FMT(YVU420,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 3),
};
@@ -487,13 +487,13 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, DPU_FORMAT_FLAG_COMPRESSED,
+ false, 2, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* ARGB8888 and ABGR8888 purposely have the same color
@@ -503,37 +503,37 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* XRGB2101010 and ARGB2101010 purposely have the same color
@@ -543,22 +543,22 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_YUV |
- DPU_FORMAT_FLAG_COMPRESSED,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_DX |
- DPU_FORMAT_FLAG_YUV |
- DPU_FORMAT_FLAG_COMPRESSED,
+ CHROMA_420, MSM_FORMAT_FLAG_DX |
+ MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index ed5206652413..aa639a43941f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -9,7 +9,8 @@
#include <linux/err.h>
#include "msm_drv.h"
-#include "mdp_common.xml.h"
+
+#include "disp/mdp_format.h"
#define DPU_DBG_NAME "dpu"
@@ -36,25 +37,11 @@
#define DPU_MAX_DE_CURVES 3
#endif
-enum dpu_format_flags {
- DPU_FORMAT_FLAG_YUV_BIT,
- DPU_FORMAT_FLAG_DX_BIT,
- DPU_FORMAT_FLAG_COMPRESSED_BIT,
-};
-
-#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
-#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
-#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
-
-#define DPU_FORMAT_IS_YUV(X) ((X)->flags & DPU_FORMAT_FLAG_YUV)
-#define DPU_FORMAT_IS_DX(X) ((X)->flags & DPU_FORMAT_FLAG_DX)
-#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
-#define DPU_FORMAT_IS_TILE(X) \
- (((X)->fetch_mode == MDP_FETCH_UBWC) && \
- !((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
-#define DPU_FORMAT_IS_UBWC(X) \
- (((X)->fetch_mode == MDP_FETCH_UBWC) && \
- ((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
+#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
+#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
+#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
+#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
+#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
@@ -331,8 +318,6 @@ enum dpu_3d_blend_mode {
* @bpp: bytes per pixel
* @alpha_enable: whether the format has an alpha channel
* @num_planes: number of planes (including meta data planes)
- * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
- * @flags: usage bit flags
* @tile_width: format tile width
* @tile_height: format tile height
*/
@@ -348,8 +333,6 @@ struct dpu_format {
u8 bpp;
u8 alpha_enable;
u8 num_planes;
- enum mdp_fetch_mode fetch_mode;
- unsigned long flags;
u16 tile_width;
u16 tile_height;
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 896fb576f5b5..d19fffa3d97e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -267,10 +267,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
- if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
+ if (!DPU_FORMAT_IS_LINEAR(fmt)) {
if (DPU_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
- src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
+ src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE |
ctx->ubwc->highest_bank_bit << 18);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index daaf6fe7e904..e6c9b4f2a0e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -294,14 +294,14 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
(fmt) ? fmt->base.pixel_format : 0,
- (fmt) ? fmt->fetch_mode : 0,
+ (fmt) ? fmt->base.fetch_mode : 0,
cfg.danger_lut,
cfg.safe_lut);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
pdpu->pipe - SSPP_VIG0,
fmt ? &fmt->base.pixel_format : NULL,
- fmt ? fmt->fetch_mode : -1,
+ fmt ? fmt->base.fetch_mode : -1,
cfg.danger_lut,
cfg.safe_lut);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index aa8342d93393..e40f6d1d5433 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -634,10 +634,10 @@ static uint32_t get_scale_config(const struct mdp_format *format,
uint32_t src, uint32_t dst, bool horz)
{
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
- bool scaling = format->is_yuv ? true : (src != dst);
+ bool yuv = MDP_FORMAT_IS_YUV(format);
+ bool scaling = yuv ? true : (src != dst);
uint32_t sub;
uint32_t ya_filter, uv_filter;
- bool yuv = format->is_yuv;
if (!scaling)
return 0;
@@ -666,7 +666,7 @@ static void calc_pixel_ext(const struct mdp_format *format,
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
bool horz)
{
- bool scaling = format->is_yuv ? true : (src != dst);
+ bool scaling = MDP_FORMAT_IS_YUV(format) ? true : (src != dst);
int i;
/*
@@ -696,7 +696,7 @@ static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
uint32_t roi_w = src_w;
uint32_t roi_h = src_h;
- if (format->is_yuv && i == COMP_1_2) {
+ if (MDP_FORMAT_IS_YUV(format) && i == COMP_1_2) {
roi_w /= info->hsub;
roi_h /= info->vsub;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 69ab5bcff1a9..30919641c813 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -63,7 +63,10 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
};
#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
- .base = { .pixel_format = DRM_FORMAT_ ## name }, \
+ .base = { \
+ .pixel_format = DRM_FORMAT_ ## name, \
+ .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
+ }, \
.bpc_a = BPC ## a ## A, \
.bpc_r = BPC ## r, \
.bpc_g = BPC ## g, \
@@ -75,7 +78,6 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.unpack_count = cnt, \
.fetch_type = fp, \
.chroma_sample = cs, \
- .is_yuv = yuv, \
}
#define BPC0A 0
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
new file mode 100644
index 000000000000..b1f199d4a079
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <[email protected]>
+ */
+
+#ifndef __MSM_FORMAT_H__
+#define __MSM_FORMAT_H__
+
+#include "mdp_common.xml.h"
+
+enum msm_format_flags {
+ MSM_FORMAT_FLAG_YUV_BIT,
+ MSM_FORMAT_FLAG_DX_BIT,
+ MSM_FORMAT_FLAG_COMPRESSED_BIT,
+};
+
+#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
+#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
+#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+
+struct msm_format {
+ uint32_t pixel_format;
+ unsigned long flags;
+ enum mdp_fetch_mode fetch_mode;
+};
+
+#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
+#define MSM_FORMAT_IS_DX(X) ((X)->flags & MSM_FORMAT_FLAG_DX)
+#define MSM_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
+#define MSM_FORMAT_IS_TILE(X) \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
+ !((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+#define MSM_FORMAT_IS_UBWC(X) \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
+ ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index d0718c16de3e..b6e68a343336 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -11,6 +11,7 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include "mdp_format.h"
#include "msm_drv.h"
#include "msm_kms.h"
#include "mdp_common.xml.h"
@@ -86,10 +87,9 @@ struct mdp_format {
uint8_t cpp, unpack_count;
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
- bool is_yuv;
};
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
-#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
+#define MDP_FORMAT_IS_YUV(mdp_format) (MSM_FORMAT_IS_YUV(&(mdp_format)->base))
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 65f213660452..f66faff17a60 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -239,10 +239,6 @@ struct msm_drm_private {
bool disable_err_irq;
};
-struct msm_format {
- uint32_t pixel_format;
-};
-
struct msm_pending_timer;
int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
--
2.39.2
Now as all subdrivers were converted to use common database of formats,
drop the get_format() callback and use mdp_get_format() directly.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
drivers/gpu/drm/msm/msm_fb.c | 2 +-
drivers/gpu/drm/msm/msm_kms.h | 4 ----
8 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b966c44ec835..ef69c2f408c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
- fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
+ fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
if (phys_enc->hw_cdm)
@@ -414,7 +414,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
ctl = phys_enc->hw_ctl;
fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
- fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
+ fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index de17bcbb8492..d3ea91c1d7d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -326,8 +326,7 @@ static void dpu_encoder_phys_wb_setup(
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
- dpu_fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base,
- format->pixel_format, wb_job->fb->modifier);
+ dpu_fmt = mdp_get_format(&phys_enc->dpu_kms->base, format->pixel_format, wb_job->fb->modifier);
DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
hw_wb->idx - WB_0, mode.name,
@@ -577,7 +576,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base,
+ wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base,
format->pixel_format, job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index cb30137443e8..1955848b1b78 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -982,7 +982,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = mdp_get_format,
.destroy = dpu_kms_destroy,
.snapshot = dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b92a13cc9b36..1c3a2657450c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -627,7 +627,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = priv->kms->funcs->get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
+ fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
/* should not happen ever */
if (!fmt)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4ba1cb74ad76..6e4e74f9d63d 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -151,7 +151,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.flush_commit = mdp4_flush_commit,
.wait_flush = mdp4_wait_flush,
.complete_commit = mdp4_complete_commit,
- .get_format = mdp_get_format,
.round_pixclk = mdp4_round_pixclk,
.destroy = mdp4_destroy,
},
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index a874fd95cc20..374704cce656 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -224,7 +224,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.prepare_commit = mdp5_prepare_commit,
.wait_flush = mdp5_wait_flush,
.complete_commit = mdp5_complete_commit,
- .get_format = mdp_get_format,
.destroy = mdp5_kms_destroy,
},
.set_irqmask = mdp5_set_irqmask,
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index ad4bb2b2cd66..09268e416843 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -181,7 +181,7 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
&mode_cmd->pixel_format);
n = info->num_planes;
- format = kms->funcs->get_format(kms, mode_cmd->pixel_format,
+ format = mdp_get_format(kms, mode_cmd->pixel_format,
mode_cmd->modifier[0]);
if (!format) {
DRM_DEV_ERROR(dev->dev, "unsupported pixel format: %p4cc\n",
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 0641f6111b93..1e0c54de3716 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -92,10 +92,6 @@ struct msm_kms_funcs {
* Format handling:
*/
- /* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */
- const struct msm_format *(*get_format)(struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers);
/* do format checking on format modified through fb_cmd2 modifiers */
int (*check_modified_format)(const struct msm_kms *kms,
const struct msm_format *msm_fmt,
--
2.39.2
Finally remove duplication between DPU and generic MDP code by merging
DPU format lists to the MDP format database.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 602 --------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 10 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 614 ++++++++++++++++++---
drivers/gpu/drm/msm/disp/mdp_format.h | 10 +
drivers/gpu/drm/msm/disp/mdp_kms.h | 2 -
drivers/gpu/drm/msm/msm_drv.h | 2 +
11 files changed, 571 insertions(+), 708 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index deb2f6b446d3..b966c44ec835 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
if (phys_enc->hw_cdm)
@@ -414,7 +414,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
ctl = phys_enc->hw_ctl;
fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 8b5a4a1c239e..de17bcbb8492 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -326,7 +326,8 @@ static void dpu_encoder_phys_wb_setup(
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
- dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier);
+ dpu_fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base,
+ format->pixel_format, wb_job->fb->modifier);
DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
hw_wb->idx - WB_0, mode.name,
@@ -576,8 +577,8 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = dpu_get_dpu_format_ext(
- format->pixel_format, job->fb->modifier);
+ wb_cfg->dest.format = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base,
+ format->pixel_format, job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 2bb1584920c6..6b1e9a617da3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -11,186 +11,11 @@
#include "dpu_kms.h"
#include "dpu_formats.h"
-#define DPU_UBWC_META_MACRO_W_H 16
-#define DPU_UBWC_META_BLOCK_SIZE 256
#define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096
-#define DPU_TILE_HEIGHT_DEFAULT 1
-#define DPU_TILE_HEIGHT_TILED 4
-#define DPU_TILE_HEIGHT_UBWC 4
-#define DPU_TILE_HEIGHT_NV12 8
-
#define DPU_MAX_IMG_WIDTH 0x3FFF
#define DPU_MAX_IMG_HEIGHT 0x3FFF
-/*
- * DPU supported format packing, bpp, and other format
- * information.
- * DPU currently only supports interleaved RGB formats
- * UBWC support for a pixel format is indicated by the flag,
- * there is additional meta data plane for such formats
- */
-
-#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
-bp, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), (e3) }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = CHROMA_FULL, \
- .unpack_count = uc, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
-alpha, bp, flg, fm, np, th) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), (e3) }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = CHROMA_FULL, \
- .unpack_count = uc, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-
-#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
-alpha, chroma, count, bp, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), (e3)}, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = count, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
-flg, fm, np, th) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
-flg, fm, np, th) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-
-#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
-flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PLANAR, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 1, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
/*
* struct dpu_media_color_map - maps drm format to media format
* @format: DRM base pixel format
@@ -201,375 +26,6 @@ struct dpu_media_color_map {
uint32_t color;
};
-static const struct msm_format dpu_format_map[] = {
- INTERLEAVED_RGB_FMT(ARGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGB888,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
- false, 3, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGR888,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 3, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGB565,
- 0, BPC5, BPC6, BPC5,
- C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGR565,
- 0, BPC5, BPC6, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB1555,
- BPC1A, BPC5, BPC5, BPC5,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR1555,
- BPC1A, BPC5, BPC5, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB1555,
- BPC1A, BPC5, BPC5, BPC5,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR1555,
- BPC1A, BPC5, BPC5, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB4444,
- BPC4A, BPC4, BPC4, BPC4,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR4444,
- BPC4A, BPC4, BPC4, BPC4,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB4444,
- BPC4A, BPC4, BPC4, BPC4,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR4444,
- BPC4A, BPC4, BPC4, BPC4,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- PSEUDO_YUV_FMT(NV12,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV21,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C1_B_Cb,
- CHROMA_420, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV16,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV61,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C1_B_Cb,
- CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT_LOOSE(P010,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(VYUY,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(UYVY,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(YUYV,
- 0, BPC8, BPC8, BPC8,
- C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(YVYU,
- 0, BPC8, BPC8, BPC8,
- C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PLANAR_YUV_FMT(YUV420,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 3),
-
- PLANAR_YUV_FMT(YVU420,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 3),
-};
-
-/*
- * UBWC formats table:
- * This table holds the UBWC formats supported.
- * If a compression ratio needs to be used for this or any other format,
- * the data will be passed by user-space.
- */
-static const struct msm_format dpu_format_map_ubwc[] = {
- INTERLEAVED_RGB_FMT_TILED(BGR565,
- 0, BPC5, BPC6, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(ABGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- /* ARGB8888 and ABGR8888 purposely have the same color
- * ordering. The hardware only supports ABGR8888 UBWC
- * natively.
- */
- INTERLEAVED_RGB_FMT_TILED(ARGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XBGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XRGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- /* XRGB2101010 and ARGB2101010 purposely have the same color
- * ordering. The hardware only supports ARGB2101010 UBWC
- * natively.
- */
- INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- PSEUDO_YUV_FMT_TILED(NV12,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_YUV |
- MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
-
- PSEUDO_YUV_FMT_TILED(P010,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_DX |
- MSM_FORMAT_FLAG_YUV |
- MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
-};
-
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
* Note: Not using the drm_format_*_subsampling since we have formats
*/
@@ -1010,61 +466,3 @@ int dpu_format_check_modified_format(
return 0;
}
-
-const struct msm_format *dpu_get_dpu_format_ext(
- const uint32_t format,
- const uint64_t modifier)
-{
- uint32_t i = 0;
- const struct msm_format *fmt = NULL;
- const struct msm_format *map = NULL;
- ssize_t map_size = 0;
-
- /*
- * Currently only support exactly zero or one modifier.
- * All planes use the same modifier.
- */
- DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
-
- switch (modifier) {
- case 0:
- map = dpu_format_map;
- map_size = ARRAY_SIZE(dpu_format_map);
- break;
- case DRM_FORMAT_MOD_QCOM_COMPRESSED:
- map = dpu_format_map_ubwc;
- map_size = ARRAY_SIZE(dpu_format_map_ubwc);
- DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
- (char *)&format);
- break;
- default:
- DPU_ERROR("unsupported format modifier %llX\n", modifier);
- return NULL;
- }
-
- for (i = 0; i < map_size; i++) {
- if (format == map[i].pixel_format) {
- fmt = &map[i];
- break;
- }
- }
-
- if (fmt == NULL)
- DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
- (char *)&format, modifier);
- else
- DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
- (char *)&format, modifier,
- MSM_FORMAT_IS_UBWC(fmt),
- MSM_FORMAT_IS_YUV(fmt));
-
- return fmt;
-}
-
-const struct msm_format *dpu_get_msm_format(
- struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers)
-{
- return dpu_get_dpu_format_ext(format, modifiers);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
index 78b585dca195..72ffd48fa6de 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -9,17 +9,6 @@
#include "msm_gem.h"
#include "dpu_hw_mdss.h"
-/**
- * dpu_get_dpu_format_ext() - Returns dpu format structure pointer.
- * @format: DRM FourCC Code
- * @modifiers: format modifier array from client, one per plane
- */
-const struct msm_format *dpu_get_dpu_format_ext(
- const uint32_t format,
- const uint64_t modifier);
-
-#define dpu_get_dpu_format(f) dpu_get_dpu_format_ext(f, 0)
-
/**
* dpu_find_format - validate if the pixel format is supported
* @format: dpu format
@@ -42,18 +31,6 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats,
return false;
}
-/**
- * dpu_get_msm_format - get an msm_format by its msm_format base
- * callback function registers with the msm_kms layer
- * @kms: kms driver
- * @format: DRM FourCC Code
- * @modifiers: data layout modifier
- */
-const struct msm_format *dpu_get_msm_format(
- struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers);
-
/**
* dpu_format_check_modified_format - validate format and buffers for
* dpu non-standard, i.e. modified format
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index d40572b251b1..66759623fc42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -270,16 +270,6 @@ enum dpu_vbif {
VBIF_MAX,
};
-/**
- * DPU HW,Component order color map
- */
-enum {
- C0_G_Y = 0,
- C1_B_Cb = 1,
- C2_R_Cr = 2,
- C3_ALPHA = 3
-};
-
/**
* enum dpu_3d_blend_mode
* Desribes how the 3d data is blended
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9a1fe6868979..cb30137443e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -982,7 +982,7 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = dpu_get_msm_format,
+ .get_format = mdp_get_format,
.destroy = dpu_kms_destroy,
.snapshot = dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 4de5c37d6e92..b92a13cc9b36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -617,6 +617,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
{
const struct msm_format *fmt;
const struct drm_plane *plane = &pdpu->base;
+ struct msm_drm_private *priv = plane->dev->dev_private;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
@@ -626,7 +627,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
+ fmt = priv->kms->funcs->get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
/* should not happen ever */
if (!fmt)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index b9f0b13d25d5..426782d50cb4 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -62,87 +62,573 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
};
-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, c, cnt, fp, cs, yuv) { \
- .pixel_format = DRM_FORMAT_ ## name, \
- .bpc_a = BPC ## a ## A, \
- .bpc_r_cr = BPC ## r, \
- .bpc_g_y = BPC ## g, \
- .bpc_b_cb = BPC ## b, \
- .element = { e0, e1, e2, e3 }, \
- .fetch_type = fp, \
- .chroma_sample = cs, \
- .alpha_enable = alpha, \
- .unpack_count = cnt, \
- .bpp = c, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (yuv ? MSM_FORMAT_FLAG_YUV : 0), \
+#define MDP_TILE_HEIGHT_DEFAULT 1
+#define MDP_TILE_HEIGHT_UBWC 4
+#define MDP_TILE_HEIGHT_NV12 8
+
+#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
+bp, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = uc, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
+alpha, bp, flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = uc, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
+
+#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
+alpha, chroma, count, bp, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), (e3)}, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = count, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
+flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
+
+#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
-#define BPC0A 0
-
-static const struct msm_format formats[] = {
- /* name a r g b e0 e1 e2 e3 alpha cpp cnt ... */
- FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, 3, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, 3, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, 2, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, 2, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
+#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
+flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
+
+#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
+flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PLANAR, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 1, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+static const struct msm_format mdp_formats[] = {
+ INTERLEAVED_RGB_FMT(ARGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGB888,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+ false, 3, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGR888,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 3, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGB565,
+ 0, BPC5, BPC6, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGR565,
+ 0, BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
/* --- RGB formats above / YUV formats below this line --- */
/* 2 plane YUV */
- FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
- FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
+ PSEUDO_YUV_FMT(NV12,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV21,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV16,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV61,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT_LOOSE(P010,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
/* 1 plane YUV */
- FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
+ INTERLEAVED_YUV_FMT(VYUY,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(UYVY,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(YUYV,
+ 0, BPC8, BPC8, BPC8,
+ C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(YVYU,
+ 0, BPC8, BPC8, BPC8,
+ C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
/* 3 plane YUV */
- FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, 1, 1,
- MDP_PLANE_PLANAR, CHROMA_420, true),
- FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, 1, 1,
- MDP_PLANE_PLANAR, CHROMA_420, true),
+ PLANAR_YUV_FMT(YUV420,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb, C0_G_Y,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
+
+ PLANAR_YUV_FMT(YVU420,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr, C0_G_Y,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
+};
+
+/*
+ * UBWC formats table:
+ * This table holds the UBWC formats supported.
+ * If a compression ratio needs to be used for this or any other format,
+ * the data will be passed by user-space.
+ */
+static const struct msm_format mdp_formats_ubwc[] = {
+ INTERLEAVED_RGB_FMT_TILED(BGR565,
+ 0, BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 2, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(ABGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ /* ARGB8888 and ABGR8888 purposely have the same color
+ * ordering. The hardware only supports ABGR8888 UBWC
+ * natively.
+ */
+ INTERLEAVED_RGB_FMT_TILED(ARGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XBGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XRGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ /* XRGB2101010 and ARGB2101010 purposely have the same color
+ * ordering. The hardware only supports ARGB2101010 UBWC
+ * natively.
+ */
+ INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ PSEUDO_YUV_FMT_TILED(NV12,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_NV12),
+
+ PSEUDO_YUV_FMT_TILED(P010,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_DX |
+ MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_UBWC),
};
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
uint64_t modifier)
{
+ const struct msm_format *map = NULL;
+ ssize_t map_size;
int i;
- for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct msm_format *f = &formats[i];
+
+ switch (modifier) {
+ case 0:
+ map = mdp_formats;
+ map_size = ARRAY_SIZE(mdp_formats);
+ break;
+ case DRM_FORMAT_MOD_QCOM_COMPRESSED:
+ map = mdp_formats_ubwc;
+ map_size = ARRAY_SIZE(mdp_formats_ubwc);
+ break;
+ default:
+ drm_err(kms->dev, "unsupported format modifier %llX\n", modifier);
+ return NULL;
+ }
+
+ for (i = 0; i < map_size; i++) {
+ const struct msm_format *f = &map[i];
+
if (f->pixel_format == format)
return f;
}
+
+ drm_err(kms->dev, "unsupported fmt: %p4cc modifier 0x%llX\n",
+ &format, modifier);
+
return NULL;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
index d17f63c045a7..a00d646ff4d4 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.h
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -24,6 +24,16 @@ enum msm_format_flags {
#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
+/**
+ * DPU HW,Component order color map
+ */
+enum {
+ C0_G_Y = 0,
+ C1_B_Cb = 1,
+ C2_R_Cr = 2,
+ C3_ALPHA = 3
+};
+
/**
* struct msm_format: defines the format configuration
* @pixel_format: format fourcc
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index a2d5af5c65e5..068fbeac6edb 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -78,8 +78,6 @@ void mdp_irq_update(struct mdp_kms *mdp_kms);
* pixel format helpers:
*/
-const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
-
/* MDP capabilities */
#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index f66faff17a60..d9c1bce567d7 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -239,6 +239,8 @@ struct msm_drm_private {
bool disable_err_irq;
};
+const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
+
struct msm_pending_timer;
int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
--
2.39.2
Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.
Reviewed-by: Abhinav Kumar <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 184 +++++++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 41 +----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 14 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 74 ++++-----
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 26 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 54 +++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ++--
drivers/gpu/drm/msm/disp/mdp_format.h | 28 ++++
drivers/gpu/drm/msm/disp/mdp_kms.h | 13 --
28 files changed, 296 insertions(+), 305 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 88c2e51ab166..9f2164782844 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -320,7 +320,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, struct dpu_format *format)
+ struct dpu_plane_state *pstate, const struct msm_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
@@ -363,7 +363,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- &format->base.pixel_format, format->alpha_enable, blend_op);
+ &format->pixel_format, format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -395,7 +395,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
struct dpu_crtc_mixer *mixer,
u32 num_mixers,
enum dpu_stage stage,
- struct dpu_format *format,
+ const struct msm_format *format,
uint64_t modifier,
struct dpu_sw_pipe *pipe,
unsigned int stage_idx,
@@ -412,7 +412,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, to_dpu_plane_state(state), stage_idx,
- format->base.pixel_format,
+ format->pixel_format,
modifier);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
@@ -440,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
- struct dpu_format *format;
+ const struct msm_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
uint32_t lm_idx;
@@ -459,7 +459,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ format = msm_framebuffer_format(pstate->base.fb);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 43431cb55421..119f3ea50a7c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -675,7 +675,7 @@ static int dpu_encoder_virt_atomic_check(
if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
fb = conn_state->writeback_job->fb;
- if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb))))
+ if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
topology.needs_cdm = true;
} else if (disp_info->intf_type == INTF_DP) {
if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
@@ -2184,7 +2184,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
}
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
- const struct dpu_format *dpu_fmt,
+ const struct msm_format *dpu_fmt,
u32 output_type)
{
struct dpu_hw_cdm *hw_cdm;
@@ -2202,9 +2202,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
if (!hw_cdm)
return;
- if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
+ if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
- &dpu_fmt->base.pixel_format);
+ &dpu_fmt->pixel_format);
if (hw_cdm->ops.bind_pingpong_blk)
hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
@@ -2217,7 +2217,7 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
cdm_cfg->output_fmt = dpu_fmt;
cdm_cfg->output_type = output_type;
- cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
+ cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
@@ -2246,7 +2246,7 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
DRMID(phys_enc->parent), cdm_cfg->output_width,
- cdm_cfg->output_height, &cdm_cfg->output_fmt->base.pixel_format,
+ cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
cdm_cfg->output_type, cdm_cfg->output_bit_depth,
cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 98d1b64a43e8..002e89cc1705 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -393,7 +393,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
* @output_type: HDMI/WB
*/
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
- const struct dpu_format *dpu_fmt,
+ const struct msm_format *dpu_fmt,
u32 output_type);
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d9e7dbf0499c..deb2f6b446d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -235,7 +235,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
{
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
- const struct dpu_format *fmt = NULL;
+ const struct msm_format *fmt = NULL;
u32 fmt_fourcc;
unsigned long lock_flags;
struct dpu_hw_intf_cfg intf_cfg = { 0 };
@@ -409,7 +409,7 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
{
struct dpu_hw_ctl *ctl;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
u32 fmt_fourcc;
ctl = phys_enc->hw_ctl;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index ff41493147ab..8b5a4a1c239e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -322,7 +322,7 @@ static void dpu_encoder_phys_wb_setup(
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
struct drm_writeback_job *wb_job;
const struct msm_format *format;
- const struct dpu_format *dpu_fmt;
+ const struct msm_format *dpu_fmt;
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
@@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 0c2afded0e56..855f0d29c387 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -34,18 +34,21 @@
#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
bp, flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_INTERLEAVED, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -53,18 +56,21 @@ bp, flg, fm, np) \
#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
alpha, bp, flg, fm, np, th) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_INTERLEAVED, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -73,36 +79,42 @@ alpha, bp, flg, fm, np, th) \
#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
alpha, chroma, count, bp, flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_INTERLEAVED, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -110,36 +122,42 @@ alpha, chroma, count, bp, flg, fm, np) \
#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -147,18 +165,21 @@ flg, fm, np, th) \
#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -167,18 +188,21 @@ flg, fm, np, th) \
#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PLANAR, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PLANAR, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -193,7 +217,7 @@ struct dpu_media_color_map {
uint32_t color;
};
-static const struct dpu_format dpu_format_map[] = {
+static const struct msm_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(ARGB8888,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
@@ -483,7 +507,7 @@ static const struct dpu_format dpu_format_map[] = {
* If a compression ratio needs to be used for this or any other format,
* the data will be passed by user-space.
*/
-static const struct dpu_format dpu_format_map_ubwc[] = {
+static const struct msm_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
@@ -593,7 +617,7 @@ static void _dpu_get_v_h_subsample_rate(
}
}
-static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
+static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
{
static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
@@ -609,9 +633,9 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
int color_fmt = -1;
int i;
- if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
- fmt->base.pixel_format == DRM_FORMAT_P010) {
- if (DPU_FORMAT_IS_DX(fmt)) {
+ if (fmt->pixel_format == DRM_FORMAT_NV12 ||
+ fmt->pixel_format == DRM_FORMAT_P010) {
+ if (MSM_FORMAT_IS_DX(fmt)) {
if (fmt->unpack_tight)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
else
@@ -622,7 +646,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i)
- if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) {
+ if (fmt->pixel_format == dpu_media_ubwc_map[i].format) {
color_fmt = dpu_media_ubwc_map[i].color;
break;
}
@@ -630,14 +654,14 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
static int _dpu_format_get_plane_sizes_ubwc(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout)
{
int i;
int color;
- bool meta = DPU_FORMAT_IS_UBWC(fmt);
+ bool meta = MSM_FORMAT_IS_UBWC(fmt);
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
layout->format = fmt;
@@ -648,11 +672,11 @@ static int _dpu_format_get_plane_sizes_ubwc(
color = _dpu_format_get_media_color_ubwc(fmt);
if (color < 0) {
DRM_ERROR("UBWC format not supported for fmt: %p4cc\n",
- &fmt->base.pixel_format);
+ &fmt->pixel_format);
return -EINVAL;
}
- if (DPU_FORMAT_IS_YUV(layout->format)) {
+ if (MSM_FORMAT_IS_YUV(layout->format)) {
uint32_t y_sclines, uv_sclines;
uint32_t y_meta_scanlines = 0;
uint32_t uv_meta_scanlines = 0;
@@ -709,7 +733,7 @@ static int _dpu_format_get_plane_sizes_ubwc(
}
static int _dpu_format_get_plane_sizes_linear(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout,
@@ -724,7 +748,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->num_planes = fmt->num_planes;
/* Due to memset above, only need to set planes of interest */
- if (fmt->fetch_planes == MDP_PLANE_INTERLEAVED) {
+ if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) {
layout->num_planes = 1;
layout->plane_size[0] = width * height * layout->format->bpp;
layout->plane_pitch[0] = width * layout->format->bpp;
@@ -742,8 +766,8 @@ static int _dpu_format_get_plane_sizes_linear(
return -EINVAL;
}
- if ((fmt->base.pixel_format == DRM_FORMAT_NV12) &&
- (DPU_FORMAT_IS_DX(fmt)))
+ if ((fmt->pixel_format == DRM_FORMAT_NV12) &&
+ (MSM_FORMAT_IS_DX(fmt)))
bpp = 2;
layout->plane_pitch[0] = width * bpp;
layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample;
@@ -751,7 +775,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->plane_size[1] = layout->plane_pitch[1] *
(height / v_subsample);
- if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
layout->num_planes = 2;
layout->plane_size[1] *= 2;
layout->plane_pitch[1] *= 2;
@@ -781,7 +805,7 @@ static int _dpu_format_get_plane_sizes_linear(
}
static int dpu_format_get_plane_sizes(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t w,
const uint32_t h,
struct dpu_hw_fmt_layout *layout,
@@ -797,7 +821,7 @@ static int dpu_format_get_plane_sizes(
return -ERANGE;
}
- if (DPU_FORMAT_IS_UBWC(fmt) || DPU_FORMAT_IS_TILE(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout);
return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches);
@@ -823,10 +847,10 @@ static int _dpu_format_populate_addrs_ubwc(
return -EFAULT;
}
- meta = DPU_FORMAT_IS_UBWC(layout->format);
+ meta = MSM_FORMAT_IS_UBWC(layout->format);
/* Per-format logic for verifying active planes */
- if (DPU_FORMAT_IS_YUV(layout->format)) {
+ if (MSM_FORMAT_IS_YUV(layout->format)) {
/************************************************/
/* UBWC ** */
/* buffer ** DPU PLANE */
@@ -942,7 +966,7 @@ int dpu_format_populate_layout(
return -ERANGE;
}
- layout->format = to_dpu_format(msm_framebuffer_format(fb));
+ layout->format = msm_framebuffer_format(fb);
/* Populate the plane sizes etc via get_format */
ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height,
@@ -951,8 +975,8 @@ int dpu_format_populate_layout(
return ret;
/* Populate the addresses given the fb */
- if (DPU_FORMAT_IS_UBWC(layout->format) ||
- DPU_FORMAT_IS_TILE(layout->format))
+ if (MSM_FORMAT_IS_UBWC(layout->format) ||
+ MSM_FORMAT_IS_TILE(layout->format))
ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout);
else
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
@@ -962,23 +986,21 @@ int dpu_format_populate_layout(
int dpu_format_check_modified_format(
const struct msm_kms *kms,
- const struct msm_format *msm_fmt,
+ const struct msm_format *fmt,
const struct drm_mode_fb_cmd2 *cmd,
struct drm_gem_object **bos)
{
const struct drm_format_info *info;
- const struct dpu_format *fmt;
struct dpu_hw_fmt_layout layout;
uint32_t bos_total_size = 0;
int ret, i;
- if (!msm_fmt || !cmd || !bos) {
+ if (!fmt || !cmd || !bos) {
DRM_ERROR("invalid arguments\n");
return -EINVAL;
}
- fmt = to_dpu_format(msm_fmt);
- info = drm_format_info(fmt->base.pixel_format);
+ info = drm_format_info(fmt->pixel_format);
if (!info)
return -EINVAL;
@@ -1005,13 +1027,13 @@ int dpu_format_check_modified_format(
return 0;
}
-const struct dpu_format *dpu_get_dpu_format_ext(
+const struct msm_format *dpu_get_dpu_format_ext(
const uint32_t format,
const uint64_t modifier)
{
uint32_t i = 0;
- const struct dpu_format *fmt = NULL;
- const struct dpu_format *map = NULL;
+ const struct msm_format *fmt = NULL;
+ const struct msm_format *map = NULL;
ssize_t map_size = 0;
/*
@@ -1037,7 +1059,7 @@ const struct dpu_format *dpu_get_dpu_format_ext(
}
for (i = 0; i < map_size; i++) {
- if (format == map[i].base.pixel_format) {
+ if (format == map[i].pixel_format) {
fmt = &map[i];
break;
}
@@ -1049,8 +1071,8 @@ const struct dpu_format *dpu_get_dpu_format_ext(
else
DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
(char *)&format, modifier,
- DPU_FORMAT_IS_UBWC(fmt),
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_UBWC(fmt),
+ MSM_FORMAT_IS_YUV(fmt));
return fmt;
}
@@ -1060,9 +1082,5 @@ const struct msm_format *dpu_get_msm_format(
const uint32_t format,
const uint64_t modifiers)
{
- const struct dpu_format *fmt = dpu_get_dpu_format_ext(format,
- modifiers);
- if (fmt)
- return &fmt->base;
- return NULL;
+ return dpu_get_dpu_format_ext(format, modifiers);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
index 84b8b3289f18..78b585dca195 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -14,7 +14,7 @@
* @format: DRM FourCC Code
* @modifiers: format modifier array from client, one per plane
*/
-const struct dpu_format *dpu_get_dpu_format_ext(
+const struct msm_format *dpu_get_dpu_format_ext(
const uint32_t format,
const uint64_t modifier);
@@ -43,7 +43,7 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats,
}
/**
- * dpu_get_msm_format - get an dpu_format by its msm_format base
+ * dpu_get_msm_format - get an msm_format by its msm_format base
* callback function registers with the msm_kms layer
* @kms: kms driver
* @format: DRM FourCC Code
@@ -58,7 +58,7 @@ const struct msm_format *dpu_get_msm_format(
* dpu_format_check_modified_format - validate format and buffers for
* dpu non-standard, i.e. modified format
* @kms: kms driver
- * @msm_fmt: pointer to the msm_fmt base pointer of an dpu_format
+ * @msm_fmt: pointer to the msm_fmt base pointer of an msm_format
* @cmd: fb_cmd2 structure user request
* @bos: gem buffer object list
*
@@ -85,4 +85,4 @@ int dpu_format_populate_layout(
struct drm_framebuffer *fb,
struct dpu_hw_fmt_layout *fmtl);
-#endif /*_DPU_FORMATS_H */
+#endif /*_MSM_FORMATS_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
index 3602cbda793e..55d2768a6d4d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
@@ -170,7 +170,7 @@ static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *
static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
u32 opmode = 0;
u32 csc = 0;
@@ -179,7 +179,7 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
fmt = cdm->output_fmt;
- if (!DPU_FORMAT_IS_YUV(fmt))
+ if (!MSM_FORMAT_IS_YUV(fmt))
return -EINVAL;
dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
index 348424df87c6..ec71c9886d75 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
@@ -19,7 +19,7 @@ struct dpu_hw_cdm;
* @output_bit_depth: output bit-depth of CDM block
* @h_cdwn_type: downsample type used for horizontal pixels
* @v_cdwn_type: downsample type used for vertical pixels
- * @output_fmt: handle to dpu_format of CDM block
+ * @output_fmt: handle to msm_format of CDM block
* @csc_cfg: handle to CSC matrix programmed for CDM block
* @output_type: interface to which CDM is paired (HDMI/WB)
* @pp_id: ping-pong block to which CDM is bound to
@@ -30,7 +30,7 @@ struct dpu_hw_cdm_cfg {
u32 output_bit_depth;
u32 h_cdwn_type;
u32 v_cdwn_type;
- const struct dpu_format *output_fmt;
+ const struct msm_format *output_fmt;
const struct dpu_csc_cfg *csc_cfg;
u32 output_type;
int pp_id;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 55c7e941e163..0fa0d3b18dae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -98,7 +98,7 @@
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
const struct dpu_hw_intf_timing_params *p,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
u32 hsync_period, vsync_period;
@@ -194,10 +194,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
(p->vsync_polarity << 1) | /* VSYNC Polarity */
(p->hsync_polarity << 0); /* HSYNC Polarity */
- if (!DPU_FORMAT_IS_YUV(fmt))
- panel_format = (fmt->bits[C0_G_Y] |
- (fmt->bits[C1_B_Cb] << 2) |
- (fmt->bits[C2_R_Cr] << 4) |
+ if (!MSM_FORMAT_IS_YUV(fmt))
+ panel_format = (fmt->bpc_g_y |
+ (fmt->bpc_b_cb << 2) |
+ (fmt->bpc_r_cr << 4) |
(0x21 << 8));
else
/* Interface treats all the pixel data in RGB888 format */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 6f4c87244f94..f9015c67a574 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -81,7 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct dpu_format *fmt);
+ const struct msm_format *fmt);
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_prog_fetch *fetch);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index aa639a43941f..d40572b251b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -37,12 +37,6 @@
#define DPU_MAX_DE_CURVES 3
#endif
-#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
-#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
-#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
-#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
-#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
-
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
@@ -305,39 +299,6 @@ enum dpu_3d_blend_mode {
BLEND_3D_MAX
};
-/** struct dpu_format - defines the format configuration which
- * allows DPU HW to correctly fetch and decode the format
- * @base: base msm_format structure containing fourcc code
- * @fetch_planes: how the color components are packed in pixel format
- * @element: element color ordering
- * @bits: element bit widths
- * @chroma_sample: chroma sub-samplng type
- * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
- * @unpack_tight: 0 for loose, 1 for tight
- * @unpack_count: 0 = 1 component, 1 = 2 component
- * @bpp: bytes per pixel
- * @alpha_enable: whether the format has an alpha channel
- * @num_planes: number of planes (including meta data planes)
- * @tile_width: format tile width
- * @tile_height: format tile height
- */
-struct dpu_format {
- struct msm_format base;
- enum mdp_fetch_type fetch_planes;
- u8 element[DPU_MAX_PLANES];
- u8 bits[DPU_MAX_PLANES];
- enum mdp_chroma_samp_type chroma_sample;
- u8 unpack_align_msb;
- u8 unpack_tight;
- u8 unpack_count;
- u8 bpp;
- u8 alpha_enable;
- u8 num_planes;
- u16 tile_width;
- u16 tile_height;
-};
-#define to_dpu_format(x) container_of(x, struct dpu_format, base)
-
/**
* struct dpu_hw_fmt_layout - format information of the source pixel data
* @format: pixel format parameters
@@ -350,7 +311,7 @@ struct dpu_format {
* @plane_pitch: pitch of each plane
*/
struct dpu_hw_fmt_layout {
- const struct dpu_format *format;
+ const struct msm_format *format;
uint32_t num_planes;
uint32_t width;
uint32_t height;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index d19fffa3d97e..fdd77dc51776 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -206,7 +206,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
* Setup source pixel format, flip,
*/
static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, u32 flags)
+ const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
@@ -247,14 +247,14 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
chroma_samp = CHROMA_H2V1;
}
- src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
- (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
- (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
+ src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) |
+ (fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) |
+ (fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0);
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
- if (fmt->alpha_enable && fmt->fetch_planes == MDP_PLANE_INTERLEAVED)
+ if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@@ -267,10 +267,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
- if (!DPU_FORMAT_IS_LINEAR(fmt)) {
- if (DPU_FORMAT_IS_UBWC(fmt))
+ if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
+ if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
- src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */
+ src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE |
ctx->ubwc->highest_bank_bit << 18);
@@ -295,7 +295,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
break;
case UBWC_4_0:
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+ MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
}
@@ -303,20 +303,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
/* if this is YUV pixel format, enable CSC */
- if (DPU_FORMAT_IS_YUV(fmt))
+ if (MSM_FORMAT_IS_YUV(fmt))
src_format |= BIT(15);
- if (DPU_FORMAT_IS_DX(fmt))
+ if (MSM_FORMAT_IS_DX(fmt))
src_format |= BIT(14);
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
_sspp_setup_csc10_opmode(ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_YUV(fmt));
DPU_REG_WRITE(c, format_off, src_format);
DPU_REG_WRITE(c, unpack_pat_off, unpack);
@@ -385,7 +385,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct dpu_format *format)
+ const struct msm_format *format)
{
if (!ctx || !scaler3_cfg)
return;
@@ -556,7 +556,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index b7dc52312c39..4a910b808687 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -183,7 +183,7 @@ struct dpu_hw_sspp_ops {
* @flags: Extra flags for format config
*/
void (*setup_format)(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, u32 flags);
+ const struct msm_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
@@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct dpu_format *format);
+ const struct msm_format *format);
/**
* setup_cdp - setup client driven prefetch
@@ -288,7 +288,7 @@ struct dpu_hw_sspp_ops {
* @enable: whether the CDP should be enabled for this pipe
*/
void (*setup_cdp)(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable);
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index dd475827314e..486be346d40d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -282,7 +282,7 @@ static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
- const struct dpu_format *format)
+ const struct msm_format *format)
{
u32 op_mode = 0;
u32 phase_init, preload, src_y_rgb, src_uv, dst;
@@ -293,7 +293,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
op_mode |= BIT(0);
op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
- if (format && DPU_FORMAT_IS_YUV(format)) {
+ if (format && MSM_FORMAT_IS_YUV(format)) {
op_mode |= BIT(12);
op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
}
@@ -367,7 +367,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
end:
- if (format && !DPU_FORMAT_IS_DX(format))
+ if (format && !MSM_FORMAT_IS_DX(format))
op_mode |= BIT(14);
if (format && format->alpha_enable) {
@@ -522,16 +522,16 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
#define CDP_PRELOAD_AHEAD_64 BIT(3)
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
- const struct dpu_format *fmt, bool enable)
+ const struct msm_format *fmt, bool enable)
{
u32 cdp_cntl = CDP_PRELOAD_AHEAD_64;
if (enable)
cdp_cntl |= CDP_ENABLE;
- if (DPU_FORMAT_IS_UBWC(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt))
cdp_cntl |= CDP_UBWC_META_ENABLE;
- if (DPU_FORMAT_IS_UBWC(fmt) ||
- DPU_FORMAT_IS_TILE(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt) ||
+ MSM_FORMAT_IS_TILE(fmt))
cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE;
DPU_REG_WRITE(c, offset, cdp_cntl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 64ded69fa903..67b08e99335d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -344,14 +344,14 @@ void *dpu_hw_util_get_dir(void);
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
- const struct dpu_format *format);
+ const struct msm_format *format);
void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
u32 csc_reg_off,
const struct dpu_csc_cfg *data, bool csc10);
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
- const struct dpu_format *fmt, bool enable);
+ const struct msm_format *fmt, bool enable);
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
u32 total_fl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index e75995f7fcea..2fdf1b703042 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -67,7 +67,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
struct dpu_hw_wb_cfg *data)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
- const struct dpu_format *fmt = data->dest.format;
+ const struct msm_format *fmt = data->dest.format;
u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
u32 write_config = 0;
u32 opmode = 0;
@@ -76,20 +76,20 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
chroma_samp = fmt->chroma_sample;
dst_format = (chroma_samp << 23) |
- (fmt->fetch_planes << 19) |
- (fmt->bits[C3_ALPHA] << 6) |
- (fmt->bits[C2_R_Cr] << 4) |
- (fmt->bits[C1_B_Cb] << 2) |
- (fmt->bits[C0_G_Y] << 0);
+ (fmt->fetch_type << 19) |
+ (fmt->bpc_a << 6) |
+ (fmt->bpc_r_cr << 4) |
+ (fmt->bpc_b_cb << 2) |
+ (fmt->bpc_g_y << 0);
- if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
+ if (fmt->bpc_a || fmt->alpha_enable) {
dst_format |= BIT(8); /* DSTC3_EN */
if (!fmt->alpha_enable ||
!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
dst_format |= BIT(14); /* DST_ALPHA_X */
}
- if (DPU_FORMAT_IS_YUV(fmt))
+ if (MSM_FORMAT_IS_YUV(fmt))
dst_format |= BIT(15);
pattern = (fmt->element[3] << 24) |
@@ -149,7 +149,7 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
}
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable)
{
if (!ctx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
index e671796ea379..37497473e16c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
@@ -46,7 +46,7 @@ struct dpu_hw_wb_ops {
struct dpu_hw_qos_cfg *cfg);
void (*setup_cdp)(struct dpu_hw_wb *ctx,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable);
bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index e6c9b4f2a0e0..4de5c37d6e92 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -113,7 +113,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
* Prefill BW Equation: line src bytes * line_time
*/
static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const struct drm_display_mode *mode,
struct dpu_sw_pipe_cfg *pipe_cfg)
{
@@ -195,7 +195,7 @@ static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
enum dpu_qos_lut_usage lut_usage,
- const struct dpu_format *fmt, u32 src_width)
+ const struct msm_format *fmt, u32 src_width)
{
struct dpu_plane *pdpu;
u32 fixed_buff_size;
@@ -214,7 +214,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/* FIXME: in multirect case account for the src_width of all the planes */
- if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
if (fmt->chroma_sample == CHROMA_420) {
/* NV12 */
total_fl = (fixed_buff_size / 2) /
@@ -236,7 +236,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
pipe->sspp->idx - SSPP_VIG0,
- &fmt->base.pixel_format,
+ &fmt->pixel_format,
src_width, total_fl);
return total_fl;
@@ -251,7 +251,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
+ const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_hw_qos_cfg cfg;
@@ -260,7 +260,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
if (!pdpu->is_rt_pipe) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
- if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
+ if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
else
lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
@@ -284,24 +284,24 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
pdpu->is_rt_pipe);
trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
+ (fmt) ? fmt->pixel_format : 0,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
pdpu->pipe - SSPP_VIG0,
- fmt ? &fmt->base.pixel_format : NULL,
+ fmt ? &fmt->pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
- (fmt) ? fmt->base.fetch_mode : 0,
+ (fmt) ? fmt->pixel_format : 0,
+ (fmt) ? fmt->fetch_mode : 0,
cfg.danger_lut,
cfg.safe_lut);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
pdpu->pipe - SSPP_VIG0,
- fmt ? &fmt->base.pixel_format : NULL,
- fmt ? fmt->base.fetch_mode : -1,
+ fmt ? &fmt->pixel_format : NULL,
+ fmt ? fmt->fetch_mode : -1,
cfg.danger_lut,
cfg.safe_lut);
@@ -425,7 +425,7 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
unsigned int rotation)
{
@@ -477,7 +477,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
}
}
- if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
+ if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
&& (src_w == dst_w))
return;
@@ -510,11 +510,11 @@ static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
}
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
const struct dpu_csc_cfg *csc_ptr;
- if (!DPU_FORMAT_IS_YUV(fmt))
+ if (!MSM_FORMAT_IS_YUV(fmt))
return NULL;
if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
@@ -526,12 +526,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
}
static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, bool color_fill,
+ const struct msm_format *fmt, bool color_fill,
struct dpu_sw_pipe_cfg *pipe_cfg,
unsigned int rotation)
{
struct dpu_hw_sspp *pipe_hw = pipe->sspp;
- const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
@@ -577,7 +577,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
struct dpu_sw_pipe *pipe,
struct drm_rect *dst_rect,
u32 fill_color,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
struct dpu_sw_pipe_cfg pipe_cfg;
@@ -615,7 +615,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
uint32_t color, uint32_t alpha)
{
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
const struct drm_plane *plane = &pdpu->base;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
@@ -704,7 +704,7 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
const struct dpu_sspp_sub_blks *sblk,
- struct drm_rect src, const struct dpu_format *fmt)
+ struct drm_rect src, const struct msm_format *fmt)
{
size_t num_formats;
const u32 *supported_formats;
@@ -723,8 +723,8 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
supported_formats = sblk->rotation_cfg->rot_format_list;
num_formats = sblk->rotation_cfg->rot_num_formats;
- if (!DPU_FORMAT_IS_UBWC(fmt) ||
- !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
+ if (!MSM_FORMAT_IS_UBWC(fmt) ||
+ !dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
return -EINVAL;
return 0;
@@ -733,15 +733,15 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const struct drm_display_mode *mode)
{
uint32_t min_src_size;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
- min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
+ min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
- if (DPU_FORMAT_IS_YUV(fmt) &&
+ if (MSM_FORMAT_IS_YUV(fmt) &&
(!pipe->sspp->cap->sblk->scaler_blk.len ||
!pipe->sspp->cap->sblk->csc_blk.len)) {
DPU_DEBUG_PLANE(pdpu,
@@ -758,7 +758,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
}
/* valid yuv image */
- if (DPU_FORMAT_IS_YUV(fmt) &&
+ if (MSM_FORMAT_IS_YUV(fmt) &&
(pipe_cfg->src_rect.x1 & 0x1 ||
pipe_cfg->src_rect.y1 & 0x1 ||
drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
@@ -798,7 +798,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_sw_pipe *pipe = &pstate->pipe;
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
const struct drm_crtc_state *crtc_state = NULL;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct drm_rect fb_rect = { 0 };
@@ -858,7 +858,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -E2BIG;
}
- fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ fmt = msm_framebuffer_format(new_plane_state->fb);
max_linewidth = pdpu->catalog->caps->max_linewidth;
@@ -870,7 +870,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
* full width is more than max_linewidth, thus each rect is
* wider than allowed.
*/
- if (DPU_FORMAT_IS_UBWC(fmt) &&
+ if (MSM_FORMAT_IS_UBWC(fmt) &&
drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
@@ -887,7 +887,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
(!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
!test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
- DPU_FORMAT_IS_YUV(fmt)) {
+ MSM_FORMAT_IS_YUV(fmt)) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
return -E2BIG;
@@ -945,8 +945,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
{
- const struct dpu_format *format =
- to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(pdpu->base.state->fb);
const struct dpu_csc_cfg *csc_ptr;
if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
@@ -1017,7 +1017,7 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error)
static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
int frame_rate,
struct dpu_hw_fmt_layout *layout)
{
@@ -1095,8 +1095,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
- const struct dpu_format *fmt =
- to_dpu_format(msm_framebuffer_format(fb));
+ const struct msm_format *fmt =
+ msm_framebuffer_format(fb);
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
@@ -1120,7 +1120,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
crtc->base.id, DRM_RECT_ARG(&state->dst),
- &fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
+ &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
drm_mode_vrefresh(&crtc->mode),
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 75f93e346282..b8610aa806ea 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -182,8 +182,8 @@ static void blend_setup(struct drm_crtc *crtc)
enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
int idx = idxs[pipe_id];
if (idx > 0) {
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(plane->state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(plane->state->fb);
alpha[idx-1] = format->alpha_enable;
}
}
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index cebe20c82a54..0bae90d3f21e 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -218,7 +218,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
- const struct mdp_format *format;
+ const struct msm_format *format;
uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
@@ -241,7 +241,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
fb->base.id, src_x, src_y, src_w, src_h,
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
- format = to_mdp_format(msm_framebuffer_format(fb));
+ format = msm_framebuffer_format(fb);
if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
@@ -267,7 +267,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_w > src_w)
sel_unit = SCALE_PIXEL_RPT;
else if (crtc_w <= (src_w / 4))
@@ -283,7 +283,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_h > src_h)
sel_unit = SCALE_PIXEL_RPT;
@@ -316,11 +316,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
- MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
- MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
- MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+ MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
+ MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
+ MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
- MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+ MDP4_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
@@ -328,12 +328,12 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
- MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
- MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
- MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
- MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+ MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 4a3db2ea1689..0f653e62b4a0 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -216,7 +216,7 @@ static void blend_setup(struct drm_crtc *crtc)
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct drm_plane *plane;
struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
- const struct mdp_format *format;
+ const struct msm_format *format;
struct mdp5_hw_mixer *mixer = pipeline->mixer;
uint32_t lm = mixer->lm;
struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
@@ -274,7 +274,7 @@ static void blend_setup(struct drm_crtc *crtc)
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
DBG("Border Color is enabled");
} else if (plane_cnt) {
- format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
+ format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
if (format->alpha_enable)
bg_alpha_enabled = true;
@@ -285,8 +285,7 @@ static void blend_setup(struct drm_crtc *crtc)
if (!pstates[i])
continue;
- format = to_mdp_format(
- msm_framebuffer_format(pstates[i]->base.fb));
+ format = msm_framebuffer_format(pstates[i]->base.fb);
plane = pstates[i]->base.plane;
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index e40f6d1d5433..3b7c3eac8eda 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -228,12 +228,12 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
if (plane_enabled(state)) {
unsigned int rotation;
- const struct mdp_format *format;
+ const struct msm_format *format;
struct mdp5_kms *mdp5_kms = get_kms(plane);
uint32_t blkcfg = 0;
- format = to_mdp_format(msm_framebuffer_format(state->fb));
- if (MDP_FORMAT_IS_YUV(format))
+ format = msm_framebuffer_format(state->fb);
+ if (MSM_FORMAT_IS_YUV(format))
caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
if (((state->src_w >> 16) != state->crtc_w) ||
@@ -268,8 +268,8 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
new_hwpipe = true;
if (mdp5_kms->smp) {
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(state->fb);
blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
state->src_w >> 16, false);
@@ -630,11 +630,11 @@ static int calc_scaley_steps(struct drm_plane *plane,
return 0;
}
-static uint32_t get_scale_config(const struct mdp_format *format,
+static uint32_t get_scale_config(const struct msm_format *format,
uint32_t src, uint32_t dst, bool horz)
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
- bool yuv = MDP_FORMAT_IS_YUV(format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
+ bool yuv = MSM_FORMAT_IS_YUV(format);
bool scaling = yuv ? true : (src != dst);
uint32_t sub;
uint32_t ya_filter, uv_filter;
@@ -661,12 +661,12 @@ static uint32_t get_scale_config(const struct mdp_format *format,
COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
}
-static void calc_pixel_ext(const struct mdp_format *format,
+static void calc_pixel_ext(const struct msm_format *format,
uint32_t src, uint32_t dst, uint32_t phase_step[2],
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
bool horz)
{
- bool scaling = MDP_FORMAT_IS_YUV(format) ? true : (src != dst);
+ bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst);
int i;
/*
@@ -684,11 +684,11 @@ static void calc_pixel_ext(const struct mdp_format *format,
}
static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
- const struct mdp_format *format,
+ const struct msm_format *format,
uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
uint32_t lr, tb, req;
int i;
@@ -696,7 +696,7 @@ static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
uint32_t roi_w = src_w;
uint32_t roi_h = src_h;
- if (MDP_FORMAT_IS_YUV(format) && i == COMP_1_2) {
+ if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) {
roi_w /= info->hsub;
roi_h /= info->vsub;
}
@@ -770,8 +770,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
{
enum mdp5_pipe pipe = hwpipe->pipe;
bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(fb);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
@@ -795,21 +795,21 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
- MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
- MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
- MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+ MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
+ MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
+ MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
- MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+ MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
- MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
- MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
- MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
- MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+ MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
(hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
@@ -842,7 +842,7 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
}
if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
- if (MDP_FORMAT_IS_YUV(format))
+ if (MSM_FORMAT_IS_YUV(format))
csc_enable(mdp5_kms, pipe,
mdp_get_default_csc_cfg(CSC_YUV2RGB));
else
@@ -861,7 +861,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
struct mdp5_kms *mdp5_kms = get_kms(plane);
enum mdp5_pipe pipe = hwpipe->pipe;
struct mdp5_hw_pipe *right_hwpipe;
- const struct mdp_format *format;
+ const struct msm_format *format;
uint32_t nplanes, config = 0;
struct phase_step step = { { 0 } };
struct pixel_ext pe = { { 0 } };
@@ -882,8 +882,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
if (WARN_ON(nplanes > pipe2nclients(pipe)))
return -EINVAL;
- format = to_mdp_format(msm_framebuffer_format(fb));
- pix_format = format->base.pixel_format;
+ format = msm_framebuffer_format(fb);
+ pix_format = format->pixel_format;
src_x = src->x1;
src_y = src->y1;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
index b4bebb425d22..3a7f7edda96b 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
@@ -114,10 +114,10 @@ static void set_fifo_thresholds(struct mdp5_smp *smp,
* presumably happens during the dma from scanout buffer).
*/
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
- const struct mdp_format *format,
+ const struct msm_format *format,
u32 width, bool hdecim)
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
struct mdp5_kms *mdp5_kms = get_kms(smp);
int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
int i, hsub, nplanes, nlines;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
index 21732ed485be..1be9832382d7 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
@@ -74,7 +74,7 @@ void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p,
struct mdp5_global_state *global_state);
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
- const struct mdp_format *format,
+ const struct msm_format *format,
u32 width, bool hdecim);
int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 30919641c813..5fc55f41e74f 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -63,26 +63,24 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
};
#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
- .base = { \
- .pixel_format = DRM_FORMAT_ ## name, \
- .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
- }, \
+ .pixel_format = DRM_FORMAT_ ## name, \
.bpc_a = BPC ## a ## A, \
- .bpc_r = BPC ## r, \
- .bpc_g = BPC ## g, \
- .bpc_b = BPC ## b, \
- .unpack = { e0, e1, e2, e3 }, \
+ .bpc_r_cr = BPC ## r, \
+ .bpc_g_y = BPC ## g, \
+ .bpc_b_cb = BPC ## b, \
+ .element = { e0, e1, e2, e3 }, \
+ .fetch_type = fp, \
+ .chroma_sample = cs, \
.alpha_enable = alpha, \
.unpack_tight = tight, \
- .cpp = c, \
.unpack_count = cnt, \
- .fetch_type = fp, \
- .chroma_sample = cs, \
+ .bpp = c, \
+ .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
}
#define BPC0A 0
-static const struct mdp_format formats[] = {
+static const struct msm_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
@@ -141,9 +139,9 @@ const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
{
int i;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct mdp_format *f = &formats[i];
- if (f->base.pixel_format == format)
- return &f->base;
+ const struct msm_format *f = &formats[i];
+ if (f->pixel_format == format)
+ return f;
}
return NULL;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
index b1f199d4a079..6443d53954ee 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.h
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -20,10 +20,38 @@ enum msm_format_flags {
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+/**
+ * struct msm_format: defines the format configuration
+ * @pixel_format: format fourcc
+ * @element: element color ordering
+ * @fetch_type: how the color components are packed in pixel format
+ * @chroma_sample: chroma sub-samplng type
+ * @alpha_enable: whether the format has an alpha channel
+ * @unpack_tight: whether to use tight or loose unpack
+ * @unpack_align_msb: unpack aligned to LSB or MSB
+ * @unpack_count: number of the components to unpack
+ * @bpp: bytes per pixel
+ * @flags: usage bit flags
+ * @num_planes: number of planes (including meta data planes)
+ * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
+ * @tile_height: format tile height
+ */
struct msm_format {
uint32_t pixel_format;
+ enum mdp_bpc bpc_g_y, bpc_b_cb, bpc_r_cr;
+ enum mdp_bpc_alpha bpc_a;
+ u8 element[4];
+ enum mdp_fetch_type fetch_type;
+ enum mdp_chroma_samp_type chroma_sample;
+ bool alpha_enable;
+ u8 unpack_tight;
+ u8 unpack_align_msb;
+ u8 unpack_count;
+ u8 bpp;
unsigned long flags;
+ u8 num_planes;
enum mdp_fetch_mode fetch_mode;
+ u16 tile_height;
};
#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index b6e68a343336..a2d5af5c65e5 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -78,19 +78,6 @@ void mdp_irq_update(struct mdp_kms *mdp_kms);
* pixel format helpers:
*/
-struct mdp_format {
- struct msm_format base;
- enum mdp_bpc bpc_r, bpc_g, bpc_b;
- enum mdp_bpc_alpha bpc_a;
- uint8_t unpack[4];
- bool alpha_enable, unpack_tight;
- uint8_t cpp, unpack_count;
- enum mdp_fetch_type fetch_type;
- enum mdp_chroma_samp_type chroma_sample;
-};
-#define to_mdp_format(x) container_of(x, struct mdp_format, base)
-#define MDP_FORMAT_IS_YUV(mdp_format) (MSM_FORMAT_IS_YUV(&(mdp_format)->base))
-
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
/* MDP capabilities */
--
2.39.2
On 4/19/2024 9:01 PM, Dmitry Baryshkov wrote:
> In preparation to merger of formats databases, pull format flag
> definitions to mdp_format.h header, so that they are visibile to both
> dpu and mdp drivers.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++++++++++++++---------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 31 +++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +--
> drivers/gpu/drm/msm/disp/mdp_format.c | 6 +-
> drivers/gpu/drm/msm/disp/mdp_format.h | 39 ++++++++++++
> drivers/gpu/drm/msm/disp/mdp_kms.h | 4 +-
> drivers/gpu/drm/msm/msm_drv.h | 4 --
> 9 files changed, 109 insertions(+), 89 deletions(-)
>
Reviewed-by: Abhinav Kumar <[email protected]>
On 4/19/2024 9:01 PM, Dmitry Baryshkov wrote:
> Finally remove duplication between DPU and generic MDP code by merging
> DPU format lists to the MDP format database.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 602 --------------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 10 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
> drivers/gpu/drm/msm/disp/mdp_format.c | 614 ++++++++++++++++++---
> drivers/gpu/drm/msm/disp/mdp_format.h | 10 +
> drivers/gpu/drm/msm/disp/mdp_kms.h | 2 -
> drivers/gpu/drm/msm/msm_drv.h | 2 +
> 11 files changed, 571 insertions(+), 708 deletions(-)
>
Reviewed-by: Abhinav Kumar <[email protected]>