Hi all,
V4 of this series adding octal SPI-NOR support to Mobileye EyeQ5
platform. It has been tested on EyeQ5 hardware successfully. Patches
have been taken over time, meaning series got smaller over time.
Patches:
- Make cdns,fifo-depth optional by computing it from hardware.
- No-IRQ mode for indirect read operations. Behind a quirk flag.
- Busywait on commands and indirect reads; reduces hrtimeouts load.
- Add mobileye,eyeq5-ospi compatible.
- EyeQ5 devicetree:
- Add octal SPI-NOR node.
- Add SPI-NOR flash node on eval board.
There is no dependency except if you want zero errors in devicetree:
system-controller series [3] for <&clocks> phandle.
Have a nice day,
Théo
[0]: https://lore.kernel.org/lkml/[email protected]/
[1]: https://lore.kernel.org/linux-mips/[email protected]/
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/log/
[3]: https://lore.kernel.org/lkml/[email protected]/
[4]: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/
[5]: https://lore.kernel.org/lkml/[email protected]/
[6]: https://lore.kernel.org/lkml/[email protected]/
Signed-off-by: Théo Lebrun <[email protected]>
---
Changes in v4:
- Fix -Wunused-variable warning on patch "allow FIFO depth detection"
by dropping two unused local variables.
- Rebase onto spi/for-next, drop three applied patches:
- spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically
- spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible
- spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional
- Link to v3: https://lore.kernel.org/r/[email protected]
Changes in v3:
- dt-bindings:
- Patch "sort compatibles alphabetically":
- Moved first.
- Take Reviewed-By Krzysztof.
- Patch "add mobileye,eyeq5-ospi compatible":
- EyeQ5 no longer implies no cdns,fifo-depth prop. Patch now only adds
compatible, no more property conditional.
- New "make cdns,fifo-depth optional" patch, for all compatibles.
- Driver:
- FIFO depth detection is no longer a quirk. It is for all compatibles
if no DT property is provided.
- Rebase onto spi-next [4] to drop three patches. No-IRQ mode patch is
mentioned in email saying a subset of patches got applied [6].
However, it is not in spi-next, so it is kept in series.
- Busywait is no longer behind a quirk; it applies to all compatibles.
- No-IRQ mode patch got modified to change its quirk index because
previous quirk got removed.
- As we removed some quirks, we no longer overflow u8 quirks.
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Rebase upon v6.9-rc2.
- Fix dt-bindings commit subject tags.
- Take Reviewed-by: Krzysztof Kozlowski on dt-bindings commit.
- Add dt-bindings commit to order compatibles alphabetically.
Krzysztof: unsure if you want this. It is second so that commit
adding EyeQ5 compatible can be taken alone easily.
- Drop patch taken upstream:
spi: cadence-qspi: switch from legacy names to modern ones
- Add To: Rob Herring, following get_maintainer.pl recommendation.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Théo Lebrun (6):
spi: cadence-qspi: allow FIFO depth detection
spi: cadence-qspi: add no-IRQ mode to indirect reads
spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
MIPS: mobileye: eyeq5: Add SPI-NOR controller node
MIPS: mobileye: eyeq5: add octal flash node to eval board DTS
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++
drivers/spi/spi-cadence-quadspi.c | 91 +++++++++++++++++++++++-------
3 files changed, 102 insertions(+), 19 deletions(-)
---
base-commit: 9deae5003d0e89ec6ef15879a70ba6fb43e15029
change-id: 20240209-cdns-qspi-mbly-de2205a44ab3
Best regards,
--
Théo Lebrun <[email protected]>
Call readl_relaxed_poll_timeout() with no sleep at the start of
cqspi_wait_for_bit(). If its short timeout expires, a sleeping
readl_relaxed_poll_timeout() call takes the relay.
The reason is to avoid hrtimer interrupts on the system. All read
operations are expected to take less than 100µs.
Signed-off-by: Théo Lebrun <[email protected]>
---
drivers/spi/spi-cadence-quadspi.c | 31 +++++++++++++++++++++++--------
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index a82e23526a6f..87c88ee708e4 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -120,6 +120,7 @@ struct cqspi_driver_platdata {
/* Operation timeout value */
#define CQSPI_TIMEOUT_MS 500
#define CQSPI_READ_TIMEOUT_MS 10
+#define CQSPI_BUSYWAIT_TIMEOUT_US 500
/* Runtime_pm autosuspend delay */
#define CQSPI_AUTOSUSPEND_TIMEOUT 2000
@@ -298,13 +299,27 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_VERSAL_DMA_VAL 0x602
-static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
+static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata,
+ void __iomem *reg, const u32 mask, bool clr,
+ bool busywait)
{
+ u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC;
u32 val;
+ if (busywait) {
+ int ret = readl_relaxed_poll_timeout(reg, val,
+ (((clr ? ~val : val) & mask) == mask),
+ 0, CQSPI_BUSYWAIT_TIMEOUT_US);
+
+ if (ret != -ETIMEDOUT)
+ return ret;
+
+ timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US;
+ }
+
return readl_relaxed_poll_timeout(reg, val,
(((clr ? ~val : val) & mask) == mask),
- 10, CQSPI_TIMEOUT_MS * 1000);
+ 10, timeout_us);
}
static bool cqspi_is_idle(struct cqspi_st *cqspi)
@@ -434,8 +449,8 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
/* Polling for completion. */
- ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
- CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
+ ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,
+ CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true);
if (ret) {
dev_err(&cqspi->pdev->dev,
"Flash command execution timed out.\n");
@@ -790,8 +805,8 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
}
/* Check indirect done status */
- ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
+ ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,
+ CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true);
if (ret) {
dev_err(dev, "Indirect read completion error (%i)\n", ret);
goto failrd;
@@ -1091,8 +1106,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
}
/* Check indirect done status */
- ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
- CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
+ ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,
+ CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false);
if (ret) {
dev_err(dev, "Indirect write completion error (%i)\n", ret);
goto failwr;
--
2.44.0
Add SPI-NOR octal flash node to evaluation board devicetree.
Signed-off-by: Théo Lebrun <[email protected]>
---
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
index 6898b2d8267d..0e5fee7b680c 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
+++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
@@ -21,3 +21,18 @@ memory@0 {
<0x8 0x02000000 0x0 0x7E000000>;
};
};
+
+&ospi {
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* chip select */
+
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <8>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <400>;
+ cdns,tsd2d-ns = <400>;
+ cdns,tchsh-ns = <125>;
+ cdns,tslch-ns = <50>;
+ };
+};
--
2.44.0
Add Cadence Quad SPI controller node to EyeQ5 SoC devicetree.
Octal is supported.
Signed-off-by: Théo Lebrun <[email protected]>
---
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 8d4f65ec912d..1543c2b9bcb6 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -158,6 +158,21 @@ timer {
clocks = <&core0_clk>;
};
};
+
+ ospi: spi@2100000 {
+ compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
+ reg = <0 0x2100000 0x0 0x1000>,
+ <0 0x10000000 0x0 0x8000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks EQ5C_DIV_OSPI>;
+ assigned-clocks = <&clocks EQ5C_DIV_OSPI>;
+ assigned-clock-rates = <167000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ };
};
};
--
2.44.0
Declare a new mobileye,eyeq5-ospi compatible.
Signed-off-by: Théo Lebrun <[email protected]>
---
drivers/spi/spi-cadence-quadspi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 87c88ee708e4..05ebb03d319f 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2055,6 +2055,12 @@ static const struct cqspi_driver_platdata pensando_cdns_qspi = {
.quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
};
+static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
+ .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION |
+ CQSPI_RD_NO_IRQ,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -2088,6 +2094,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "amd,pensando-elba-qspi",
.data = &pensando_cdns_qspi,
},
+ {
+ .compatible = "mobileye,eyeq5-ospi",
+ .data = &mobileye_eyeq5_ospi,
+ },
{ /* end of table */ }
};
--
2.44.0
On Tue, 23 Apr 2024 12:01:39 +0200, Théo Lebrun wrote:
> V4 of this series adding octal SPI-NOR support to Mobileye EyeQ5
> platform. It has been tested on EyeQ5 hardware successfully. Patches
> have been taken over time, meaning series got smaller over time.
>
> Patches:
> - Make cdns,fifo-depth optional by computing it from hardware.
> - No-IRQ mode for indirect read operations. Behind a quirk flag.
> - Busywait on commands and indirect reads; reduces hrtimeouts load.
> - Add mobileye,eyeq5-ospi compatible.
> - EyeQ5 devicetree:
> - Add octal SPI-NOR node.
> - Add SPI-NOR flash node on eval board.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/6] spi: cadence-qspi: allow FIFO depth detection
commit: 3bf64a2b66edffd28614b004648ccd60e3139c9e
[2/6] spi: cadence-qspi: add no-IRQ mode to indirect reads
commit: 1f257b92e6330d576cc826fb8f0b74fe0e8209de
[3/6] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
commit: c1887396373b8faecef61d352bd521ac66162706
[4/6] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
commit: 47766799f546249813e97a0ccde8978ba114e89f
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark