Add the driver of PDM controller for the StarFive JH8100 SoC.
The Pulse Density Modulation (PDM) controller is a digital PDM
microphone interface controller and decoder that supports up to
4 channels. The PDM have two blocks and each block controls
stereo audio data which is transferred to a Inter-IC Sound (I2S)
recorder on the JH8100 SoC.
Signed-off-by: Xingyu Wu <[email protected]>
---
MAINTAINERS | 7 +
sound/soc/starfive/Kconfig | 7 +
sound/soc/starfive/Makefile | 1 +
sound/soc/starfive/jh8100_pdm.c | 447 ++++++++++++++++++++++++++++++++
4 files changed, 462 insertions(+)
create mode 100644 sound/soc/starfive/jh8100_pdm.c
diff --git a/MAINTAINERS b/MAINTAINERS
index c23fda1aa1f0..cf6e26ce16e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21079,6 +21079,13 @@ F: Documentation/devicetree/bindings/power/starfive*
F: drivers/pmdomain/starfive/
F: include/dt-bindings/power/starfive,jh7110-pmu.h
+STARFIVE JH8100 PDM DRIVER
+M: Xingyu Wu <[email protected]>
+M: Walker Chen <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/sound/starfive,jh8100-pdm.yaml
+F: sound/soc/starfive/jh8100_pdm.c
+
STARFIVE SOC DRIVERS
M: Conor Dooley <[email protected]>
S: Maintained
diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig
index 279ac5c1d309..f6b03ab0dd98 100644
--- a/sound/soc/starfive/Kconfig
+++ b/sound/soc/starfive/Kconfig
@@ -22,3 +22,10 @@ config SND_SOC_JH7110_TDM
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for StarFive TDM driver.
+
+config SND_SOC_JH8100_PDM
+ tristate "JH8100 PDM controller device driver"
+ depends on HAVE_CLK && SND_SOC_STARFIVE
+ select REGMAP_MMIO
+ help
+ Say Y or M if you want to add support for StarFive PDM driver.
diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile
index 9e958f70ef51..b672425830d9 100644
--- a/sound/soc/starfive/Makefile
+++ b/sound/soc/starfive/Makefile
@@ -1,3 +1,4 @@
# StarFive Platform Support
obj-$(CONFIG_SND_SOC_JH7110_PWMDAC) += jh7110_pwmdac.o
obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o
+obj-$(CONFIG_SND_SOC_JH8100_PDM) += jh8100_pdm.o
diff --git a/sound/soc/starfive/jh8100_pdm.c b/sound/soc/starfive/jh8100_pdm.c
new file mode 100644
index 000000000000..74b5f22622cc
--- /dev/null
+++ b/sound/soc/starfive/jh8100_pdm.c
@@ -0,0 +1,447 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PDM driver for the StarFive JH8100 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/tlv.h>
+
+/* PDM RES: BLOCK 0 */
+#define JH8100_PDM_DMIC_CTRL0 0x00
+#define JH8100_PDM_DC_SCALE0 0x04
+/* BLOCK 1 */
+#define JH8100_PDM_DMIC_CTRL1 0x10
+#define JH8100_PDM_DC_SCALE1 0x14
+
+#define JH8100_PDM_BLOCKX_SHIFT 0x10
+#define JH8100_PDM_GET_CTRLX(x) (JH8100_PDM_DMIC_CTRL0 + \
+ (x) * JH8100_PDM_BLOCKX_SHIFT)
+#define JH8100_PDM_GET_SCALEX(x) (JH8100_PDM_DC_SCALE0 + \
+ (x) * JH8100_PDM_BLOCKX_SHIFT)
+
+/* PDM CTRL0/1 OFFSET */
+#define JH8100_PDM_DMIC_MSB_MASK GENMASK(3, 1)
+#define JH8100_PDM_DMIC_VOL_MASK GENMASK(21, 16)
+#define JH8100_PDM_VOL_DB_MUTE GENMASK(21, 16)
+#define JH8100_PDM_VOL_DB_MAX 0
+
+#define JH8100_PDM_DMIC_RSWITCH_MASK BIT(22)
+#define JH8100_PDM_DMIC_LSWITCH_MASK BIT(23)
+#define JH8100_PDM_DMIC_I2S_SLAVE BIT(24)
+#define JH8100_PDM_DMIC_HPF_EN BIT(28)
+#define JH8100_PDM_DMIC_FASTMODE_MASK BIT(29)
+#define JH8100_PDM_SW_RST_MASK BIT(31)
+#define JH8100_PDM_SW_RST_RELEASE BIT(31)
+
+/* PDM SCALE0/1 OFFSET */
+#define JH8100_DMIC_DCOFF_MASK GENMASK(27, 8)
+#define JH8100_DMIC_DCOFF_DEF_VAL 0xc0005
+#define JH8100_DMIC_SCALE_MASK GENMASK(5, 0)
+#define JH8100_DMIC_SCALE_DEF_VAL 0x8
+
+enum jh8100_pdm_blockx {
+ JH8100_PDM_BLK0 = 0,
+ JH8100_PDM_BLK1 = 1,
+};
+
+struct jh8100_pdm_priv {
+ struct regmap *regmap;
+ struct regmap *syscon_regmap;
+ struct device *dev;
+ struct clk *dmic_clk;
+ struct clk *icg_clk;
+ struct reset_control *rst;
+ unsigned int syscon_args[2]; /* [0]: offset, [1]: mask */
+};
+
+static const DECLARE_TLV_DB_SCALE(volume_tlv, -9450, 150, 0);
+
+static const struct snd_kcontrol_new jh8100_pdm_snd_controls[] = {
+ SOC_DOUBLE_R("DC compensation Switch", JH8100_PDM_DMIC_CTRL0,
+ JH8100_PDM_DMIC_CTRL1, 30, 1, 0),
+ SOC_DOUBLE_R("High Pass Filter Switch", JH8100_PDM_DMIC_CTRL0,
+ JH8100_PDM_DMIC_CTRL1, 28, 1, 0),
+ SOC_DOUBLE_R_TLV("Volume", JH8100_PDM_DMIC_CTRL0,
+ JH8100_PDM_DMIC_CTRL1, 16, 0x3F, 1, volume_tlv),
+ SOC_DOUBLE_R("Data MSB Shift Route", JH8100_PDM_DMIC_CTRL0,
+ JH8100_PDM_DMIC_CTRL1, 1, 7, 0),
+ SOC_DOUBLE_R("SCALE Route", JH8100_PDM_DC_SCALE0,
+ JH8100_PDM_DC_SCALE1, 0, 0x3F, 0),
+ SOC_DOUBLE_R("DC offset Route", JH8100_PDM_DC_SCALE0,
+ JH8100_PDM_DC_SCALE1, 8, 0xFFFFF, 0),
+};
+
+/* Left (and Right) Channel Swicth Enable */
+static void jh8100_pdm_enable_lr(struct regmap *map, u8 block,
+ bool right)
+{
+ u16 res = JH8100_PDM_GET_CTRLX(block);
+
+ regmap_update_bits(map, res, JH8100_PDM_DMIC_RSWITCH_MASK, 0);
+
+ if (right)
+ regmap_update_bits(map, res, JH8100_PDM_DMIC_LSWITCH_MASK, 0);
+}
+
+/* Left and Right Channel Swicth Disable */
+static void jh8100_pdm_disable(struct regmap *map, u8 block)
+{
+ u16 res = JH8100_PDM_GET_CTRLX(block);
+
+ regmap_update_bits(map, res,
+ JH8100_PDM_DMIC_RSWITCH_MASK | JH8100_PDM_DMIC_LSWITCH_MASK,
+ JH8100_PDM_DMIC_RSWITCH_MASK | JH8100_PDM_DMIC_LSWITCH_MASK);
+}
+
+static void jh8100_pdm_disable_all(struct regmap *map)
+{
+ jh8100_pdm_disable(map, JH8100_PDM_BLK0);
+ jh8100_pdm_disable(map, JH8100_PDM_BLK1);
+}
+
+static int jh8100_pdm_dai_probe(struct snd_soc_dai *dai)
+{
+ struct jh8100_pdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+
+ /* Change I2SDIN source to PDM */
+ regmap_update_bits(priv->syscon_regmap, priv->syscon_args[0],
+ priv->syscon_args[1], priv->syscon_args[1]);
+
+ return 0;
+}
+
+static int jh8100_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct jh8100_pdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ return 0;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ jh8100_pdm_disable_all(priv->regmap);
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int jh8100_pdm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct jh8100_pdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+
+ /*
+ * 1 channel: block 0 left channel on,
+ * 2 channels: block 0 left/right on,
+ * 3 channels: block 0 left/right on, block 1 left on,
+ * 4 channels: block 0 and 1 all on.
+ */
+ switch (params_channels(params)) {
+ case 1:
+ jh8100_pdm_enable_lr(priv->regmap, JH8100_PDM_BLK0, false);
+ break;
+ case 2:
+ jh8100_pdm_enable_lr(priv->regmap, JH8100_PDM_BLK0, true);
+ break;
+ case 3:
+ jh8100_pdm_enable_lr(priv->regmap, JH8100_PDM_BLK0, true);
+ jh8100_pdm_enable_lr(priv->regmap, JH8100_PDM_BLK1, false);
+ break;
+ case 4:
+ jh8100_pdm_enable_lr(priv->regmap, JH8100_PDM_BLK0, true);
+ jh8100_pdm_enable_lr(priv->regmap, JH8100_PDM_BLK1, true);
+ break;
+
+ default:
+ dev_err(priv->dev, "channels are not supported\n");
+ return -EINVAL;
+ }
+
+ /* set pdm_mclk, PDM MCLK = 128 * LRCLK */
+ return clk_set_rate(priv->dmic_clk, 128 * params_rate(params));
+}
+
+static const struct snd_soc_dai_ops jh8100_pdm_dai_ops = {
+ .probe = jh8100_pdm_dai_probe,
+ .trigger = jh8100_pdm_trigger,
+ .hw_params = jh8100_pdm_hw_params,
+};
+
+static void jh8100_pdm_block_init(struct jh8100_pdm_priv *priv, u8 block)
+{
+ u16 ctrl = JH8100_PDM_GET_CTRLX(block);
+ u16 scale = JH8100_PDM_GET_SCALEX(block);
+
+ /* Reset */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_SW_RST_MASK, 0);
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_SW_RST_MASK, JH8100_PDM_SW_RST_RELEASE);
+
+ /* Make sure the device is initially disabled */
+ jh8100_pdm_disable(priv->regmap, block);
+
+ /* MUTE */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_DMIC_VOL_MASK, JH8100_PDM_VOL_DB_MUTE);
+
+ /* UNMUTE */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_DMIC_VOL_MASK, JH8100_PDM_VOL_DB_MAX);
+
+ /* enable high pass filter */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_DMIC_HPF_EN, JH8100_PDM_DMIC_HPF_EN);
+
+ /* PDM work as slave mode */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_DMIC_I2S_SLAVE, JH8100_PDM_DMIC_I2S_SLAVE);
+
+ /* Enable fast mode */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_DMIC_FASTMODE_MASK,
+ JH8100_PDM_DMIC_FASTMODE_MASK);
+
+ /* Default dmic msb shift 0 */
+ regmap_update_bits(priv->regmap, ctrl,
+ JH8100_PDM_DMIC_MSB_MASK, 0);
+
+ /* Default scale: 0x8 */
+ regmap_update_bits(priv->regmap, scale,
+ JH8100_DMIC_SCALE_MASK, JH8100_DMIC_SCALE_DEF_VAL);
+
+ /* Default DC offset: 0xc005 */
+ regmap_update_bits(priv->regmap, scale,
+ JH8100_DMIC_DCOFF_MASK,
+ FIELD_PREP(JH8100_DMIC_DCOFF_MASK, JH8100_DMIC_DCOFF_DEF_VAL));
+}
+
+#define JH8100_PDM_RATES (SNDRV_PCM_RATE_8000 | \
+ SNDRV_PCM_RATE_11025 | \
+ SNDRV_PCM_RATE_16000)
+
+#define JH8100_PDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver jh8100_pdm_dai_drv = {
+ .name = "PDM",
+ .id = 0,
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 1,
+ .channels_max = 4,
+ .rates = JH8100_PDM_RATES,
+ .formats = JH8100_PDM_FORMATS,
+ },
+ .ops = &jh8100_pdm_dai_ops,
+ .symmetric_rate = 1,
+};
+
+static int jh8100_pdm_component_probe(struct snd_soc_component *component)
+{
+ struct jh8100_pdm_priv *priv = snd_soc_component_get_drvdata(component);
+
+ snd_soc_component_init_regmap(component, priv->regmap);
+
+ return 0;
+}
+
+static int jh8100_pdm_crg_enable(struct jh8100_pdm_priv *priv)
+{
+ int ret;
+
+ ret = clk_prepare_enable(priv->icg_clk);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to enable icg clock\n");
+
+ ret = reset_control_deassert(priv->rst);
+ if (ret) {
+ dev_err(priv->dev, "failed to deassert pdm_apb\n");
+ goto disable_icg;
+ }
+
+ return 0;
+
+disable_icg:
+ clk_disable_unprepare(priv->icg_clk);
+ return ret;
+}
+
+static int jh8100_pdm_crg_disable(struct jh8100_pdm_priv *priv)
+{
+ int ret = reset_control_assert(priv->rst);
+
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to assert pdm_apb\n");
+
+ clk_disable_unprepare(priv->icg_clk);
+ return 0;
+}
+
+static int __maybe_unused jh8100_pdm_runtime_suspend(struct device *dev)
+{
+ struct jh8100_pdm_priv *priv = dev_get_drvdata(dev);
+
+ return jh8100_pdm_crg_disable(priv);
+}
+
+static int __maybe_unused jh8100_pdm_runtime_resume(struct device *dev)
+{
+ struct jh8100_pdm_priv *priv = dev_get_drvdata(dev);
+
+ return jh8100_pdm_crg_enable(priv);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int jh8100_pdm_suspend(struct snd_soc_component *component)
+{
+ return pm_runtime_force_suspend(component->dev);
+}
+
+static int jh8100_pdm_resume(struct snd_soc_component *component)
+{
+ return pm_runtime_force_resume(component->dev);
+}
+#else
+#define jh8100_pdm_suspend NULL
+#define jh8100_pdm_resume NULL
+#endif
+
+static const struct snd_soc_component_driver jh8100_pdm_component_drv = {
+ .name = "jh8100-pdm",
+ .probe = jh8100_pdm_component_probe,
+ .suspend = jh8100_pdm_suspend,
+ .resume = jh8100_pdm_resume,
+ .controls = jh8100_pdm_snd_controls,
+ .num_controls = ARRAY_SIZE(jh8100_pdm_snd_controls),
+};
+
+static const struct regmap_config jh8100_pdm_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x20,
+};
+
+static int jh8100_pdm_crg_init(struct jh8100_pdm_priv *priv)
+{
+ priv->dmic_clk = devm_clk_get(priv->dev, "dmic");
+ if (IS_ERR(priv->dmic_clk))
+ return dev_err_probe(priv->dev, PTR_ERR(priv->dmic_clk),
+ "failed to get dmic clock.\n");
+
+ priv->icg_clk = devm_clk_get(priv->dev, "icg");
+ if (IS_ERR(priv->icg_clk))
+ return dev_err_probe(priv->dev, PTR_ERR(priv->icg_clk),
+ "failed to get icg clock.\n");
+
+ priv->rst = devm_reset_control_get_exclusive(priv->dev, NULL);
+ if (IS_ERR(priv->rst))
+ return dev_err_probe(priv->dev, PTR_ERR(priv->rst), "failed to get pdm reset\n");
+
+ return jh8100_pdm_crg_enable(priv);
+}
+
+static int jh8100_pdm_probe(struct platform_device *pdev)
+{
+ struct jh8100_pdm_priv *priv;
+ void __iomem *base;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ platform_set_drvdata(pdev, priv);
+
+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &jh8100_pdm_regmap_cfg);
+ if (IS_ERR(priv->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->regmap),
+ "failed to init regmap\n");
+
+ priv->dev = &pdev->dev;
+ ret = jh8100_pdm_crg_init(priv);
+ if (ret)
+ return ret;
+
+ priv->syscon_regmap = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,syscon",
+ 2, priv->syscon_args);
+ if (IS_ERR(priv->syscon_regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->syscon_regmap),
+ "get the syscon regmap failed\n");
+
+ ret = devm_snd_soc_register_component(&pdev->dev, &jh8100_pdm_component_drv,
+ &jh8100_pdm_dai_drv, 1);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "failed to register pdm dai\n");
+
+ jh8100_pdm_block_init(priv, JH8100_PDM_BLK0);
+ jh8100_pdm_block_init(priv, JH8100_PDM_BLK1);
+
+ pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+}
+
+static int jh8100_pdm_remove(struct platform_device *pdev)
+{
+ struct jh8100_pdm_priv *priv = platform_get_drvdata(pdev);
+
+ /* Change I2SDIN source to default (PAD) */
+ regmap_update_bits(priv->syscon_regmap, priv->syscon_args[0],
+ priv->syscon_args[1], 0);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id jh8100_pdm_of_match[] = {
+ {.compatible = "starfive,jh8100-pdm",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, jh8100_pdm_of_match);
+
+static const struct dev_pm_ops jh8100_pdm_pm_ops = {
+ SET_RUNTIME_PM_OPS(jh8100_pdm_runtime_suspend,
+ jh8100_pdm_runtime_resume, NULL)
+};
+
+static struct platform_driver jh8100_pdm_driver = {
+ .driver = {
+ .name = "jh8100-pdm",
+ .of_match_table = jh8100_pdm_of_match,
+ .pm = &jh8100_pdm_pm_ops,
+ },
+ .probe = jh8100_pdm_probe,
+ .remove = jh8100_pdm_remove,
+};
+module_platform_driver(jh8100_pdm_driver);
+
+MODULE_AUTHOR("Xingyu Wu <[email protected]>");
+MODULE_AUTHOR("Walker Chen <[email protected]>");
+MODULE_DESCRIPTION("StarFive JH8100 PDM Controller Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
> Subject: [PATCH v2 2/2] ASoC: starfive: Add PDM controller support
>
> Add the driver of PDM controller for the StarFive JH8100 SoC.
>
> The Pulse Density Modulation (PDM) controller is a digital PDM microphone
> interface controller and decoder that supports up to
> 4 channels. The PDM have two blocks and each block controls stereo audio data
> which is transferred to a Inter-IC Sound (I2S) recorder on the JH8100 SoC.
>
> Signed-off-by: Xingyu Wu <[email protected]>
> ---
> MAINTAINERS | 7 +
> sound/soc/starfive/Kconfig | 7 +
> sound/soc/starfive/Makefile | 1 +
> sound/soc/starfive/jh8100_pdm.c | 447
> ++++++++++++++++++++++++++++++++
> 4 files changed, 462 insertions(+)
> create mode 100644 sound/soc/starfive/jh8100_pdm.c
>
Hi Mark,
Could you please help to review and give your comment about this PDM driver?
Thanks,
Xingyu Wu
On Wed, May 22, 2024 at 02:11:55AM +0000, Xingyu Wu wrote:
> Could you please help to review and give your comment about this PDM driver?
Please don't send content free pings and please allow a reasonable time
for review. People get busy, go on holiday, attend conferences and so
on so unless there is some reason for urgency (like critical bug fixes)
please allow at least a couple of weeks for review. If there have been
review comments then people may be waiting for those to be addressed.
Sending content free pings adds to the mail volume (if they are seen at
all) which is often the problem and since they can't be reviewed
directly if something has gone wrong you'll have to resend the patches
anyway, so sending again is generally a better approach though there are
some other maintainers who like them - if in doubt look at how patches
for the subsystem are normally handled.
On 22/05/2024 19:23, Mark Brown wrote:
>
> On Wed, May 22, 2024 at 02:11:55AM +0000, Xingyu Wu wrote:
>
> > Could you please help to review and give your comment about this PDM driver?
>
> Please don't send content free pings and please allow a reasonable time for
> review. People get busy, go on holiday, attend conferences and so on so unless
> there is some reason for urgency (like critical bug fixes) please allow at least a
> couple of weeks for review. If there have been review comments then people
> may be waiting for those to be addressed.
>
> Sending content free pings adds to the mail volume (if they are seen at
> all) which is often the problem and since they can't be reviewed directly if
> something has gone wrong you'll have to resend the patches anyway, so sending
> again is generally a better approach though there are some other maintainers
> who like them - if in doubt look at how patches for the subsystem are normally
> handled.
Sorry, you can do it when you have free time. Don't mind.
Thanks,
Xingyu Wu