This series enables clock support on the Samsung Exynos pin controller
driver.
This is required on Socs like Google Tensor gs101, which implement
fine-grained clock control / gating, and as such a running bus clock is
required for register access to work.
Signed-off-by: André Draszik <[email protected]>
---
André Draszik (2):
dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock
pinctrl: samsung: support a bus clock
.../bindings/pinctrl/samsung,pinctrl.yaml | 17 ++++
drivers/pinctrl/samsung/pinctrl-exynos.c | 111 +++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 74 ++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.h | 2 +
4 files changed, 204 insertions(+)
---
base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8
change-id: 20240425-samsung-pinctrl-busclock-151c23d76860
Best regards,
--
André Draszik <[email protected]>
The pin controller on Google Tensor gs101 requires a bus clock for
register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
---
As we only have the one clock here, please let me know if the
clock-names should be removed. Having it does make
/sys/kernel/debug/clk/clk_summary look nicer / more meaningful though
:-)
---
.../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 118549c25976..49cc36b76fd0 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -73,6 +73,13 @@ properties:
minItems: 1
maxItems: 2
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pclk
+
wakeup-interrupt-controller:
$ref: samsung,pinctrl-wakeup-interrupt.yaml
@@ -120,6 +127,16 @@ required:
allOf:
- $ref: pinctrl.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-pinctrl
+ then:
+ required:
+ - clocks
+ - clock-names
+
- if:
properties:
compatible:
--
2.44.0.769.g3c40516874-goog
On some Samsung-based SoCs there are separate bus clocks / gates each
for each pinctrl instance. To be able to access each pinctrl instance's
registers, this bus clock needs to be running, otherwise register
access will hang. Google Tensor gs101 is one example for such an
implementation.
Update the driver to handle this optional bus clock:
* handle an optional bus clock from DT
* prepare it during driver probe
* enclose all relevant register accesses with a clock enable & disable
Signed-off-by: André Draszik <[email protected]>
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 111 ++++++++++++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 74 ++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.h | 2 +
3 files changed, 187 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 871c1eb46ddf..857d631132f9 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -13,6 +13,7 @@
// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
// external gpio and wakeup interrupt support.
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
@@ -61,6 +62,12 @@ static void exynos_irq_mask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for masking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -68,6 +75,8 @@ static void exynos_irq_mask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_ack(struct irq_data *irqd)
@@ -82,7 +91,15 @@ static void exynos_irq_ack(struct irq_data *irqd)
else
reg_pend = our_chip->eint_pend + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock to ack IRQ\n");
+ return;
+ }
+
writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_unmask(struct irq_data *irqd)
@@ -110,6 +127,12 @@ static void exynos_irq_unmask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for unmasking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -117,6 +140,8 @@ static void exynos_irq_unmask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -127,6 +152,7 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
unsigned int con, trig_type;
unsigned long reg_con;
+ int ret;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -159,11 +185,20 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
else
reg_con = our_chip->eint_con + bank->eint_offset;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring IRQ type\n");
+ return ret;
+ }
+
con = readl(bank->eint_base + reg_con);
con &= ~(EXYNOS_EINT_CON_MASK << shift);
con |= trig_type << shift;
writel(con, bank->eint_base + reg_con);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -200,6 +235,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -209,6 +252,8 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for deconfiguring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -232,6 +284,8 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
}
@@ -281,10 +335,19 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
unsigned int svc, group, pin;
int ret;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for handling IRQ\n");
+ return IRQ_NONE;
+ }
+
if (bank->eint_con_offset)
svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
else
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
+
+ clk_disable(bank->drvdata->pclk);
+
group = EXYNOS_SVC_GROUP(svc);
pin = svc & EXYNOS_SVC_NUM_MASK;
@@ -563,6 +626,19 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
chained_irq_enter(chip, desc);
+ /* just enable the clock once here, to avoid an enable/disable dance for
+ * each bank.
+ */
+ if (eintd->nr_banks) {
+ struct samsung_pin_bank *b = eintd->banks[0];
+
+ if (clk_enable(b->drvdata->pclk)) {
+ dev_err(b->gpio_chip.parent,
+ "unable to enable clock for pending IRQs\n");
+ return;
+ }
+ }
+
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
pend = readl(b->eint_base + b->irq_chip->eint_pend
@@ -572,6 +648,9 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
+ if (eintd->nr_banks)
+ clk_disable(eintd->banks[0]->drvdata->pclk);
+
chained_irq_exit(chip, desc);
}
@@ -695,6 +774,12 @@ static void exynos_pinctrl_suspend_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
@@ -704,6 +789,8 @@ static void exynos_pinctrl_suspend_bank(
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
@@ -716,9 +803,17 @@ static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drv
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
}
@@ -753,6 +848,12 @@ static void exynos_pinctrl_resume_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset), save->eint_con);
@@ -774,6 +875,8 @@ static void exynos_pinctrl_resume_bank(
+ 2 * bank->eint_offset + 4);
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
@@ -782,6 +885,12 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
@@ -789,6 +898,8 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ed07e23e0912..8e4742d3655c 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -15,6 +15,7 @@
// but provides extensions to which platform specific implementation of the gpio
// and wakeup interrupts can be hooked to.
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
@@ -397,6 +398,11 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
reg += 4;
}
+ if (clk_enable(drvdata->pclk)) {
+ dev_err(pctldev->dev, "failed to enable clock for setup\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
@@ -405,6 +411,8 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
}
/* enable a specified pinmux by writing to registers */
@@ -436,6 +444,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
u32 data, width, pin_offset, mask, shift;
u32 cfg_value, cfg_reg;
unsigned long flags;
+ int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank);
@@ -447,6 +456,12 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
width = type->fld_width[cfg_type];
cfg_reg = type->reg_offset[cfg_type];
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = (1 << width) - 1;
@@ -466,6 +481,8 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(drvdata->pclk);
+
return 0;
}
@@ -539,16 +556,24 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
void __iomem *reg;
u32 data;
reg = bank->pctl_base + bank->pctl_offset;
+ if (clk_enable(drvdata->pclk)) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return;
+ }
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data &= ~(1 << offset);
if (value)
data |= 1 << offset;
writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);
+
+ clk_disable(drvdata->pclk);
}
/* gpiolib gpio_set callback function */
@@ -569,12 +594,23 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
u32 data;
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
+ int ret;
reg = bank->pctl_base + bank->pctl_offset;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data >>= offset;
data &= 1;
+
+ clk_disable(drvdata->pclk);
+
return data;
}
@@ -591,9 +627,12 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
struct samsung_pin_bank *bank;
void __iomem *reg;
u32 data, mask, shift;
+ struct samsung_pinctrl_drv_data *drvdata;
+ int ret;
bank = gpiochip_get_data(gc);
type = bank->type;
+ drvdata = bank->drvdata;
reg = bank->pctl_base + bank->pctl_offset
+ type->reg_offset[PINCFG_TYPE_FUNC];
@@ -606,12 +645,20 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
reg += 4;
}
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
data = readl(reg);
data &= ~(mask << shift);
if (!input)
data |= PIN_CON_FUNC_OUTPUT << shift;
writel(data, reg);
+ clk_disable(drvdata->pclk);
+
return 0;
}
@@ -1164,6 +1211,12 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
}
}
+ drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk");
+ if (IS_ERR(drvdata->pclk)) {
+ ret = PTR_ERR(drvdata->pclk);
+ goto err_put_banks;
+ }
+
ret = samsung_pinctrl_register(pdev, drvdata);
if (ret)
goto err_put_banks;
@@ -1202,6 +1255,13 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
int i;
+ i = clk_enable(drvdata->pclk);
+ if (i) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for saving state\n");
+ return i;
+ }
+
for (i = 0; i < drvdata->nr_banks; i++) {
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
@@ -1231,6 +1291,8 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
}
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->suspend)
drvdata->suspend(drvdata);
if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
@@ -1252,6 +1314,16 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
int i;
+ /* enable clock before the callback, as we don't want to have to deal
+ * with callback cleanup on clock failures.
+ */
+ i = clk_enable(drvdata->pclk);
+ if (i) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for restoring state\n");
+ return i;
+ }
+
if (drvdata->resume)
drvdata->resume(drvdata);
@@ -1286,6 +1358,8 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
writel(bank->pm_save[type], reg + offs[type]);
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable)
drvdata->retention_ctrl->disable(drvdata);
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index ab791afaabf5..d50ba6f07d5d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -274,6 +274,7 @@ struct samsung_pin_ctrl {
* through samsung_pinctrl_drv_data, not samsung_pin_bank).
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
+ * @pclk: optional bus clock if required for accessing registers
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
@@ -293,6 +294,7 @@ struct samsung_pinctrl_drv_data {
void __iomem *virt_base;
struct device *dev;
int irq;
+ struct clk *pclk;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
--
2.44.0.769.g3c40516874-goog
On 25/04/2024 20:15, Krzysztof Kozlowski wrote:
>> + properties:
>> + compatible:
>> + contains:
>> + const: google,gs101-pinctrl
>> + then:
>> + required:
>> + - clocks
>> + - clock-names
>
> else:
> properties:
> clocks: false
> clock-names: false
>
> but anyway this is all a bit fragile, because pinctrl is not a driver
> and you rely on initcall ordering.
It is a driver, although initcall ordering is still there. Anyway, it's
the first soc requiring clock for pinctrl
Best regards,
Krzysztof
On 25/04/2024 18:03, André Draszik wrote:
> The pin controller on Google Tensor gs101 requires a bus clock for
> register access to work. Add it.
>
> Signed-off-by: André Draszik <[email protected]>
>
> ---
> As we only have the one clock here, please let me know if the
> clock-names should be removed. Having it does make
> /sys/kernel/debug/clk/clk_summary look nicer / more meaningful though
> :-)
> ---
> .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> index 118549c25976..49cc36b76fd0 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
> @@ -73,6 +73,13 @@ properties:
> minItems: 1
> maxItems: 2
>
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: pclk
> +
> wakeup-interrupt-controller:
> $ref: samsung,pinctrl-wakeup-interrupt.yaml
>
> @@ -120,6 +127,16 @@ required:
>
> allOf:
> - $ref: pinctrl.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-pinctrl
> + then:
> + required:
> + - clocks
> + - clock-names
else:
properties:
clocks: false
clock-names: false
but anyway this is all a bit fragile, because pinctrl is not a driver
and you rely on initcall ordering.
>
Best regards,
Krzysztof
On 25/04/2024 18:03, André Draszik wrote:
> On some Samsung-based SoCs there are separate bus clocks / gates each
> for each pinctrl instance. To be able to access each pinctrl instance's
> registers, this bus clock needs to be running, otherwise register
> access will hang. Google Tensor gs101 is one example for such an
> implementation.
>
> Update the driver to handle this optional bus clock:
> * handle an optional bus clock from DT
> * prepare it during driver probe
> * enclose all relevant register accesses with a clock enable & disable
>
..
> drvdata = pinctrl_dev_get_drvdata(pctldev);
> pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank);
> @@ -447,6 +456,12 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
> width = type->fld_width[cfg_type];
> cfg_reg = type->reg_offset[cfg_type];
>
> + ret = clk_enable(drvdata->pclk);
> + if (ret) {
> + dev_err(drvdata->dev, "failed to enable clock\n");
> + return ret;
> + }
> +
> raw_spin_lock_irqsave(&bank->slock, flags);
>
> mask = (1 << width) - 1;
> @@ -466,6 +481,8 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
>
> raw_spin_unlock_irqrestore(&bank->slock, flags);
>
> + clk_disable(drvdata->pclk);
> +
> return 0;
> }
>
> @@ -539,16 +556,24 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
> {
> struct samsung_pin_bank *bank = gpiochip_get_data(gc);
> const struct samsung_pin_bank_type *type = bank->type;
> + struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
> void __iomem *reg;
> u32 data;
>
> reg = bank->pctl_base + bank->pctl_offset;
>
> + if (clk_enable(drvdata->pclk)) {
This is now called with bank->slock held, so you reversed the locking
thus creating possibility of ABBA deadlock.
Need to be moved to callers of samsung_gpio_set_value().
> + dev_err(drvdata->dev, "failed to enable clock\n");
> + return;
> + }
> +
> data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
> data &= ~(1 << offset);
> if (value)
> data |= 1 << offset;
> writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);
> +
> + clk_disable(drvdata->pclk);
> }
>
> /* gpiolib gpio_set callback function */
> @@ -569,12 +594,23 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
> u32 data;
> struct samsung_pin_bank *bank = gpiochip_get_data(gc);
> const struct samsung_pin_bank_type *type = bank->type;
> + struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
> + int ret;
>
> reg = bank->pctl_base + bank->pctl_offset;
>
> + ret = clk_enable(drvdata->pclk);
> + if (ret) {
> + dev_err(drvdata->dev, "failed to enable clock\n");
> + return ret;
> + }
> +
> data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
> data >>= offset;
> data &= 1;
> +
> + clk_disable(drvdata->pclk);
> +
> return data;
> }
>
> @@ -591,9 +627,12 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
> struct samsung_pin_bank *bank;
> void __iomem *reg;
> u32 data, mask, shift;
> + struct samsung_pinctrl_drv_data *drvdata;
> + int ret;
>
> bank = gpiochip_get_data(gc);
> type = bank->type;
> + drvdata = bank->drvdata;
>
> reg = bank->pctl_base + bank->pctl_offset
> + type->reg_offset[PINCFG_TYPE_FUNC];
> @@ -606,12 +645,20 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
> reg += 4;
> }
>
> + ret = clk_enable(drvdata->pclk);
Same problem.
> + if (ret) {
> + dev_err(drvdata->dev, "failed to enable clock\n");
> + return ret;
> + }
> +
> data = readl(reg);
> data &= ~(mask << shift);
> if (!input)
> data |= PIN_CON_FUNC_OUTPUT << shift;
> writel(data, reg);
>
> + clk_disable(drvdata->pclk);
> +
> return 0;
> }
>
> @@ -1164,6 +1211,12 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
> }
> }
>
> + drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk");
> + if (IS_ERR(drvdata->pclk)) {
> + ret = PTR_ERR(drvdata->pclk);
> + goto err_put_banks;
> + }
> +
> ret = samsung_pinctrl_register(pdev, drvdata);
> if (ret)
> goto err_put_banks;
> @@ -1202,6 +1255,13 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
> struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
> int i;
>
> + i = clk_enable(drvdata->pclk);
> + if (i) {
> + dev_err(drvdata->dev,
> + "failed to enable clock for saving state\n");
> + return i;
> + }
> +
> for (i = 0; i < drvdata->nr_banks; i++) {
> struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
> const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
> @@ -1231,6 +1291,8 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
> }
> }
>
> + clk_disable(drvdata->pclk);
> +
> if (drvdata->suspend)
> drvdata->suspend(drvdata);
> if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
> @@ -1252,6 +1314,16 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
> struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
> int i;
>
> + /* enable clock before the callback, as we don't want to have to deal
That's not netdev, so:
/*
*
> + * with callback cleanup on clock failures.
> + */
> + i = clk_enable(drvdata->pclk);
"i" is iterator, not return value. You want ret.
> + if (i) {
> + dev_err(drvdata->dev,
> + "failed to enable clock for restoring state\n");
> + return i;
> + }
> +
> if (drvdata->resume)
> drvdata->resume(drvdata);
>
> @@ -1286,6 +1358,8 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
> writel(bank->pm_save[type], reg + offs[type]);
> }
>
> + clk_disable(drvdata->pclk);
> +
> if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable)
> drvdata->retention_ctrl->disable(drvdata);
>
Best regards,
Krzysztof
On Thu, 2024-04-25 at 20:18 +0200, Krzysztof Kozlowski wrote:
> On 25/04/2024 20:15, Krzysztof Kozlowski wrote:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: google,gs101-pinctrl
> > > + then:
> > > + required:
> > > + - clocks
> > > + - clock-names
> >
> > else:
> > properties:
> > clocks: false
> > clock-names: false
> >
> > but anyway this is all a bit fragile, because pinctrl is not a driver
> > and you rely on initcall ordering.
>
> It is a driver, although initcall ordering is still there. Anyway, it's
> the first soc requiring clock for pinctrl
If I see it right, E850 has similar gates, and like on gs101 they're currently
also all marked as CLK_IGNORE_UNUSED in the e850 clock driver with a comment that
a driver update is needed. I've added Sam.
Cheers,
Andre'
On 26/04/2024 12:54, André Draszik wrote:
> On Thu, 2024-04-25 at 20:18 +0200, Krzysztof Kozlowski wrote:
>> On 25/04/2024 20:15, Krzysztof Kozlowski wrote:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: google,gs101-pinctrl
>>>> + then:
>>>> + required:
>>>> + - clocks
>>>> + - clock-names
>>>
>>> else:
>>> properties:
>>> clocks: false
>>> clock-names: false
>>>
>>> but anyway this is all a bit fragile, because pinctrl is not a driver
>>> and you rely on initcall ordering.
>>
>> It is a driver, although initcall ordering is still there. Anyway, it's
>> the first soc requiring clock for pinctrl
>
> If I see it right, E850 has similar gates, and like on gs101 they're currently
> also all marked as CLK_IGNORE_UNUSED in the e850 clock driver with a comment that
> a driver update is needed. I've added Sam.
Cool, so this should solve also Sam's problem. Sam, can you test the
patchset in spare time?
Best regards,
Krzysztof