Fixed 8mp EP mode problem.
imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
pci-imx.c to avoid confuse.
Using callback to reduce switch case for core reset and refclk.
Add imx95 iommux and its stream id information.
Base on linux-pci/controller/imx
To: Richard Zhu <[email protected]>
To: Lucas Stach <[email protected]>
To: Lorenzo Pieralisi <[email protected]>
To: Krzysztof Wilczyński <[email protected]>
To: Rob Herring <[email protected]>
To: Bjorn Helgaas <[email protected]>
To: Shawn Guo <[email protected]>
To: Sascha Hauer <[email protected]>
To: Pengutronix Kernel Team <[email protected]>
To: Fabio Estevam <[email protected]>
To: NXP Linux Team <[email protected]>
To: Philipp Zabel <[email protected]>
To: Liam Girdwood <[email protected]>
To: Mark Brown <[email protected]>
To: Manivannan Sadhasivam <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Conor Dooley <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Frank Li <[email protected]>
Changes in v3:
- Add an EP fixed patch
PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
- Add 8qxp rc support
dt-bing yaml pass binding check
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- remove file to 'pcie-imx.c'
- keep CONFIG unchange.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Frank Li (7):
PCI: imx6: Rename imx6_* with imx_*
PCI: imx6: Rename pci-imx6.c to pcie-imx.c
MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file
PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
PCI: imx: Simplify switch-case logic by involve core_reset callback
PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95
PCI: imx: Consolidate redundant if-checks
Richard Zhu (4):
PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
PCI: imx6: Add i.MX8Q PCIe support
.../bindings/pci/fsl,imx6q-pcie-common.yaml | 5 +
.../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 18 +
MAINTAINERS | 4 +-
drivers/pci/controller/dwc/Makefile | 2 +-
.../pci/controller/dwc/{pci-imx6.c => pcie-imx.c} | 1173 ++++++++++++--------
5 files changed, 727 insertions(+), 475 deletions(-)
---
base-commit: 2e45e73eebd43365cb585c49b3a671dcfae6b5b5
change-id: 20240227-pci2_upstream-0cdd19a15163
Best regards,
---
Frank Li <[email protected]>
Add me to imx pcie driver maintainer.
Add mail list [email protected].
Signed-off-by: Frank Li <[email protected]>
---
MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d1052fa6a692..59a409dd604d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16736,14 +16736,16 @@ F: drivers/pci/controller/pci-host-generic.c
PCI DRIVER FOR IMX6
M: Richard Zhu <[email protected]>
+M: Frank Li <[email protected]>
M: Lucas Stach <[email protected]>
L: [email protected]
+L: [email protected]
L: [email protected] (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
-F: drivers/pci/controller/dwc/*imx6*
+F: drivers/pci/controller/dwc/*imx*
PCI DRIVER FOR INTEL IXP4XX
M: Linus Walleij <[email protected]>
--
2.34.1
From: Richard Zhu <[email protected]>
Fix i.MX8MP PCIe EP can't trigger MSI issue.
There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound
region configuration.
EP uses Bar0 to set the outboud region to configure the MSI setting.
Set the page_size to "epc_features->align" to meet the requirement,
let the MSI can be triggered successfully.
Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code")
Signed-off-by: Richard Zhu <[email protected]>
Acked-by: Jason Liu <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index e43eda6b33ca7..6c4d25b92225e 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ ep->page_size = imx6_pcie->drvdata->epc_features->align;
+
ret = dw_pcie_ep_init(ep);
if (ret) {
dev_err(dev, "failed to initialize endpoint\n");
--
2.34.1
Instead of using the switch case statement to enable/disable the reference
clock handled by this driver itself, let's introduce a new callback
set_ref_clk() and define it for platforms that require it. This simplifies
the code.
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pcie-imx.c | 119 ++++++++++++++++------------------
1 file changed, 55 insertions(+), 64 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
index e93070d60df52..77dae5c3f7057 100644
--- a/drivers/pci/controller/dwc/pcie-imx.c
+++ b/drivers/pci/controller/dwc/pcie-imx.c
@@ -103,6 +103,7 @@ struct imx_pcie_drvdata {
const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx_pcie *pcie);
+ int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
};
struct imx_pcie {
@@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev)
return 0;
}
-static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
+static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
- unsigned int offset;
- int ret = 0;
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+ enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
- switch (imx_pcie->drvdata->variant) {
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
- break;
- case IMX6QP:
- case IMX6Q:
+ return 0;
+}
+
+static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+ if (enable) {
/* power up core phy and enable ref clock */
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0);
/*
- * the async reset input need ref clock to sync internally,
- * when the ref clock comes after reset, internal synced
- * reset time is too short, cannot meet the requirement.
- * add one ~10us delay here.
+ * the async reset input need ref clock to sync internally, when the ref clock comes
+ * after reset, internal synced reset time is too short, cannot meet the
+ * requirement.add one ~10us delay here.
*/
usleep_range(10, 100);
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
- break;
- case IMX7D:
- case IMX95:
- case IMX95_EP:
- break;
- case IMX8MM:
- case IMX8MM_EP:
- case IMX8MQ:
- case IMX8MQ_EP:
- case IMX8MP:
- case IMX8MP_EP:
- offset = imx_pcie_grp_offset(imx_pcie);
- /*
- * Set the over ride low and enabled
- * make sure that REF_CLK is turned on.
- */
- regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
- 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
- break;
+ IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN);
+ } else {
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD);
}
- return ret;
+ return 0;
}
-static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
+static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
- switch (imx_pcie->drvdata->variant) {
- case IMX6QP:
- case IMX6Q:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD,
- IMX6Q_GPR1_PCIE_TEST_PD);
- break;
- case IMX7D:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
- break;
- default:
- break;
- }
+ int offset = imx_pcie_grp_offset(imx_pcie);
+
+ /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
+ enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
+ return 0;
+}
+
+static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
+ enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
+ return 0;
}
static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
@@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
if (ret)
return ret;
- ret = imx_pcie_enable_ref_clk(imx_pcie);
- if (ret) {
- dev_err(dev, "unable to enable pcie ref clock\n");
- goto err_ref_clk;
+ if (imx_pcie->drvdata->set_ref_clk) {
+ ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true);
+ if (ret) {
+ dev_err(dev, "unable to enable pcie ref clock\n");
+ goto err_ref_clk;
+ }
}
/* allow the clocks to stabilize */
@@ -686,7 +666,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
{
- imx_pcie_disable_ref_clk(imx_pcie);
+ if (imx_pcie->drvdata->set_ref_clk)
+ imx_pcie->drvdata->set_ref_clk(imx_pcie, false);
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
@@ -1465,6 +1446,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
+ .set_ref_clk = imx6q_pcie_set_ref_clk,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1479,6 +1461,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx6sx_pcie_init_phy,
+ .set_ref_clk = imx6sx_pcie_set_ref_clk,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1494,6 +1477,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
+ .set_ref_clk = imx6q_pcie_set_ref_clk,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1506,6 +1490,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx7d_pcie_init_phy,
+ .set_ref_clk = imx7d_pcie_set_ref_clk,
},
[IMX8MQ] = {
.variant = IMX8MQ,
@@ -1519,6 +1504,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[1] = IOMUXC_GPR12,
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
.init_phy = imx8mq_pcie_init_phy,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MM] = {
.variant = IMX8MM,
@@ -1530,6 +1516,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MP] = {
.variant = IMX8MP,
@@ -1541,6 +1528,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX95] = {
.variant = IMX95,
@@ -1567,6 +1555,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
.init_phy = imx8mq_pcie_init_phy,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
@@ -1579,6 +1568,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
@@ -1591,6 +1581,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX95_EP] = {
.variant = IMX95_EP,
--
2.34.1
On Tue, Apr 02, 2024 at 10:33:36AM -0400, Frank Li wrote:
> Fixed 8mp EP mode problem.
>
> imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
> confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
> pci-imx.c to avoid confuse.
Mani and lorenzo:
Do you have chance to look these patches?
Frank
>
> Using callback to reduce switch case for core reset and refclk.
>
> Add imx95 iommux and its stream id information.
>
> Base on linux-pci/controller/imx
>
> To: Richard Zhu <[email protected]>
> To: Lucas Stach <[email protected]>
> To: Lorenzo Pieralisi <[email protected]>
> To: Krzysztof Wilczyński <[email protected]>
> To: Rob Herring <[email protected]>
> To: Bjorn Helgaas <[email protected]>
> To: Shawn Guo <[email protected]>
> To: Sascha Hauer <[email protected]>
> To: Pengutronix Kernel Team <[email protected]>
> To: Fabio Estevam <[email protected]>
> To: NXP Linux Team <[email protected]>
> To: Philipp Zabel <[email protected]>
> To: Liam Girdwood <[email protected]>
> To: Mark Brown <[email protected]>
> To: Manivannan Sadhasivam <[email protected]>
> To: Krzysztof Kozlowski <[email protected]>
> To: Conor Dooley <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Frank Li <[email protected]>
>
> Changes in v3:
> - Add an EP fixed patch
> PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> - Add 8qxp rc support
> dt-bing yaml pass binding check
> make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
> LINT Documentation/devicetree/bindings
> DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
>
> - Link to v2: https://lore.kernel.org/r/[email protected]
>
> Changes in v2:
> - remove file to 'pcie-imx.c'
> - keep CONFIG unchange.
> - Link to v1: https://lore.kernel.org/r/[email protected]
>
> ---
> Frank Li (7):
> PCI: imx6: Rename imx6_* with imx_*
> PCI: imx6: Rename pci-imx6.c to pcie-imx.c
> MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file
> PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
> PCI: imx: Simplify switch-case logic by involve core_reset callback
> PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95
> PCI: imx: Consolidate redundant if-checks
>
> Richard Zhu (4):
> PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
> PCI: imx6: Add i.MX8Q PCIe support
>
> .../bindings/pci/fsl,imx6q-pcie-common.yaml | 5 +
> .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 18 +
> MAINTAINERS | 4 +-
> drivers/pci/controller/dwc/Makefile | 2 +-
> .../pci/controller/dwc/{pci-imx6.c => pcie-imx.c} | 1173 ++++++++++++--------
> 5 files changed, 727 insertions(+), 475 deletions(-)
> ---
> base-commit: 2e45e73eebd43365cb585c49b3a671dcfae6b5b5
> change-id: 20240227-pci2_upstream-0cdd19a15163
>
> Best regards,
> ---
> Frank Li <[email protected]>
>
On Tue, Apr 02, 2024 at 10:33:36AM -0400, Frank Li wrote:
> Fixed 8mp EP mode problem.
>
> imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
> confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
> pci-imx.c to avoid confuse.
>
> Using callback to reduce switch case for core reset and refclk.
>
> Add imx95 iommux and its stream id information.
Mani and lorenzo:
Do you have chance to review these patches?
Frank
>
> Base on linux-pci/controller/imx
>
> To: Richard Zhu <[email protected]>
> To: Lucas Stach <[email protected]>
> To: Lorenzo Pieralisi <[email protected]>
> To: Krzysztof Wilczyński <[email protected]>
> To: Rob Herring <[email protected]>
> To: Bjorn Helgaas <[email protected]>
> To: Shawn Guo <[email protected]>
> To: Sascha Hauer <[email protected]>
> To: Pengutronix Kernel Team <[email protected]>
> To: Fabio Estevam <[email protected]>
> To: NXP Linux Team <[email protected]>
> To: Philipp Zabel <[email protected]>
> To: Liam Girdwood <[email protected]>
> To: Mark Brown <[email protected]>
> To: Manivannan Sadhasivam <[email protected]>
> To: Krzysztof Kozlowski <[email protected]>
> To: Conor Dooley <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Frank Li <[email protected]>
>
> Changes in v3:
> - Add an EP fixed patch
> PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> - Add 8qxp rc support
> dt-bing yaml pass binding check
> make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
> LINT Documentation/devicetree/bindings
> DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
>
> - Link to v2: https://lore.kernel.org/r/[email protected]
>
> Changes in v2:
> - remove file to 'pcie-imx.c'
> - keep CONFIG unchange.
> - Link to v1: https://lore.kernel.org/r/[email protected]
>
> ---
> Frank Li (7):
> PCI: imx6: Rename imx6_* with imx_*
> PCI: imx6: Rename pci-imx6.c to pcie-imx.c
> MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file
> PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
> PCI: imx: Simplify switch-case logic by involve core_reset callback
> PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95
> PCI: imx: Consolidate redundant if-checks
>
> Richard Zhu (4):
> PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
> PCI: imx6: Add i.MX8Q PCIe support
>
> .../bindings/pci/fsl,imx6q-pcie-common.yaml | 5 +
> .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 18 +
> MAINTAINERS | 4 +-
> drivers/pci/controller/dwc/Makefile | 2 +-
> .../pci/controller/dwc/{pci-imx6.c => pcie-imx.c} | 1173 ++++++++++++--------
> 5 files changed, 727 insertions(+), 475 deletions(-)
> ---
> base-commit: 2e45e73eebd43365cb585c49b3a671dcfae6b5b5
> change-id: 20240227-pci2_upstream-0cdd19a15163
>
> Best regards,
> ---
> Frank Li <[email protected]>
>
On Tue, Apr 16, 2024 at 10:07:25AM -0400, Frank Li wrote:
> On Tue, Apr 02, 2024 at 10:33:36AM -0400, Frank Li wrote:
> > Fixed 8mp EP mode problem.
> >
> > imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
> > confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
> > pci-imx.c to avoid confuse.
>
>
> Mani and lorenzo:
>
> Do you have chance to look these patches?
>
Sorry for the delay. Since this is a non-dwc driver, it got into my low priority
queue. Will take a look this week.
- Mani
> Frank
>
> >
> > Using callback to reduce switch case for core reset and refclk.
> >
> > Add imx95 iommux and its stream id information.
> >
> > Base on linux-pci/controller/imx
> >
> > To: Richard Zhu <[email protected]>
> > To: Lucas Stach <[email protected]>
> > To: Lorenzo Pieralisi <[email protected]>
> > To: Krzysztof Wilczyński <[email protected]>
> > To: Rob Herring <[email protected]>
> > To: Bjorn Helgaas <[email protected]>
> > To: Shawn Guo <[email protected]>
> > To: Sascha Hauer <[email protected]>
> > To: Pengutronix Kernel Team <[email protected]>
> > To: Fabio Estevam <[email protected]>
> > To: NXP Linux Team <[email protected]>
> > To: Philipp Zabel <[email protected]>
> > To: Liam Girdwood <[email protected]>
> > To: Mark Brown <[email protected]>
> > To: Manivannan Sadhasivam <[email protected]>
> > To: Krzysztof Kozlowski <[email protected]>
> > To: Conor Dooley <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Signed-off-by: Frank Li <[email protected]>
> >
> > Changes in v3:
> > - Add an EP fixed patch
> > PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> > PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> > - Add 8qxp rc support
> > dt-bing yaml pass binding check
> > make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
> > LINT Documentation/devicetree/bindings
> > DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
> > CHKDT Documentation/devicetree/bindings/processed-schema.json
> > SCHEMA Documentation/devicetree/bindings/processed-schema.json
> > DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
> >
> > - Link to v2: https://lore.kernel.org/r/[email protected]
> >
> > Changes in v2:
> > - remove file to 'pcie-imx.c'
> > - keep CONFIG unchange.
> > - Link to v1: https://lore.kernel.org/r/[email protected]
> >
> > ---
> > Frank Li (7):
> > PCI: imx6: Rename imx6_* with imx_*
> > PCI: imx6: Rename pci-imx6.c to pcie-imx.c
> > MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file
> > PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
> > PCI: imx: Simplify switch-case logic by involve core_reset callback
> > PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95
> > PCI: imx: Consolidate redundant if-checks
> >
> > Richard Zhu (4):
> > PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> > PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> > dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
> > PCI: imx6: Add i.MX8Q PCIe support
> >
> > .../bindings/pci/fsl,imx6q-pcie-common.yaml | 5 +
> > .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 18 +
> > MAINTAINERS | 4 +-
> > drivers/pci/controller/dwc/Makefile | 2 +-
> > .../pci/controller/dwc/{pci-imx6.c => pcie-imx.c} | 1173 ++++++++++++--------
> > 5 files changed, 727 insertions(+), 475 deletions(-)
> > ---
> > base-commit: 2e45e73eebd43365cb585c49b3a671dcfae6b5b5
> > change-id: 20240227-pci2_upstream-0cdd19a15163
> >
> > Best regards,
> > ---
> > Frank Li <[email protected]>
> >
--
மணிவண்ணன் சதாசிவம்
On Tue, Apr 02, 2024 at 10:33:38AM -0400, Frank Li wrote:
> From: Richard Zhu <[email protected]>
>
> Fix i.MX8MP PCIe EP can't trigger MSI issue.
> There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound
> region configuration.
>
> EP uses Bar0 to set the outboud region to configure the MSI setting.
I don't understand this statement. How EP can use BAR0 for MSI? MSIs are
triggered using outbound window memory while BARs are mapped as inbound.
- Mani
> Set the page_size to "epc_features->align" to meet the requirement,
> let the MSI can be triggered successfully.
>
> Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code")
> Signed-off-by: Richard Zhu <[email protected]>
> Acked-by: Jason Liu <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index e43eda6b33ca7..6c4d25b92225e 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
> if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
> dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
>
> + ep->page_size = imx6_pcie->drvdata->epc_features->align;
> +
> ret = dw_pcie_ep_init(ep);
> if (ret) {
> dev_err(dev, "failed to initialize endpoint\n");
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
On Tue, Apr 02, 2024 at 10:33:41AM -0400, Frank Li wrote:
> Add me to imx pcie driver maintainer.
> Add mail list [email protected].
>
> Signed-off-by: Frank Li <[email protected]>
The driver name changing part should be dropped. But adding a co-maintainer,
warrants an ACK from previous maintainers.
- Mani
> ---
> MAINTAINERS | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8d1052fa6a692..59a409dd604d8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16736,14 +16736,16 @@ F: drivers/pci/controller/pci-host-generic.c
>
> PCI DRIVER FOR IMX6
> M: Richard Zhu <[email protected]>
> +M: Frank Li <[email protected]>
> M: Lucas Stach <[email protected]>
> L: [email protected]
> +L: [email protected]
> L: [email protected] (moderated for non-subscribers)
> S: Maintained
> F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> -F: drivers/pci/controller/dwc/*imx6*
> +F: drivers/pci/controller/dwc/*imx*
>
> PCI DRIVER FOR INTEL IXP4XX
> M: Linus Walleij <[email protected]>
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
On Tue, Apr 02, 2024 at 10:33:42AM -0400, Frank Li wrote:
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
> Instead of using the switch case statement to enable/disable the reference
> clock handled by this driver itself, let's introduce a new callback
> set_ref_clk() and define it for platforms that require it. This simplifies
> the code.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-imx.c | 119 ++++++++++++++++------------------
> 1 file changed, 55 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> index e93070d60df52..77dae5c3f7057 100644
> --- a/drivers/pci/controller/dwc/pcie-imx.c
> +++ b/drivers/pci/controller/dwc/pcie-imx.c
> @@ -103,6 +103,7 @@ struct imx_pcie_drvdata {
> const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
> const struct pci_epc_features *epc_features;
> int (*init_phy)(struct imx_pcie *pcie);
> + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
> };
>
> struct imx_pcie {
> @@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev)
> return 0;
> }
>
> -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
> +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - unsigned int offset;
> - int ret = 0;
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
>
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6SX:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
> - break;
> - case IMX6QP:
> - case IMX6Q:
> + return 0;
> +}
> +
> +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> + if (enable) {
> /* power up core phy and enable ref clock */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0);
> /*
> - * the async reset input need ref clock to sync internally,
> - * when the ref clock comes after reset, internal synced
> - * reset time is too short, cannot meet the requirement.
> - * add one ~10us delay here.
> + * the async reset input need ref clock to sync internally, when the ref clock comes
> + * after reset, internal synced reset time is too short, cannot meet the
> + * requirement.add one ~10us delay here.
Please wrap the comments to 80 column width.
> */
> usleep_range(10, 100);
> regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> - break;
> - case IMX7D:
> - case IMX95:
> - case IMX95_EP:
> - break;
> - case IMX8MM:
> - case IMX8MM_EP:
> - case IMX8MQ:
> - case IMX8MQ_EP:
> - case IMX8MP:
> - case IMX8MP_EP:
> - offset = imx_pcie_grp_offset(imx_pcie);
> - /*
> - * Set the over ride low and enabled
> - * make sure that REF_CLK is turned on.
> - */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> - 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> - break;
> + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN);
> + } else {
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD);
> }
>
> - return ret;
> + return 0;
> }
>
> -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
> +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6QP:
> - case IMX6Q:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD,
> - IMX6Q_GPR1_PCIE_TEST_PD);
> - break;
> - case IMX7D:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> - break;
> - default:
> - break;
> - }
> + int offset = imx_pcie_grp_offset(imx_pcie);
> +
> + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
Extra space after :
> + return 0;
> +}
> +
> +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> + return 0;
> }
>
> static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> if (ret)
> return ret;
>
> - ret = imx_pcie_enable_ref_clk(imx_pcie);
> - if (ret) {
> - dev_err(dev, "unable to enable pcie ref clock\n");
> - goto err_ref_clk;
> + if (imx_pcie->drvdata->set_ref_clk) {
> + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true);
> + if (ret) {
> + dev_err(dev, "unable to enable pcie ref clock\n");
'Failed to enable PCIe REFCLK'
- Mani
--
மணிவண்ணன் சதாசிவம்
On Tue, Apr 02, 2024 at 10:33:41AM -0400, Frank Li wrote:
> Add me to imx pcie driver maintainer.
> Add mail list [email protected].
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> MAINTAINERS | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8d1052fa6a692..59a409dd604d8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16736,14 +16736,16 @@ F: drivers/pci/controller/pci-host-generic.c
>
> PCI DRIVER FOR IMX6
Don't you want to rename this too?
> M: Richard Zhu <[email protected]>
> +M: Frank Li <[email protected]>
> M: Lucas Stach <[email protected]>
> L: [email protected]
> +L: [email protected]
> L: [email protected] (moderated for non-subscribers)
> S: Maintained
> F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> -F: drivers/pci/controller/dwc/*imx6*
> +F: drivers/pci/controller/dwc/*imx*
>
> PCI DRIVER FOR INTEL IXP4XX
> M: Linus Walleij <[email protected]>
>
> --
> 2.34.1
>
On Sat, Apr 27, 2024 at 02:53:03PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Apr 02, 2024 at 10:33:38AM -0400, Frank Li wrote:
> > From: Richard Zhu <[email protected]>
> >
> > Fix i.MX8MP PCIe EP can't trigger MSI issue.
> > There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound
> > region configuration.
> >
> > EP uses Bar0 to set the outboud region to configure the MSI setting.
>
> I don't understand this statement. How EP can use BAR0 for MSI? MSIs are
> triggered using outbound window memory while BARs are mapped as inbound.
>
> - Mani
Let's rewrite commit message.
PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
i.MX8MP PCIe EP requires 64KB alignment. MSI triggering may fail if the
outbound MSI memory region (ep->msi_mem) is not aligned to 64KB.
In dw_pcie_ep_init():
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
epc->mem->window.page_size);
Set ep->page_size to match drvdata::epc_features::align since different
SOCs have different alignment requirements.
Frank
>
> > Set the page_size to "epc_features->align" to meet the requirement,
> > let the MSI can be triggered successfully.
> >
> > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code")
> > Signed-off-by: Richard Zhu <[email protected]>
> > Acked-by: Jason Liu <[email protected]>
> > Signed-off-by: Frank Li <[email protected]>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index e43eda6b33ca7..6c4d25b92225e 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
> > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
> > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
> >
> > + ep->page_size = imx6_pcie->drvdata->epc_features->align;
> > +
> > ret = dw_pcie_ep_init(ep);
> > if (ret) {
> > dev_err(dev, "failed to initialize endpoint\n");
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்