This series adds dispcc, videocc and camcc support for SM7150. This series
also introduces various fixes for sm7150-gcc.
David Wronek and Jens Reidel were added as maintainers. These people will
be able to test new features at any time or make fixes if necessary.
Changes in v3:
- Split patch 1 into two patches (patch 1 and patch 2) (Konrad)
- Drop CLK_GET_RATE_NOCACHE from dispcc (Konrad)
- Fix DisplayPort clocks (based on a series of patches from Dmitry Baryshkov):
https://lore.kernel.org/all/[email protected]/
- Fix typo in cover-letter-v2
- Link to v2:
https://lore.kernel.org/all/[email protected]/
Changes in v2:
- Drop patch 1 from v1
- Add Rob's R-b tag to patches no. 3, 5 and 7
- Switch disp_cc/dispcc, cam_cc/camcc and video_cc/videocc
- Make clk_init_data const for dispcc (For some reason this was missed in
the first version)
- Add gdsc cxcs for videocc
- Fix topology around titan_top power domain for camcc
- Drop the CAMCC_ prefix from camcc gdsc names
- Add flags for camcc gdscs
- Link to v1:
https://lore.kernel.org/all/[email protected]/
To: Bjorn Andersson <[email protected]>
To: Konrad Dybcio <[email protected]>
To: Michael Turquette <[email protected]>
To: Stephen Boyd <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Conor Dooley <[email protected]>
To: David Wronek <[email protected]>
To: Jens Reidel <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Danila Tikhonov <[email protected]>
.../bindings/clock/qcom,sm7150-camcc.yaml | 60 +
.../bindings/clock/qcom,sm7150-dispcc.yaml | 75 +
.../bindings/clock/qcom,sm7150-videocc.yaml | 58 +
drivers/clk/qcom/Kconfig | 29 +
drivers/clk/qcom/Makefile | 3 +
drivers/clk/qcom/camcc-sm7150.c | 2061 +++++++++++++++++
drivers/clk/qcom/dispcc-sm7150.c | 1006 ++++++++
drivers/clk/qcom/gcc-sm7150.c | 392 ++--
drivers/clk/qcom/videocc-sm7150.c | 357 +++
include/dt-bindings/clock/qcom,sm7150-camcc.h | 113 +
.../dt-bindings/clock/qcom,sm7150-dispcc.h | 59 +
.../dt-bindings/clock/qcom,sm7150-videocc.h | 28 +
12 files changed, 4045 insertions(+), 196 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml
create mode 100644 drivers/clk/qcom/camcc-sm7150.c
create mode 100644 drivers/clk/qcom/dispcc-sm7150.c
create mode 100644 drivers/clk/qcom/videocc-sm7150.c
create mode 100644 include/dt-bindings/clock/qcom,sm7150-camcc.h
create mode 100644 include/dt-bindings/clock/qcom,sm7150-dispcc.h
create mode 100644 include/dt-bindings/clock/qcom,sm7150-videocc.h
--
2.44.0
Add device tree bindings for the display clock controller on Qualcomm
SM7150 platform.
Co-developed-by: David Wronek <[email protected]>
Signed-off-by: David Wronek <[email protected]>
Signed-off-by: Danila Tikhonov <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/clock/qcom,sm7150-dispcc.yaml | 75 +++++++++++++++++++
.../dt-bindings/clock/qcom,sm7150-dispcc.h | 59 +++++++++++++++
2 files changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
create mode 100644 include/dt-bindings/clock/qcom,sm7150-dispcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
new file mode 100644
index 000000000000..b8d6e1d05ce2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller for SM7150
+
+maintainers:
+ - Danila Tikhonov <[email protected]>
+ - David Wronek <[email protected]>
+ - Jens Reidel <[email protected]>
+
+description: |
+ Qualcomm display clock control module provides the clocks, resets and power
+ domains on SM7150.
+
+ See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
+
+properties:
+ compatible:
+ const: qcom,sm7150-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: GPLL0 source from GCC
+ - description: Sleep clock source
+ - description: Byte clock from MDSS DSI PHY0
+ - description: Pixel clock from MDSS DSI PHY0
+ - description: Byte clock from MDSS DSI PHY1
+ - description: Pixel clock from MDSS DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ power-domains:
+ maxItems: 1
+ description:
+ CX power domain.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm7150-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm7150-dispcc";
+ reg = <0x0af00000 0x200000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&sleep_clk>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
new file mode 100644
index 000000000000..fc1fefe8fd72
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <[email protected]>
+ * Copyright (c) 2024, David Wronek <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
+
+/* DISPCC clock registers */
+#define DISPCC_PLL0 0
+#define DISPCC_MDSS_AHB_CLK 1
+#define DISPCC_MDSS_AHB_CLK_SRC 2
+#define DISPCC_MDSS_BYTE0_CLK 3
+#define DISPCC_MDSS_BYTE0_CLK_SRC 4
+#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5
+#define DISPCC_MDSS_BYTE0_INTF_CLK 6
+#define DISPCC_MDSS_BYTE1_CLK 7
+#define DISPCC_MDSS_BYTE1_CLK_SRC 8
+#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9
+#define DISPCC_MDSS_BYTE1_INTF_CLK 10
+#define DISPCC_MDSS_DP_AUX_CLK 11
+#define DISPCC_MDSS_DP_AUX_CLK_SRC 12
+#define DISPCC_MDSS_DP_CRYPTO_CLK 13
+#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14
+#define DISPCC_MDSS_DP_LINK_CLK 15
+#define DISPCC_MDSS_DP_LINK_CLK_SRC 16
+#define DISPCC_MDSS_DP_LINK_INTF_CLK 17
+#define DISPCC_MDSS_DP_PIXEL1_CLK 18
+#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19
+#define DISPCC_MDSS_DP_PIXEL_CLK 20
+#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21
+#define DISPCC_MDSS_ESC0_CLK 22
+#define DISPCC_MDSS_ESC0_CLK_SRC 23
+#define DISPCC_MDSS_ESC1_CLK 24
+#define DISPCC_MDSS_ESC1_CLK_SRC 25
+#define DISPCC_MDSS_MDP_CLK 26
+#define DISPCC_MDSS_MDP_CLK_SRC 27
+#define DISPCC_MDSS_MDP_LUT_CLK 28
+#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29
+#define DISPCC_MDSS_PCLK0_CLK 30
+#define DISPCC_MDSS_PCLK0_CLK_SRC 31
+#define DISPCC_MDSS_PCLK1_CLK 32
+#define DISPCC_MDSS_PCLK1_CLK_SRC 33
+#define DISPCC_MDSS_ROT_CLK 34
+#define DISPCC_MDSS_ROT_CLK_SRC 35
+#define DISPCC_MDSS_RSCC_AHB_CLK 36
+#define DISPCC_MDSS_RSCC_VSYNC_CLK 37
+#define DISPCC_MDSS_VSYNC_CLK 38
+#define DISPCC_MDSS_VSYNC_CLK_SRC 39
+#define DISPCC_XO_CLK_SRC 40
+#define DISPCC_SLEEP_CLK 41
+#define DISPCC_SLEEP_CLK_SRC 42
+
+/* DISPCC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
--
2.44.0