2024-05-07 09:50:54

by Manorit Chawdhry

[permalink] [raw]
Subject: [PATCH 0/5] Add bootph-all property for J7 boards

The idea of this series is to add bootph-all and bootph-pre-ram property
in all the leaf nodes wherever required and cleanup any other places where
bootph-all/bootph-pre-ram exist in the parent nodes as well.

Signed-off-by: Manorit Chawdhry <[email protected]>
---
Manorit Chawdhry (5):
arm64: dts: ti: k3-j721s2*: Add bootph-* properties
arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes
arm64: dts: ti: k3-am68*: Add bootph-* properties
arm64: dts: ti: k3-j721e*: Add bootph-* properties
arm64: dts: ti: k3-j7200*: Add bootph-* properties

arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 3 +++
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 ++++++++
.../boot/dts/ti/k3-j721e-common-proc-board.dts | 20 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 +++++++++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 17 ++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++
.../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 +++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 10 +---------
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 6 +++---
18 files changed, 141 insertions(+), 12 deletions(-)
---
base-commit: 11cb68ad52ac78c81e33b806b531f097e68edfa2
change-id: 20240430-b4-upstream-bootph-all-8d47b72bc0fd

Best regards,
--
Manorit Chawdhry <[email protected]>



2024-05-07 09:50:57

by Manorit Chawdhry

[permalink] [raw]
Subject: [PATCH 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 3 +++
2 files changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index d743f023cdd9..df97884cd1c5 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins {
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
+ bootph-all;
};

main_i2c0_pins_default: main-i2c0-default-pins {
@@ -210,6 +211,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};

vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -222,6 +224,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
+ bootph-all;
};

main_mcan6_pins_default: main-mcan6-default-pins {
@@ -312,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
+ bootph-all;
};

mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -412,12 +416,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};

&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};

&main_uart8 {
@@ -426,6 +432,7 @@ &main_uart8 {
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+ bootph-all;
};

&main_i2c0 {
@@ -520,6 +527,7 @@ &main_sdhci1 {
disable-wp;
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
+ bootph-all;
};

&mcu_cpsw {
@@ -652,6 +660,7 @@ &usbss0 {
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
+ bootph-all;
};

&usb0 {
@@ -659,4 +668,5 @@ &usb0 {
maximum-speed = "super-speed";
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
index 0f4a5da0ebc4..85f02d8c645d 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
@@ -14,6 +14,7 @@ memory@80000000 {
/* 16 GB RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x03 0x80000000>;
+ bootph-all;
};

reserved_memory: reserved-memory {
@@ -136,6 +137,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
};

@@ -149,6 +151,7 @@ eeprom@51 {
/* AT24C512C-MAHM-T */
compatible = "atmel,24c512";
reg = <0x51>;
+ bootph-all;
};
};


--
2.43.2


2024-05-07 09:51:23

by Manorit Chawdhry

[permalink] [raw]
Subject: [PATCH 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++
4 files changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index c5a0b7cbb14f..6ce14f9e087b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
+ bootph-all;
};

main_i2c3_pins_default: main-i2c3-default-pins {
@@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};

vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
+ bootph-all;
};

main_mcan3_pins_default: main-mcan3-default-pins {
@@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
+ bootph-all;
};

mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
+ bootph-all;
};

mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
+ bootph-all;
};
};

@@ -316,12 +322,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};

&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};

&main_uart8 {
@@ -330,6 +338,7 @@ &main_uart8 {
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+ bootph-all;
};

&main_i2c0 {
@@ -385,6 +394,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};

&main_sdhci1 {
@@ -395,6 +405,7 @@ &main_sdhci1 {
disable-wp;
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
+ bootph-all;
};

&mcu_cpsw {
@@ -446,11 +457,13 @@ &usbss0 {
pinctrl-names = "default";
ti,vbus-divider;
ti,usb2-only;
+ bootph-all;
};

&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
+ bootph-all;
};

&ospi1 {
@@ -469,6 +482,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
+ bootph-all;
};
};

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index b70c8615e3c1..fd1513f33616 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -828,6 +828,7 @@ secure_proxy_main: mailbox@32c00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};

hwspinlock: spinlock@30e00000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index eaf7f709440e..b5013bba8509 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ sms: system-controller@44083000 {
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};

k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};

k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};

@@ -43,6 +46,7 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};

@@ -59,6 +63,7 @@ secure_proxy_sa3: mailbox@43600000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};

mcu_ram: sram@41c00000 {
@@ -166,6 +171,7 @@ mcu_timer0: timer@40400000 {
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
+ bootph-pre-ram;
};

mcu_timer1: timer@40410000 {
@@ -360,6 +366,7 @@ wkup_i2c0: i2c@42120000 {
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
+ bootph-all;
};

mcu_i2c0: i2c@40b00000 {
@@ -472,6 +479,7 @@ mcu_ringacc: ringacc@2b800000 {
ti,sci = <&sms>;
ti,sci-dev-id = <272>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};

mcu_udmap: dma-controller@285c0000 {
@@ -495,6 +503,7 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};

@@ -511,6 +520,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};

mcu_cpsw: ethernet@46000000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 623c8421525d..f3898cd49ed9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -16,6 +16,7 @@ memory@80000000 {
/* 16 GB RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x03 0x80000000>;
+ bootph-all;
};

/* Reserving memory regions still pending */
@@ -444,6 +445,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+ bootph-all;
};
};


--
2.43.2


2024-05-07 10:05:48

by Manorit Chawdhry

[permalink] [raw]
Subject: [PATCH 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <[email protected]>
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 ++++++++
4 files changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6593c5da82c0..f7b96e8d6462 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
>;
+ bootph-all;
};

wkup_uart0_pins_default: wkup-uart0-default-pins {
@@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
>;
+ bootph-all;
};

mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -153,12 +155,14 @@ J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
+ bootph-all;
};

wkup_gpio_pins_default: wkup-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
+ bootph-all;
};

mcu_mdio_pins_default: mcu-mdio1-default-pins {
@@ -204,6 +208,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
>;
+ bootph-all;
};

main_uart1_pins_default: main-uart1-default-pins {
@@ -238,6 +243,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};

vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -259,6 +265,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
+ bootph-all;
};
};

@@ -267,12 +274,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};

&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};

&main_uart0 {
@@ -281,6 +290,7 @@ &main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ bootph-all;
};

&main_uart1 {
@@ -293,6 +303,7 @@ &main_uart1 {
&main_uart2 {
/* MAIN UART 2 is used by R5F firmware */
status = "reserved";
+ bootph-all; /* Doubtful if required or not */
};

&main_uart3 {
@@ -310,11 +321,13 @@ &wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
+ bootph-all;
};

&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
+ bootph-all;
};

&davinci_mdio {
@@ -341,6 +354,7 @@ exp1: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+ bootph-all;
};

exp2: gpio@22 {
@@ -348,6 +362,7 @@ exp2: gpio@22 {
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ bootph-all;
};
};

@@ -381,6 +396,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};

&main_sdhci1 {
@@ -392,15 +408,18 @@ &main_sdhci1 {
vqmmc-supply = <&vdd_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};

&serdes_ln_ctrl {
idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+ bootph-all;
};

&usb_serdes_mux {
idle-states = <1>; /* USB0 to SERDES lane 3 */
+ bootph-all;
};

&usbss0 {
@@ -408,11 +427,13 @@ &usbss0 {
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
ti,usb2-only;
+ bootph-all;
};

&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
+ bootph-all;
};

&tscadc0 {
@@ -432,6 +453,7 @@ serdes0_pcie_link: phy@0 {
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ bootph-all;
};

serdes0_qsgmii_link: phy@1 {
@@ -440,6 +462,7 @@ serdes0_qsgmii_link: phy@1 {
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz0 3>;
+ bootph-all;
};
};

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 657f9cc9f4ea..111eba71ed33 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};

hwspinlock: spinlock@30e00000 {
@@ -1538,5 +1539,6 @@ main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <656>, <657>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 7cf21c99956e..1e346451ee35 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};

k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};

k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};

@@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
+ bootph-pre-ram;
};

mcu_timer1: timer@40410000 {
@@ -187,6 +191,7 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};

@@ -347,6 +352,7 @@ mcu_ringacc: ringacc@2b800000 {
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};

mcu_udmap: dma-controller@285c0000 {
@@ -371,6 +377,7 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};

@@ -387,6 +394,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};

mcu_cpsw: ethernet@46000000 {
@@ -530,6 +538,7 @@ hbmc_mux: mux-controller@47000004 {
reg = <0x00 0x47000004 0x00 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x2>; /* HBMC select */
+ bootph-all;
};

hbmc: hyperbus@47034000 {
@@ -648,6 +657,7 @@ wkup_vtm0: temperature-sensor@42040000 {
<0x00 0x42050000 0x00 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
+ bootph-all;
};

mcu_esm: esm@40800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index 7e6a584ac6f0..a875a79e95c6 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -15,6 +15,7 @@ memory@80000000 {
/* 4G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x00 0x80000000>;
+ bootph-all;
};

reserved_memory: reserved-memory {
@@ -120,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
+ bootph-all;
};

mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@@ -136,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
>;
+ bootph-all;
};
};

@@ -145,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
};

@@ -162,6 +166,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>;
+ bootph-all;
};

main_mcan0_pins_default: main-mcan0-default-pins {
@@ -185,6 +190,7 @@ &hbmc {
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
+ bootph-all;

partitions {
compatible = "fixed-partitions";
@@ -329,6 +335,7 @@ bucka1: buck1 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
+ bootph-all;
};

bucka2: buck2 {
@@ -463,6 +470,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+ bootph-all;

partitions {
compatible = "fixed-partitions";

--
2.43.2


2024-05-28 09:05:51

by Limaye, Aniket

[permalink] [raw]
Subject: Re: [PATCH 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

Hi Manorit,

Had some comments below:
(Re-sending coz I forgot to change to plain-text formatting and the
mailing-list rejected it)


On 5/7/2024 3:14 PM, Manorit Chawdhry wrote:
> Adds bootph-* properties to the leaf nodes to enable U-boot to
> utilise them.
>
> Signed-off-by: Manorit Chawdhry <[email protected]>
> ---
> .../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 10 ++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 ++++++++
> 4 files changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 6593c5da82c0..f7b96e8d6462 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

[...]

>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 657f9cc9f4ea..111eba71ed33 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
> <0x00 0x32800000 0x00 0x100000>;
> interrupt-names = "rx_011";
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + bootph-all;
> };
>
> hwspinlock: spinlock@30e00000 {
> @@ -1538,5 +1539,6 @@ main_esm: esm@700000 {
> compatible = "ti,j721e-esm";
> reg = <0x0 0x700000 0x0 0x1000>;
> ti,esm-pins = <656>, <657>;
> + bootph-all;

Should this be bootph-pre-ram?

> };
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index 7cf21c99956e..1e346451ee35 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {

Do we need to add bootph-all property to the parent "dmsc" node too?

For some reason, for me, boot is failing without the bootph-all property
in the parent "dmsc" node here, even though it;s added to the child
nodes below

Failing logs with current patch (boot gets stuck) : [0]

If I ONLY add the bootph-all property to the dmsc node as well, the
device boots up just fine.


[0]: https://gist.github.com/aniket-l/a33a2e5d71432f6824310c8658929b40

> k3_pds: power-controller {
> compatible = "ti,sci-pm-domain";
> #power-domain-cells = <2>;
> + bootph-all;
> };
>
> k3_clks: clock-controller {
> compatible = "ti,k2g-sci-clk";
> #clock-cells = <2>;
> + bootph-all;
> };
>
> k3_reset: reset-controller {
> compatible = "ti,sci-reset";
> #reset-cells = <2>;
> + bootph-all;
> };
> };
>
> @@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
> assigned-clock-parents = <&k3_clks 35 2>;
> power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
> ti,timer-pwm;
> + bootph-pre-ram;
> };
>
> mcu_timer1: timer@40410000 {
> @@ -187,6 +191,7 @@ wkup_conf: bus@43000000 {
> chipid: chipid@14 {
> compatible = "ti,am654-chipid";
> reg = <0x14 0x4>;
> + bootph-all;
> };
> };
>
> @@ -347,6 +352,7 @@ mcu_ringacc: ringacc@2b800000 {
> ti,sci = <&dmsc>;
> ti,sci-dev-id = <235>;
> msi-parent = <&main_udmass_inta>;
> + bootph-all;
> };
>
> mcu_udmap: dma-controller@285c0000 {
> @@ -371,6 +377,7 @@ mcu_udmap: dma-controller@285c0000 {
> ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
> <0x0b>; /* RX_HCHAN */
> ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> + bootph-all;
> };
> };
>
> @@ -387,6 +394,7 @@ secure_proxy_mcu: mailbox@2a480000 {
> * firmware on non-MPU processors
> */
> status = "disabled";
> + bootph-pre-ram;
> };
>
> mcu_cpsw: ethernet@46000000 {
> @@ -530,6 +538,7 @@ hbmc_mux: mux-controller@47000004 {
> reg = <0x00 0x47000004 0x00 0x4>;
> #mux-control-cells = <1>;
> mux-reg-masks = <0x0 0x2>; /* HBMC select */
> + bootph-all;
> };
>
> hbmc: hyperbus@47034000 {
> @@ -648,6 +657,7 @@ wkup_vtm0: temperature-sensor@42040000 {
> <0x00 0x42050000 0x00 0x350>;
> power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
> #thermal-sensor-cells = <1>;
> + bootph-all;

Should this be bootph-pre-ram?

> };
>
> mcu_esm: esm@40800000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> index 7e6a584ac6f0..a875a79e95c6 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> @@ -15,6 +15,7 @@ memory@80000000 {
> /* 4G RAM */
> reg = <0x00 0x80000000 0x00 0x80000000>,
> <0x08 0x80000000 0x00 0x80000000>;
> + bootph-all;

Can you add the right indentation here?

> };
>
> reserved_memory: reserved-memory {
> @@ -120,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
> J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
> J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
> >;
> + bootph-all;
> };
>
> mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
> @@ -136,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
> J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
> J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
> >;
> + bootph-all;
> };
> };
>
[...]