This series aims to add support for the DesignWare MIPI DSI controller and
the Innoslicon DPHY found in RK3128 SoCs. The code additions are rather
tiny: It only need some code in the Rockchip dw-mipi-dsi glue layer for
this SoC and some changes in the clock driver. Support for the DPHY has
already been added when the driver was initially submitted. I tested it
with a 800x1280 DSI panel where all 4 lanes that are supported are used.
Alex Bee (7):
dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI
dt-bindings: clock: rk3128: Add PCLK_MIPIPHY
clk: rockchip: rk3128: Export PCLK_MIPIPHY
clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks
drm/rockchip: dsi: Add support for RK3128
ARM: dts: rockchip: Add DPHY for RK3128
ARM: dts: rockchip: Add DSI for RK3128
.../rockchip/rockchip,dw-mipi-dsi.yaml | 2 +
arch/arm/boot/dts/rockchip/rk3128.dtsi | 49 +++++++++++++++++++
drivers/clk/rockchip/clk-rk3128.c | 3 +-
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 ++++++++
include/dt-bindings/clock/rk3128-cru.h | 1 +
5 files changed, 74 insertions(+), 1 deletion(-)
--
2.43.2
The DPHY driver requires to specify a pclk so it gets exported here. I also
dropped the CLK_IGNORE_UNUSED-flag as we will enable the clock on demand.
Signed-off-by: Alex Bee <[email protected]>
---
drivers/clk/rockchip/clk-rk3128.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 75071e0cd321..a20d1fd25e2a 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -526,7 +526,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
- GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
+ GATE(PCLK_MIPIPHY, "pclk_mipiphy", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
--
2.43.2
Document the MIPI DSI controller for Rockchip RK3128. The integration is
similar to PX30 so it's bindings-constraints can be re-used.
Signed-off-by: Alex Bee <[email protected]>
---
.../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
index ccf79e738fa1..ccd71c5324af 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
@@ -15,6 +15,7 @@ properties:
items:
- enum:
- rockchip,px30-mipi-dsi
+ - rockchip,rk3128-mipi-dsi
- rockchip,rk3288-mipi-dsi
- rockchip,rk3399-mipi-dsi
- rockchip,rk3568-mipi-dsi
@@ -77,6 +78,7 @@ allOf:
contains:
enum:
- rockchip,px30-mipi-dsi
+ - rockchip,rk3128-mipi-dsi
- rockchip,rk3568-mipi-dsi
- rockchip,rv1126-mipi-dsi
--
2.43.2
The DesignWare MIPI DSI controller found RK3128 SoCs supports up to 4 dsi
data lanes. Similar to PX30/RK356x/RV1126 it uses an external DPHY.
Signed-off-by: Alex Bee <[email protected]>
---
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 4cc8ed8f4fbd..58a44af0e9ad 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -153,6 +153,11 @@
#define PX30_DSI_TURNDISABLE BIT(5)
#define PX30_DSI_LCDC_SEL BIT(0)
+#define RK3128_GRF_LVDS_CON0 0x0150
+#define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10)
+#define RK3128_DSI_FORCERXMODE BIT(9)
+#define RK3128_DSI_TURNDISABLE BIT(8)
+
#define RK3288_GRF_SOC_CON6 0x025c
#define RK3288_DSI0_LCDC_SEL BIT(6)
#define RK3288_DSI1_LCDC_SEL BIT(9)
@@ -1493,6 +1498,18 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
{ /* sentinel */ }
};
+static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
+ {
+ .reg = 0x10110000,
+ .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
+ RK3128_DSI_FORCERXMODE |
+ RK3128_DSI_FORCETXSTOPMODE),
+ .max_data_lanes = 4,
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
{
.reg = 0xff960000,
@@ -1670,6 +1687,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
{
.compatible = "rockchip,px30-mipi-dsi",
.data = &px30_chip_data,
+ }, {
+ .compatible = "rockchip,rk3128-mipi-dsi",
+ .data = &rk3128_chip_data,
}, {
.compatible = "rockchip,rk3288-mipi-dsi",
.data = &rk3288_chip_data,
--
2.43.2
The DPHY's APB clock is required to be exposed in order to be able to
enable it and access the phy's registers.
Signed-off-by: Alex Bee <[email protected]>
---
include/dt-bindings/clock/rk3128-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 6a47825dac5d..1be455ba4985 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -116,6 +116,7 @@
#define PCLK_GMAC 367
#define PCLK_PMU_PRE 368
#define PCLK_SIM_CARD 369
+#define PCLK_MIPIPHY 370
/* hclk gates */
#define HCLK_SPDIF 440
--
2.43.2
The DSI controller needs this clock to be enabled in order to be able to
access the registers. Make it critical for that purpose.
Signed-off-by: Alex Bee <[email protected]>
---
drivers/clk/rockchip/clk-rk3128.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index a20d1fd25e2a..d076b7971f33 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -563,6 +563,7 @@ static const char *const rk3128_critical_clocks[] __initconst = {
"pclk_cpu",
"aclk_peri",
"hclk_peri",
+ "hclk_vio_h2p",
"pclk_peri",
"pclk_pmu",
"sclk_timer5",
--
2.43.2
Add the Designware MIPI DSI controller and it's port nodes.
Signed-off-by: Alex Bee <[email protected]>
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index d16a9d03ba2b..93885338a80b 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -276,6 +276,42 @@ vop_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
+
+ vop_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_vop>;
+ };
+ };
+ };
+
+ dsi: dsi@10110000 {
+ compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x10110000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MIPI>;
+ clock-names = "pclk";
+ phys = <&dphy>;
+ phy-names = "dphy";
+ resets = <&cru SRST_VIO_MIPI_DSI>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ power-domains = <&power RK3128_PD_VIO>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in: port@0 {
+ reg = <0>;
+ dsi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_dsi>;
+ };
+ };
+
+ dsi_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.43.2
The InnoSilicon DPHY found in RK3128 SoCs supports DSI/LVDS/TTL with a
maximum transfer rate of 1 Gbps per lane. While at it also add the newly
exported PCLK_MIPIPHY clock id to RK3128_PD_VIO powerdomain as the phy is
part of it.
Signed-off-by: Alex Bee <[email protected]>
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index fb98873fd94e..d16a9d03ba2b 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -216,6 +216,7 @@ power-domain@RK3128_PD_VIO {
<&cru ACLK_LCDC0>,
<&cru HCLK_LCDC0>,
<&cru PCLK_MIPI>,
+ <&cru PCLK_MIPIPHY>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>,
<&cru ACLK_VIO0>,
@@ -496,6 +497,18 @@ hdmi_out: port@1 {
};
};
+ dphy: phy@20038000 {
+ compatible = "rockchip,rk3128-dsi-dphy";
+ reg = <0x20038000 0x4000>;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
+ clock-names = "ref", "pclk";
+ resets = <&cru SRST_MIPIPHY_P>;
+ reset-names = "apb";
+ power-domains = <&power RK3128_PD_VIO>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
timer0: timer@20044000 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
--
2.43.2
On Mon, May 06, 2024 at 09:43:37PM +0200, Alex Bee wrote:
> The DPHY's APB clock is required to be exposed in order to be able to
> enable it and access the phy's registers.
>
> Signed-off-by: Alex Bee <[email protected]>
Acked-by: Conor Dooley <[email protected]>
On Mon, May 06, 2024 at 09:43:36PM +0200, Alex Bee wrote:
> Document the MIPI DSI controller for Rockchip RK3128. The integration is
> similar to PX30 so it's bindings-constraints can be re-used.
>
> Signed-off-by: Alex Bee <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.