J722S has two USB instances. This series enables USB support for
both instances.
Ravi Gunasekaran (3):
arm64: dts: ti: k3-j722s: Add support for SERDES0
arm64: dts: ti: k3-j722s: Redefine USB1 node description
arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 configuration for
EVM
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 93 +++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-serdes.h | 7 ++
3 files changed, 158 insertions(+)
base-commit: b0a2c79c6f3590b74742cbbc76687014d47972d8
--
2.17.1
Add SERDES0 and its wrapper description to support USB3
and SGMII interfaces.
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c75744edb143..beba5a3ea6cc 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include <dt-bindings/phy/phy-ti.h>
#include "k3-am62p5.dtsi"
@@ -75,6 +76,50 @@
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
};
+
+ serdes_refclk: clock-cmnrefclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ serdes_wiz0: wiz@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 279 1>;
+ assigned-clock-parents = <&k3_clks 279 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 279 1>,
+ <&k3_clks 279 1>,
+ <&k3_clks 279 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
};
/* Main domain overrides */
@@ -83,6 +128,15 @@
ti,interrupt-ranges = <7 71 21>;
};
+&main_conf {
+ serdes0_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
+ };
+};
+
&oc_sram {
reg = <0x00 0x70000000 0x00 0x40000>;
ranges = <0x00 0x00 0x70000000 0x40000>;
--
2.17.1
USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 39 ++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index beba5a3ea6cc..90725eeb3178 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -13,6 +13,13 @@
#include "k3-am62p5.dtsi"
+/*
+ * USB1 controller on AM62P and J722S are of different IP.
+ * Delete AM62P's USBSS1 node definition and redefine it for J722S.
+ */
+
+/delete-node/ &usbss1;
+
/ {
model = "Texas Instruments K3 J722S SoC";
compatible = "ti,j722s";
@@ -120,6 +127,38 @@
status = "disabled"; /* Needs lane config */
};
};
+
+ usbss1: cdns-usb@f920000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x0f920000 0x00 0x100>;
+ ranges;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ usb1: usb@31200000{
+ compatible = "cdns,usb3";
+ reg = <0x00 0x31200000 0x00 0x10000>,
+ <0x00 0x31210000 0x00 0x10000>,
+ <0x00 0x31220000 0x00 0x10000>;
+ reg-names = "otg",
+ "xhci",
+ "dev";
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
};
/* Main domain overrides */
--
2.17.1
The GPIO expander on the EVM allows the USB selection for Type-C
port to either USB0 or USB1 via USB hub. By default, let the Type-C
port select USB0 via the GPIO expander port P05.
Enable super-speed on USB1 by updating SerDes0 lane configuration.
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-serdes.h | 7 +++
2 files changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1..ddb4f1f0d92d 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
#include "k3-j722s.dtsi"
+#include "k3-serdes.h"
/ {
compatible = "ti,j722s-evm", "ti,j722s";
@@ -20,6 +22,8 @@
serial2 = &main_uart0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
+ usb0 = &usb0;
+ usb1 = &usb1;
};
chosen {
@@ -202,6 +206,12 @@
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+ >;
+ };
};
&cpsw3g {
@@ -301,6 +311,14 @@
"PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
"ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
"PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+ p05-hog {
+ /* P05 - USB2.0_MUX_SEL */
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "USB2.0_MUX_SEL";
+ };
};
};
@@ -384,3 +402,43 @@
status = "okay";
bootph-all;
};
+
+&serdes0_ln_ctrl {
+ idle-states = <J722S_SERDES0_LANE0_USB>,
+ <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index a011ad893b44..9082abeddcb1 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -201,4 +201,11 @@
#define J784S4_SERDES4_LANE3_USB 0x2
#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
+/* J722S */
+#define J722S_SERDES0_LANE0_USB 0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
+
+#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
+
#endif /* DTS_ARM64_TI_K3_SERDES_H */
--
2.17.1
On Mon, Apr 29, 2024 at 05:39:32PM +0530, Ravi Gunasekaran wrote:
> The GPIO expander on the EVM allows the USB selection for Type-C
> port to either USB0 or USB1 via USB hub. By default, let the Type-C
> port select USB0 via the GPIO expander port P05.
>
> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-serdes.h | 7 +++
> 2 files changed, 65 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index bf3c246d13d1..ddb4f1f0d92d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -9,7 +9,9 @@
> /dts-v1/;
>
> #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy.h>
> #include "k3-j722s.dtsi"
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,j722s-evm", "ti,j722s";
> @@ -20,6 +22,8 @@
> serial2 = &main_uart0;
> mmc0 = &sdhci0;
> mmc1 = &sdhci1;
> + usb0 = &usb0;
> + usb1 = &usb1;
Why is this needed? Doesn't look related?
> };
>
> chosen {
> @@ -202,6 +206,12 @@
> J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
> >;
> };
> +
> + main_usb1_pins_default: main-usb1-default-pins {
> + pinctrl-single,pins = <
> + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
> + >;
> + };
> };
>
> &cpsw3g {
> @@ -301,6 +311,14 @@
> "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
> "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
> "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
> +
> + p05-hog {
> + /* P05 - USB2.0_MUX_SEL */
> + gpio-hog;
> + gpios = <5 GPIO_ACTIVE_LOW>;
> + output-high;
> + line-name = "USB2.0_MUX_SEL";
> + };
> };
> };
>
> @@ -384,3 +402,43 @@
> status = "okay";
> bootph-all;
> };
> +
> +&serdes0_ln_ctrl {
> + idle-states = <J722S_SERDES0_LANE0_USB>,
> + <J722S_SERDES1_LANE0_PCIE0_LANE0>;
> +};
> +
> +&serdes0 {
> + status = "okay";
> + serdes0_usb_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + usb-role-switch;
> +};
> +
> +&usbss1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usb1_pins_default>;
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb1 {
> + dr_mode = "host";
> + maximum-speed = "super-speed";
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> index a011ad893b44..9082abeddcb1 100644
> --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -201,4 +201,11 @@
> #define J784S4_SERDES4_LANE3_USB 0x2
> #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
>
> +/* J722S */
> +#define J722S_SERDES0_LANE0_USB 0x0
> +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
> +
> +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
> +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
> +
> #endif /* DTS_ARM64_TI_K3_SERDES_H */
> --
> 2.17.1
>
On 4/29/24 7:09 AM, Ravi Gunasekaran wrote:
> USB1 controller on J722S and AM62P are from different vendors.
> Redefine the USB1 node description for J722S by deleting the
> node inherited from AM62P dtsi.
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 39 ++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index beba5a3ea6cc..90725eeb3178 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -13,6 +13,13 @@
>
> #include "k3-am62p5.dtsi"
>
> +/*
> + * USB1 controller on AM62P and J722S are of different IP.
> + * Delete AM62P's USBSS1 node definition and redefine it for J722S.
> + */
> +
> +/delete-node/ &usbss1;
> +
> / {
> model = "Texas Instruments K3 J722S SoC";
> compatible = "ti,j722s";
> @@ -120,6 +127,38 @@
> status = "disabled"; /* Needs lane config */
> };
> };
> +
> + usbss1: cdns-usb@f920000 {
MAIN domain items are defined in -main.dtsi files, for instance the
USB node you are overriding was defined in k3-am62p-main.dtsi.
This should go in a file named k3-j722s-main.dtsi.
Andrew
> + compatible = "ti,j721e-usb";
> + reg = <0x00 0x0f920000 0x00 0x100>;
> + ranges;
> + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
> + clock-names = "ref", "lpm";
> + assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
> + assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
> + #address-cells = <2>;
> + #size-cells = <2>;
> + status = "disabled";
> +
> + usb1: usb@31200000{
> + compatible = "cdns,usb3";
> + reg = <0x00 0x31200000 0x00 0x10000>,
> + <0x00 0x31210000 0x00 0x10000>,
> + <0x00 0x31220000 0x00 0x10000>;
> + reg-names = "otg",
> + "xhci",
> + "dev";
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
> + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
> + interrupt-names = "host",
> + "peripheral",
> + "otg";
> + maximum-speed = "super-speed";
> + dr_mode = "otg";
> + };
> + };
> };
>
> /* Main domain overrides */
On 5/7/24 10:45 PM, Andrew Davis wrote:
> On 4/29/24 7:09 AM, Ravi Gunasekaran wrote:
>> USB1 controller on J722S and AM62P are from different vendors.
>> Redefine the USB1 node description for J722S by deleting the
>> node inherited from AM62P dtsi.
>>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 39 ++++++++++++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> index beba5a3ea6cc..90725eeb3178 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> @@ -13,6 +13,13 @@
>> #include "k3-am62p5.dtsi"
>> +/*
>> + * USB1 controller on AM62P and J722S are of different IP.
>> + * Delete AM62P's USBSS1 node definition and redefine it for J722S.
>> + */
>> +
>> +/delete-node/ &usbss1;
>> +
>> / {
>> model = "Texas Instruments K3 J722S SoC";
>> compatible = "ti,j722s";
>> @@ -120,6 +127,38 @@
>> status = "disabled"; /* Needs lane config */
>> };
>> };
>> +
>> + usbss1: cdns-usb@f920000 {
>
> MAIN domain items are defined in -main.dtsi files, for instance the
> USB node you are overriding was defined in k3-am62p-main.dtsi.
> This should go in a file named k3-j722s-main.dtsi.
>
> Andrew
>
Ok. I will introduce k3-j722s-main.dtsi newly and define the USB
and SerDes nodes there.
[...]
--
Regards,
Ravi
On 5/7/24 8:31 PM, Rob Herring wrote:
> On Mon, Apr 29, 2024 at 05:39:32PM +0530, Ravi Gunasekaran wrote:
>> The GPIO expander on the EVM allows the USB selection for Type-C
>> port to either USB0 or USB1 via USB hub. By default, let the Type-C
>> port select USB0 via the GPIO expander port P05.
>>
>> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/ti/k3-serdes.h | 7 +++
>> 2 files changed, 65 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
>> index bf3c246d13d1..ddb4f1f0d92d 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
>> @@ -9,7 +9,9 @@
>> /dts-v1/;
>>
>> #include <dt-bindings/net/ti-dp83867.h>
>> +#include <dt-bindings/phy/phy.h>
>> #include "k3-j722s.dtsi"
>> +#include "k3-serdes.h"
>>
>> / {
>> compatible = "ti,j722s-evm", "ti,j722s";
>> @@ -20,6 +22,8 @@
>> serial2 = &main_uart0;
>> mmc0 = &sdhci0;
>> mmc1 = &sdhci1;
>> + usb0 = &usb0;
>> + usb1 = &usb1;
>
> Why is this needed? Doesn't look related?
I rechecked, it is not needed, I will remove it in v2.
>
>> };
>>
[...]
--
Regards,
Ravi
On 29/04/2024 15:09, Ravi Gunasekaran wrote:
> Add SERDES0 and its wrapper description to support USB3
> and SGMII interfaces.
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index c75744edb143..beba5a3ea6cc 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/soc/ti,sci_pm_domain.h>
> +#include <dt-bindings/phy/phy-ti.h>
>
> #include "k3-am62p5.dtsi"
>
> @@ -75,6 +76,50 @@
> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
> };
> +
> + serdes_refclk: clock-cmnrefclk {
What could be the generic name here?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + serdes_wiz0: wiz@f000000 {
Should generic name be phy?
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 279 1>;
> + assigned-clock-parents = <&k3_clks 279 5>;
> +
> + serdes0: serdes@f000000 {
here too?
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x0f000000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 279 1>,
> + <&k3_clks 279 1>,
> + <&k3_clks 279 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled"; /* Needs lane config */
> + };
> + };
> };
>
> /* Main domain overrides */
> @@ -83,6 +128,15 @@
> ti,interrupt-ranges = <7 71 21>;
> };
>
> +&main_conf {
> + serdes0_ln_ctrl: mux-controller@4080 {
> + compatible = "reg-mux";
> + reg = <0x4080 0x4>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
> + };
> +};
> +
> &oc_sram {
> reg = <0x00 0x70000000 0x00 0x40000>;
> ranges = <0x00 0x00 0x70000000 0x40000>;
--
cheers,
-roger
On 29/04/2024 15:09, Ravi Gunasekaran wrote:
> The GPIO expander on the EVM allows the USB selection for Type-C
> port to either USB0 or USB1 via USB hub. By default, let the Type-C
> port select USB0 via the GPIO expander port P05.
>
> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-serdes.h | 7 +++
> 2 files changed, 65 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index bf3c246d13d1..ddb4f1f0d92d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -9,7 +9,9 @@
> /dts-v1/;
>
> #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy.h>
> #include "k3-j722s.dtsi"
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,j722s-evm", "ti,j722s";
> @@ -20,6 +22,8 @@
> serial2 = &main_uart0;
> mmc0 = &sdhci0;
> mmc1 = &sdhci1;
> + usb0 = &usb0;
> + usb1 = &usb1;
> };
>
> chosen {
> @@ -202,6 +206,12 @@
> J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
> >;
> };
> +
> + main_usb1_pins_default: main-usb1-default-pins {
> + pinctrl-single,pins = <
> + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
> + >;
> + };
> };
>
> &cpsw3g {
> @@ -301,6 +311,14 @@
> "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
> "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
> "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
> +
> + p05-hog {
> + /* P05 - USB2.0_MUX_SEL */
> + gpio-hog;
> + gpios = <5 GPIO_ACTIVE_LOW>;
> + output-high;
> + line-name = "USB2.0_MUX_SEL";
This line-name is already added in gpio-line-names property above.
Do we really need to add it again?
> + };
> };
> };
>
> @@ -384,3 +402,43 @@
> status = "okay";
> bootph-all;
> };
> +
> +&serdes0_ln_ctrl {
> + idle-states = <J722S_SERDES0_LANE0_USB>,
> + <J722S_SERDES1_LANE0_PCIE0_LANE0>;
> +};
> +
> +&serdes0 {
> + status = "okay";
> + serdes0_usb_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + usb-role-switch;
> +};
> +
> +&usbss1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usb1_pins_default>;
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb1 {
> + dr_mode = "host";
> + maximum-speed = "super-speed";
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> index a011ad893b44..9082abeddcb1 100644
> --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -201,4 +201,11 @@
> #define J784S4_SERDES4_LANE3_USB 0x2
> #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
>
> +/* J722S */
> +#define J722S_SERDES0_LANE0_USB 0x0
> +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
> +
> +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
> +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
> +
> #endif /* DTS_ARM64_TI_K3_SERDES_H */
--
cheers,
-roger
On 5/8/24 5:29 PM, Roger Quadros wrote:
>
>
> On 29/04/2024 15:09, Ravi Gunasekaran wrote:
>> Add SERDES0 and its wrapper description to support USB3
>> and SGMII interfaces.
>>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++
>> 1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> index c75744edb143..beba5a3ea6cc 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> @@ -9,6 +9,7 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/soc/ti,sci_pm_domain.h>
>> +#include <dt-bindings/phy/phy-ti.h>
>>
>> #include "k3-am62p5.dtsi"
>>
>> @@ -75,6 +76,50 @@
>> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
>> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
>> };
>> +
>> + serdes_refclk: clock-cmnrefclk {
>
> What could be the generic name here?
>
How about phy-clk or serdes-clk?
I searched for "fixed-clock" and wide range of naming conventions is followed.
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <0>;
>> + };
>> +
>> + serdes_wiz0: wiz@f000000 {
>
> Should generic name be phy?
Since serdes is used for both USB and PCIe,
I can go with "phy".
>
>> + compatible = "ti,am64-wiz-10g";
>> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
>> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
>> + num-lanes = <1>;
>> + #reset-cells = <1>;
>> + #clock-cells = <1>;
>> +
>> + assigned-clocks = <&k3_clks 279 1>;
>> + assigned-clock-parents = <&k3_clks 279 5>;
>> +
>> + serdes0: serdes@f000000 {
>
> here too?
I could use "phy" here as well.
https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/sa8775p.dtsi#L1853
https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/renesas/r8a779f0.dtsi#L563
>
>> + compatible = "ti,j721e-serdes-10g";
[...]
>
--
Regards,
Ravi
On 5/8/24 5:33 PM, Roger Quadros wrote:
>
>
> On 29/04/2024 15:09, Ravi Gunasekaran wrote:
>> The GPIO expander on the EVM allows the USB selection for Type-C
>> port to either USB0 or USB1 via USB hub. By default, let the Type-C
>> port select USB0 via the GPIO expander port P05.
>>
>> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/ti/k3-serdes.h | 7 +++
>> 2 files changed, 65 insertions(+)
>>
[...]
>> +
>> + p05-hog {
>> + /* P05 - USB2.0_MUX_SEL */
>> + gpio-hog;
>> + gpios = <5 GPIO_ACTIVE_LOW>;
>> + output-high;
>> + line-name = "USB2.0_MUX_SEL";
>
> This line-name is already added in gpio-line-names property above.
> Do we really need to add it again?
Not needed. If the line-name property is not present for the hog,
then its taken from the gpio chip via gpio-line-names.
So I will remove the line-name property in v2
static struct gpio_desc *of_parse_own_gpio(...)
..
if (name && of_property_read_string(np, "line-name", name))
*name = np->name;
..
>
>> + };
>> };
>> };
>>
[...]
--
Regards,
Ravi
On 08/05/2024 15:34, Ravi Gunasekaran wrote:
>
>
> On 5/8/24 5:29 PM, Roger Quadros wrote:
>>
>>
>> On 29/04/2024 15:09, Ravi Gunasekaran wrote:
>>> Add SERDES0 and its wrapper description to support USB3
>>> and SGMII interfaces.
>>>
>>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++
>>> 1 file changed, 54 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>> index c75744edb143..beba5a3ea6cc 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>> @@ -9,6 +9,7 @@
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/soc/ti,sci_pm_domain.h>
>>> +#include <dt-bindings/phy/phy-ti.h>
>>>
>>> #include "k3-am62p5.dtsi"
>>>
>>> @@ -75,6 +76,50 @@
>>> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
>>> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
>>> };
>>> +
>>> + serdes_refclk: clock-cmnrefclk {
>>
>> What could be the generic name here?
>>
>
> How about phy-clk or serdes-clk?
> I searched for "fixed-clock" and wide range of naming conventions is followed.
We shouldn't encode the clock function in the name. How about just clk-<n> ?
where <n> is an integer starting from 0 for such fixed-clocks on the platform?
e.g. from arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
tlv320_mclk: clk-0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12288000>;
};
>
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <0>;
>>> + };
>>> +
>>> + serdes_wiz0: wiz@f000000 {
>>
>> Should generic name be phy?
>
> Since serdes is used for both USB and PCIe,
> I can go with "phy".
>
>>
>>> + compatible = "ti,am64-wiz-10g";
>>> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
>>> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
>>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
>>> + num-lanes = <1>;
>>> + #reset-cells = <1>;
>>> + #clock-cells = <1>;
>>> +
>>> + assigned-clocks = <&k3_clks 279 1>;
>>> + assigned-clock-parents = <&k3_clks 279 5>;
>>> +
>>> + serdes0: serdes@f000000 {
>>
>> here too?
>
> I could use "phy" here as well.
> https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/sa8775p.dtsi#L1853
> https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/renesas/r8a779f0.dtsi#L563
>
>>
>>> + compatible = "ti,j721e-serdes-10g";
>
> [...]
>
>>
>
--
cheers,
-roger
On 5/8/24 6:32 PM, Roger Quadros wrote:
>
>
> On 08/05/2024 15:34, Ravi Gunasekaran wrote:
>>
>>
>> On 5/8/24 5:29 PM, Roger Quadros wrote:
>>>
>>>
>>> On 29/04/2024 15:09, Ravi Gunasekaran wrote:
>>>> Add SERDES0 and its wrapper description to support USB3
>>>> and SGMII interfaces.
>>>>
>>>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++
>>>> 1 file changed, 54 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>>> index c75744edb143..beba5a3ea6cc 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>>> @@ -9,6 +9,7 @@
>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> #include <dt-bindings/soc/ti,sci_pm_domain.h>
>>>> +#include <dt-bindings/phy/phy-ti.h>
>>>>
>>>> #include "k3-am62p5.dtsi"
>>>>
>>>> @@ -75,6 +76,50 @@
>>>> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
>>>> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
>>>> };
>>>> +
>>>> + serdes_refclk: clock-cmnrefclk {
>>>
>>> What could be the generic name here?
>>>
>>
>> How about phy-clk or serdes-clk?
>> I searched for "fixed-clock" and wide range of naming conventions is followed.
>
> We shouldn't encode the clock function in the name. How about just clk-<n> ?
> where <n> is an integer starting from 0 for such fixed-clocks on the platform?
>
Sure. I can follow this notation.
> e.g. from arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
>
> tlv320_mclk: clk-0 {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <12288000>;
> };
>
>>
[...]
>>
>
--
Regards,
Ravi