This patch series adds outbound inline ipsec support on Marvell
cn10k series of platform. One crypto hardware logical function
(cpt-lf) per netdev is required for inline ipsec outbound
functionality. Software prepare and submit crypto hardware
(CPT) instruction for outbound inline ipsec crypto mode offload.
The CPT instruction have details for encryption and authentication
Crypto hardware encrypt, authenticate and provide the ESP packet
to network hardware logic to transmit ipsec packet.
First patch makes dma memory writable for in-place encryption,
Second patch moves code to common file, Third patch disable
backpressure on crypto (CPT) and network (NIX) hardware.
Patch four onwards enables inline outbound ipsec.
v1->v2:
- Fix compilation error to build driver a module
- Use dma_wmb() instead of architecture specific barrier
- Fix couple of other compilation warnings
Bharat Bhushan (8):
octeontx2-pf: map skb data as device writeable
octeontx2-pf: Move skb fragment map/unmap to common code
octeontx2-af: Disable backpressure between CPT and NIX
cn10k-ipsec: Initialize crypto hardware for outb inline ipsec
cn10k-ipsec: Add SA add/delete support for outb inline ipsec
cn10k-ipsec: Process inline ipsec transmit offload
cn10k-ipsec: Allow inline ipsec offload for skb with SA
cn10k-ipsec: Enable outbound inline ipsec offload
.../net/ethernet/marvell/octeontx2/af/mbox.h | 4 +
.../ethernet/marvell/octeontx2/af/rvu_nix.c | 74 +-
.../ethernet/marvell/octeontx2/nic/Makefile | 1 +
.../marvell/octeontx2/nic/cn10k_ipsec.c | 1068 +++++++++++++++++
.../marvell/octeontx2/nic/cn10k_ipsec.h | 258 ++++
.../marvell/octeontx2/nic/otx2_common.c | 80 ++
.../marvell/octeontx2/nic/otx2_common.h | 25 +
.../marvell/octeontx2/nic/otx2_dcbnl.c | 3 +
.../ethernet/marvell/octeontx2/nic/otx2_pf.c | 19 +-
.../marvell/octeontx2/nic/otx2_txrx.c | 65 +-
.../marvell/octeontx2/nic/otx2_txrx.h | 3 +
.../ethernet/marvell/octeontx2/nic/otx2_vf.c | 10 +-
12 files changed, 1563 insertions(+), 47 deletions(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
--
2.34.1
NIX can assert backpressure to CPT on the NIX<=>CPT link.
Keep the backpressure disabled for now. NIX block anyways
handles backpressure asserted by MAC due to PFC or flow
control pkts.
Signed-off-by: Bharat Bhushan <[email protected]>
---
.../net/ethernet/marvell/octeontx2/af/mbox.h | 4 +
.../ethernet/marvell/octeontx2/af/rvu_nix.c | 74 ++++++++++++++++---
.../marvell/octeontx2/nic/otx2_common.c | 25 +++++++
.../marvell/octeontx2/nic/otx2_common.h | 1 +
.../marvell/octeontx2/nic/otx2_dcbnl.c | 3 +
.../ethernet/marvell/octeontx2/nic/otx2_pf.c | 3 +
6 files changed, 100 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 4a77f6fe2622..0cb399b8d2ca 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -309,6 +309,10 @@ M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
msg_rsp) \
M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
nix_bandprof_get_hwinfo_rsp) \
+M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
+ nix_bp_cfg_rsp) \
+M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
+ msg_rsp) \
M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
msg_req, nix_inline_ipsec_cfg) \
M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 00af8888e329..fbb45993ad0c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -567,9 +567,9 @@ void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc)
mutex_unlock(&rvu->rsrc_lock);
}
-int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
- struct nix_bp_cfg_req *req,
- struct msg_rsp *rsp)
+static int nix_bp_disable(struct rvu *rvu,
+ struct nix_bp_cfg_req *req,
+ struct msg_rsp *rsp, bool cpt_link)
{
u16 pcifunc = req->hdr.pcifunc;
int blkaddr, pf, type, err;
@@ -577,6 +577,7 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
struct rvu_pfvf *pfvf;
struct nix_hw *nix_hw;
struct nix_bp *bp;
+ u16 chan_v;
u64 cfg;
pf = rvu_get_pf(pcifunc);
@@ -584,6 +585,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)
return 0;
+ if (cpt_link && !rvu->hw->cpt_links)
+ return 0;
+
pfvf = rvu_get_pfvf(rvu, pcifunc);
err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
if (err)
@@ -592,8 +596,16 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
bp = &nix_hw->bp;
chan_base = pfvf->rx_chan_base + req->chan_base;
for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
- cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
- rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
+ /* CPT channel for a given link channel is always
+ * assumed to be BIT(11) set in link channel.
+ */
+ if (cpt_link)
+ chan_v = chan | BIT(11);
+ else
+ chan_v = chan;
+
+ cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v));
+ rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
cfg & ~BIT_ULL(16));
if (type == NIX_INTF_TYPE_LBK) {
@@ -612,6 +624,20 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
return 0;
}
+int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
+ struct nix_bp_cfg_req *req,
+ struct msg_rsp *rsp)
+{
+ return nix_bp_disable(rvu, req, rsp, false);
+}
+
+int rvu_mbox_handler_nix_cpt_bp_disable(struct rvu *rvu,
+ struct nix_bp_cfg_req *req,
+ struct msg_rsp *rsp)
+{
+ return nix_bp_disable(rvu, req, rsp, true);
+}
+
static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
int type, int chan_id)
{
@@ -691,15 +717,17 @@ static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
return bpid;
}
-int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
- struct nix_bp_cfg_req *req,
- struct nix_bp_cfg_rsp *rsp)
+static int nix_bp_enable(struct rvu *rvu,
+ struct nix_bp_cfg_req *req,
+ struct nix_bp_cfg_rsp *rsp,
+ bool cpt_link)
{
int blkaddr, pf, type, chan_id = 0;
u16 pcifunc = req->hdr.pcifunc;
struct rvu_pfvf *pfvf;
u16 chan_base, chan;
s16 bpid, bpid_base;
+ u16 chan_v;
u64 cfg;
pf = rvu_get_pf(pcifunc);
@@ -712,6 +740,9 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
type != NIX_INTF_TYPE_SDP)
return 0;
+ if (cpt_link && !rvu->hw->cpt_links)
+ return 0;
+
pfvf = rvu_get_pfvf(rvu, pcifunc);
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
@@ -725,9 +756,18 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
return -EINVAL;
}
- cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
+ /* CPT channel for a given link channel is always
+ * assumed to be BIT(11) set in link channel.
+ */
+
+ if (cpt_link)
+ chan_v = chan | BIT(11);
+ else
+ chan_v = chan;
+
+ cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v));
cfg &= ~GENMASK_ULL(8, 0);
- rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
+ rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16));
chan_id++;
bpid = rvu_nix_get_bpid(rvu, req, type, chan_id);
@@ -745,6 +785,20 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
return 0;
}
+int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
+ struct nix_bp_cfg_req *req,
+ struct nix_bp_cfg_rsp *rsp)
+{
+ return nix_bp_enable(rvu, req, rsp, false);
+}
+
+int rvu_mbox_handler_nix_cpt_bp_enable(struct rvu *rvu,
+ struct nix_bp_cfg_req *req,
+ struct nix_bp_cfg_rsp *rsp)
+{
+ return nix_bp_enable(rvu, req, rsp, true);
+}
+
static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
u64 format, bool v4, u64 *fidx)
{
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
index 7ec99c8d610c..e9d2e039a322 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
@@ -1705,6 +1705,31 @@ int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
}
EXPORT_SYMBOL(otx2_nix_config_bp);
+int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable)
+{
+ struct nix_bp_cfg_req *req;
+
+ if (enable)
+ req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf->mbox);
+ else
+ req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf->mbox);
+
+ if (!req)
+ return -ENOMEM;
+
+ req->chan_base = 0;
+#ifdef CONFIG_DCB
+ req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
+ req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
+#else
+ req->chan_cnt = 1;
+ req->bpid_per_chan = 0;
+#endif
+
+ return otx2_sync_mbox_msg(&pfvf->mbox);
+}
+EXPORT_SYMBOL(otx2_nix_cpt_config_bp);
+
/* Mbox message handlers */
void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
struct cgx_stats_rsp *rsp)
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
index 99b480e21e1c..42a759a33c11 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
@@ -987,6 +987,7 @@ int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
+int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable);
void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx);
void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c
index 28fb643d2917..da28725adcf8 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c
@@ -424,6 +424,9 @@ static int otx2_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)
return err;
}
+ /* Default disable backpressure on NIX-CPT */
+ otx2_nix_cpt_config_bp(pfvf, false);
+
/* Request Per channel Bpids */
if (pfc->pfc_en)
otx2_nix_config_bp(pfvf, true);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
index f5bce3e326cc..cbd5050f58e8 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
@@ -1509,6 +1509,9 @@ static int otx2_init_hw_resources(struct otx2_nic *pf)
if (err)
goto err_free_npa_lf;
+ /* Default disable backpressure on NIX-CPT */
+ otx2_nix_cpt_config_bp(pf, false);
+
/* Enable backpressure for CGX mapped PF/VFs */
if (!is_otx2_lbkvf(pf->pdev))
otx2_nix_config_bp(pf, true);
--
2.34.1
One crypto hardware logical function (cpt-lf) per netdev is
required for inline ipsec outbound functionality. Allocate,
attach and initialize one crypto hardware function when
enabling inline ipsec crypto offload. Crypto hardware
function will be detached and freed on disabling inline
ipsec.
Signed-off-by: Bharat Bhushan <[email protected]>
---
v1->v2:
- Fix compilation error to build driver a module
- Fix couple of compilation warnings
.../ethernet/marvell/octeontx2/nic/Makefile | 1 +
.../marvell/octeontx2/nic/cn10k_ipsec.c | 393 ++++++++++++++++++
.../marvell/octeontx2/nic/cn10k_ipsec.h | 104 +++++
.../marvell/octeontx2/nic/otx2_common.h | 18 +
.../ethernet/marvell/octeontx2/nic/otx2_pf.c | 14 +-
.../ethernet/marvell/octeontx2/nic/otx2_vf.c | 10 +-
6 files changed, 538 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
index 5664f768cb0c..9695f967d416 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile
@@ -14,5 +14,6 @@ rvu_nicvf-y := otx2_vf.o otx2_devlink.o
rvu_nicpf-$(CONFIG_DCB) += otx2_dcbnl.o
rvu_nicvf-$(CONFIG_DCB) += otx2_dcbnl.o
rvu_nicpf-$(CONFIG_MACSEC) += cn10k_macsec.o
+rvu_nicpf-$(CONFIG_XFRM_OFFLOAD) += cn10k_ipsec.o
ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
new file mode 100644
index 000000000000..46db9fd94ca3
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell IPSEC offload driver
+ *
+ * Copyright (C) 2024 Marvell.
+ */
+
+#include <net/xfrm.h>
+#include <linux/netdevice.h>
+#include <linux/bitfield.h>
+
+#include "otx2_common.h"
+#include "cn10k_ipsec.h"
+
+static bool is_dev_support_inline_ipsec(struct pci_dev *pdev)
+{
+ return is_dev_cn10ka_b0(pdev) || is_dev_cn10kb(pdev);
+}
+
+static int cn10k_outb_cptlf_attach(struct otx2_nic *pf)
+{
+ struct rsrc_attach *attach;
+ int err;
+
+ mutex_lock(&pf->mbox.lock);
+ /* Get memory to put this msg */
+ attach = otx2_mbox_alloc_msg_attach_resources(&pf->mbox);
+ if (!attach) {
+ mutex_unlock(&pf->mbox.lock);
+ return -ENOMEM;
+ }
+
+ attach->cptlfs = true;
+ attach->modify = true;
+
+ /* Send attach request to AF */
+ err = otx2_sync_mbox_msg(&pf->mbox);
+ if (err) {
+ mutex_unlock(&pf->mbox.lock);
+ return err;
+ }
+
+ mutex_unlock(&pf->mbox.lock);
+ return 0;
+}
+
+static int cn10k_outb_cptlf_detach(struct otx2_nic *pf)
+{
+ struct rsrc_detach *detach;
+
+ mutex_lock(&pf->mbox.lock);
+ detach = otx2_mbox_alloc_msg_detach_resources(&pf->mbox);
+ if (!detach) {
+ mutex_unlock(&pf->mbox.lock);
+ return -ENOMEM;
+ }
+
+ detach->partial = true;
+ detach->cptlfs = true;
+
+ /* Send detach request to AF */
+ otx2_sync_mbox_msg(&pf->mbox);
+ mutex_unlock(&pf->mbox.lock);
+ return 0;
+}
+
+static int cn10k_outb_cptlf_alloc(struct otx2_nic *pf)
+{
+ struct cpt_lf_alloc_req_msg *req;
+ int ret = 0;
+
+ mutex_lock(&pf->mbox.lock);
+ req = otx2_mbox_alloc_msg_cpt_lf_alloc(&pf->mbox);
+ if (!req) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ /* PF function */
+ req->nix_pf_func = pf->pcifunc;
+ /* Enable SE-IE Engine Group */
+ req->eng_grpmsk = 1 << CN10K_DEF_CPT_IPSEC_EGRP;
+
+ ret = otx2_sync_mbox_msg(&pf->mbox);
+
+error:
+ mutex_unlock(&pf->mbox.lock);
+ return ret;
+}
+
+static void cn10k_outb_cptlf_free(struct otx2_nic *pf)
+{
+ mutex_lock(&pf->mbox.lock);
+ otx2_mbox_alloc_msg_cpt_lf_free(&pf->mbox);
+ otx2_sync_mbox_msg(&pf->mbox);
+ mutex_unlock(&pf->mbox.lock);
+}
+
+static int cn10k_outb_cptlf_config(struct otx2_nic *pf)
+{
+ struct cpt_inline_ipsec_cfg_msg *req;
+ int ret = 0;
+
+ mutex_lock(&pf->mbox.lock);
+ req = otx2_mbox_alloc_msg_cpt_inline_ipsec_cfg(&pf->mbox);
+ if (!req) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ req->dir = CPT_INLINE_OUTBOUND;
+ req->enable = 1;
+ req->nix_pf_func = pf->pcifunc;
+ ret = otx2_sync_mbox_msg(&pf->mbox);
+error:
+ mutex_unlock(&pf->mbox.lock);
+ return ret;
+}
+
+static void cn10k_outb_cptlf_iq_enable(struct otx2_nic *pf)
+{
+ u64 reg_val;
+
+ /* Set Execution Enable of instruction queue */
+ reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);
+ reg_val |= BIT_ULL(16);
+ otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val);
+
+ /* Set iqueue's enqueuing */
+ reg_val = otx2_read64(pf, CN10K_CPT_LF_CTL);
+ reg_val |= BIT_ULL(0);
+ otx2_write64(pf, CN10K_CPT_LF_CTL, reg_val);
+}
+
+static void cn10k_outb_cptlf_iq_disable(struct otx2_nic *pf)
+{
+ u32 inflight, grb_cnt, gwb_cnt;
+ u32 nq_ptr, dq_ptr;
+ int timeout = 20;
+ u64 reg_val;
+ int cnt;
+
+ /* Disable instructions enqueuing */
+ otx2_write64(pf, CN10K_CPT_LF_CTL, 0ull);
+
+ /* Wait for instruction queue to become empty.
+ * CPT_LF_INPROG.INFLIGHT count is zero
+ */
+ do {
+ reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);
+ inflight = FIELD_GET(CPT_LF_INPROG_INFLIGHT, reg_val);
+ if (!inflight)
+ break;
+
+ usleep_range(10000, 20000);
+ if (timeout-- < 0) {
+ dev_err(pf->dev, "Error CPT LF is still busy\n");
+ break;
+ }
+ } while (1);
+
+ /* Disable executions in the LF's queue,
+ * the queue should be empty at this point
+ */
+ reg_val &= ~BIT_ULL(16);
+ otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val);
+
+ /* Wait for instruction queue to become empty */
+ cnt = 0;
+ do {
+ reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);
+ if (reg_val & BIT_ULL(31))
+ cnt = 0;
+ else
+ cnt++;
+ reg_val = otx2_read64(pf, CN10K_CPT_LF_Q_GRP_PTR);
+ nq_ptr = FIELD_GET(CPT_LF_Q_GRP_PTR_DQ_PTR, reg_val);
+ dq_ptr = FIELD_GET(CPT_LF_Q_GRP_PTR_DQ_PTR, reg_val);
+ } while ((cnt < 10) && (nq_ptr != dq_ptr));
+
+ cnt = 0;
+ do {
+ reg_val = otx2_read64(pf, CN10K_CPT_LF_INPROG);
+ inflight = FIELD_GET(CPT_LF_INPROG_INFLIGHT, reg_val);
+ grb_cnt = FIELD_GET(CPT_LF_INPROG_GRB_CNT, reg_val);
+ gwb_cnt = FIELD_GET(CPT_LF_INPROG_GWB_CNT, reg_val);
+ if (inflight == 0 && gwb_cnt < 40 &&
+ (grb_cnt == 0 || grb_cnt == 40))
+ cnt++;
+ else
+ cnt = 0;
+ } while (cnt < 10);
+}
+
+/* Allocate memory for CPT outbound Instruction queue.
+ * Instruction queue memory format is:
+ * -----------------------------
+ * | Instruction Group memory |
+ * | (CPT_LF_Q_SIZE[SIZE_DIV40] |
+ * | x 16 Bytes) |
+ * | |
+ * ----------------------------- <-- CPT_LF_Q_BASE[ADDR]
+ * | Flow Control (128 Bytes) |
+ * | |
+ * -----------------------------
+ * | Instruction Memory |
+ * | (CPT_LF_Q_SIZE[SIZE_DIV40] |
+ * | × 40 × 64 bytes) |
+ * | |
+ * -----------------------------
+ */
+static int cn10k_outb_cptlf_iq_alloc(struct otx2_nic *pf)
+{
+ struct cn10k_cpt_inst_queue *iq = &pf->ipsec.iq;
+
+ iq->size = CN10K_CPT_INST_QLEN_BYTES + CN10K_CPT_Q_FC_LEN +
+ CN10K_CPT_INST_GRP_QLEN_BYTES + OTX2_ALIGN;
+
+ iq->real_vaddr = dma_alloc_coherent(pf->dev, iq->size,
+ &iq->real_dma_addr, GFP_KERNEL);
+ if (!iq->real_vaddr)
+ return -ENOMEM;
+
+ /* iq->vaddr/dma_addr points to Flow Control location */
+ iq->vaddr = iq->real_vaddr + CN10K_CPT_INST_GRP_QLEN_BYTES;
+ iq->dma_addr = iq->real_dma_addr + CN10K_CPT_INST_GRP_QLEN_BYTES;
+
+ /* Align pointers */
+ iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_ALIGN);
+ iq->dma_addr = PTR_ALIGN(iq->dma_addr, OTX2_ALIGN);
+ return 0;
+}
+
+static void cn10k_outb_cptlf_iq_free(struct otx2_nic *pf)
+{
+ struct cn10k_cpt_inst_queue *iq = &pf->ipsec.iq;
+
+ if (!iq->real_vaddr)
+ dma_free_coherent(pf->dev, iq->size, iq->real_vaddr,
+ iq->real_dma_addr);
+
+ iq->real_vaddr = NULL;
+ iq->vaddr = NULL;
+}
+
+static int cn10k_outb_cptlf_iq_init(struct otx2_nic *pf)
+{
+ u64 reg_val;
+ int ret;
+
+ /* Allocate Memory for CPT IQ */
+ ret = cn10k_outb_cptlf_iq_alloc(pf);
+ if (ret)
+ return ret;
+
+ /* Disable IQ */
+ cn10k_outb_cptlf_iq_disable(pf);
+
+ /* Set IQ base address */
+ otx2_write64(pf, CN10K_CPT_LF_Q_BASE, pf->ipsec.iq.dma_addr);
+
+ /* Set IQ size */
+ reg_val = FIELD_PREP(CPT_LF_Q_SIZE_DIV40, CN10K_CPT_SIZE_DIV40 +
+ CN10K_CPT_EXTRA_SIZE_DIV40);
+ otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, reg_val);
+
+ return 0;
+}
+
+static int cn10k_outb_cptlf_init(struct otx2_nic *pf)
+{
+ int ret = 0;
+
+ /* Initialize CPTLF Instruction Queue (IQ) */
+ ret = cn10k_outb_cptlf_iq_init(pf);
+ if (ret)
+ return ret;
+
+ /* Configure CPTLF for outbound inline ipsec */
+ ret = cn10k_outb_cptlf_config(pf);
+ if (ret)
+ goto iq_clean;
+
+ /* Enable CPTLF IQ */
+ cn10k_outb_cptlf_iq_enable(pf);
+ return 0;
+iq_clean:
+ cn10k_outb_cptlf_iq_free(pf);
+ return ret;
+}
+
+static int cn10k_outb_cpt_init(struct net_device *netdev)
+{
+ struct otx2_nic *pf = netdev_priv(netdev);
+ int ret;
+
+ mutex_lock(&pf->ipsec.lock);
+
+ /* Attach a CPT LF for outbound inline ipsec */
+ ret = cn10k_outb_cptlf_attach(pf);
+ if (ret)
+ goto unlock;
+
+ /* Allocate a CPT LF for outbound inline ipsec */
+ ret = cn10k_outb_cptlf_alloc(pf);
+ if (ret)
+ goto detach;
+
+ /* Initialize the CPTLF for outbound inline ipsec */
+ ret = cn10k_outb_cptlf_init(pf);
+ if (ret)
+ goto lf_free;
+
+ pf->ipsec.io_addr = (__force u64)otx2_get_regaddr(pf,
+ CN10K_CPT_LF_NQX(0));
+
+ /* Set inline ipsec enabled for this device */
+ pf->flags |= OTX2_FLAG_INLINE_IPSEC_ENABLED;
+
+ goto unlock;
+
+lf_free:
+ cn10k_outb_cptlf_free(pf);
+detach:
+ cn10k_outb_cptlf_detach(pf);
+unlock:
+ mutex_unlock(&pf->ipsec.lock);
+ return ret;
+}
+
+static int cn10k_outb_cpt_clean(struct otx2_nic *pf)
+{
+ int err;
+
+ mutex_lock(&pf->ipsec.lock);
+
+ /* Set inline ipsec disabled for this device */
+ pf->flags &= ~OTX2_FLAG_INLINE_IPSEC_ENABLED;
+
+ /* Disable CPTLF Instruction Queue (IQ) */
+ cn10k_outb_cptlf_iq_disable(pf);
+
+ /* Set IQ base address and size to 0 */
+ otx2_write64(pf, CN10K_CPT_LF_Q_BASE, 0);
+ otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, 0);
+
+ /* Free CPTLF IQ */
+ cn10k_outb_cptlf_iq_free(pf);
+
+ /* Free and detach CPT LF */
+ cn10k_outb_cptlf_free(pf);
+ err = cn10k_outb_cptlf_detach(pf);
+ if (err)
+ netdev_err(pf->netdev, "Failed to detach CPT LF\n");
+
+ mutex_unlock(&pf->ipsec.lock);
+ return err;
+}
+
+int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable)
+{
+ struct otx2_nic *pf = netdev_priv(netdev);
+
+ /* Inline ipsec supported on cn10k */
+ if (!is_dev_support_inline_ipsec(pf->pdev))
+ return -ENODEV;
+
+ if (!enable)
+ return cn10k_outb_cpt_clean(pf);
+
+ /* Initialize CPT for outbound inline ipsec */
+ return cn10k_outb_cpt_init(netdev);
+}
+
+int cn10k_ipsec_init(struct net_device *netdev)
+{
+ struct otx2_nic *pf = netdev_priv(netdev);
+
+ if (!is_dev_support_inline_ipsec(pf->pdev))
+ return 0;
+
+ mutex_init(&pf->ipsec.lock);
+ return 0;
+}
+EXPORT_SYMBOL(cn10k_ipsec_init);
+
+void cn10k_ipsec_clean(struct otx2_nic *pf)
+{
+ if (!is_dev_support_inline_ipsec(pf->pdev))
+ return;
+
+ cn10k_outb_cpt_clean(pf);
+}
+EXPORT_SYMBOL(cn10k_ipsec_clean);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
new file mode 100644
index 000000000000..679583c3a18a
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell IPSEC offload driver
+ *
+ * Copyright (C) 2024 Marvell.
+ */
+
+#ifndef CN10K_IPSEC_H
+#define CN10K_IPSEC_H
+
+#include <linux/types.h>
+
+/* CPT instruction size in bytes */
+#define CN10K_CPT_INST_SIZE 64
+
+/* CPT instruction (CPT_INST_S) queue length */
+#define CN10K_CPT_INST_QLEN 8200
+
+/* CPT instruction queue size passed to HW is in units of
+ * 40*CPT_INST_S messages.
+ */
+#define CN10K_CPT_SIZE_DIV40 (CN10K_CPT_INST_QLEN / 40)
+
+/* CPT needs 320 free entries */
+#define CN10K_CPT_INST_QLEN_EXTRA_BYTES (320 * CN10K_CPT_INST_SIZE)
+#define CN10K_CPT_EXTRA_SIZE_DIV40 (320 / 40)
+
+/* CPT instruction queue length in bytes */
+#define CN10K_CPT_INST_QLEN_BYTES \
+ ((CN10K_CPT_SIZE_DIV40 * 40 * CN10K_CPT_INST_SIZE) + \
+ CN10K_CPT_INST_QLEN_EXTRA_BYTES)
+
+/* CPT instruction group queue length in bytes */
+#define CN10K_CPT_INST_GRP_QLEN_BYTES \
+ ((CN10K_CPT_SIZE_DIV40 + CN10K_CPT_EXTRA_SIZE_DIV40) * 16)
+
+/* CPT FC length in bytes */
+#define CN10K_CPT_Q_FC_LEN 128
+
+/* Default CPT engine group for inline ipsec */
+#define CN10K_DEF_CPT_IPSEC_EGRP 1
+
+/* CN10K CPT LF registers */
+#define CPT_LFBASE (BLKTYPE_CPT << RVU_FUNC_BLKADDR_SHIFT)
+#define CN10K_CPT_LF_CTL (CPT_LFBASE | 0x10)
+#define CN10K_CPT_LF_INPROG (CPT_LFBASE | 0x40)
+#define CN10K_CPT_LF_Q_BASE (CPT_LFBASE | 0xf0)
+#define CN10K_CPT_LF_Q_SIZE (CPT_LFBASE | 0x100)
+#define CN10K_CPT_LF_Q_INST_PTR (CPT_LFBASE | 0x110)
+#define CN10K_CPT_LF_Q_GRP_PTR (CPT_LFBASE | 0x120)
+#define CN10K_CPT_LF_NQX(a) (CPT_LFBASE | 0x400 | (a) << 3)
+#define CN10K_CPT_LF_CTX_FLUSH (CPT_LFBASE | 0x510)
+
+struct cn10k_cpt_inst_queue {
+ u8 *vaddr;
+ u8 *real_vaddr;
+ dma_addr_t dma_addr;
+ dma_addr_t real_dma_addr;
+ u32 size;
+};
+
+struct cn10k_ipsec {
+ /* Outbound CPT */
+ u64 io_addr;
+ /* Lock to protect SA management */
+ struct mutex lock;
+ struct cn10k_cpt_inst_queue iq;
+};
+
+/* CPT LF_INPROG Register */
+#define CPT_LF_INPROG_INFLIGHT GENMASK_ULL(8, 0)
+#define CPT_LF_INPROG_GRB_CNT GENMASK_ULL(39, 32)
+#define CPT_LF_INPROG_GWB_CNT GENMASK_ULL(47, 40)
+
+/* CPT LF_Q_GRP_PTR Register */
+#define CPT_LF_Q_GRP_PTR_DQ_PTR GENMASK_ULL(14, 0)
+#define CPT_LF_Q_GRP_PTR_NQ_PTR GENMASK_ULL(46, 32)
+
+/* CPT LF_Q_SIZE Register */
+#define CPT_LF_Q_BASE_ADDR GENMASK_ULL(52, 7)
+
+/* CPT LF_Q_SIZE Register */
+#define CPT_LF_Q_SIZE_DIV40 GENMASK_ULL(14, 0)
+
+#ifdef CONFIG_XFRM_OFFLOAD
+int cn10k_ipsec_init(struct net_device *netdev);
+void cn10k_ipsec_clean(struct otx2_nic *pf);
+int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable);
+#else
+static __maybe_unused inline int cn10k_ipsec_init(struct net_device *netdev)
+{
+ return 0;
+}
+
+static __maybe_unused inline void cn10k_ipsec_clean(struct otx2_nic *pf)
+{
+}
+
+static __maybe_unused inline
+int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable)
+{
+ return 0;
+}
+#endif
+#endif // CN10K_IPSEC_H
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
index 42a759a33c11..859bbc78e653 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
@@ -29,6 +29,7 @@
#include "otx2_devlink.h"
#include <rvu_trace.h>
#include "qos.h"
+#include "cn10k_ipsec.h"
/* IPv4 flag more fragment bit */
#define IPV4_FLAG_MORE 0x20
@@ -39,6 +40,7 @@
#define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
#define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
+#define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF 0xB900
#define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00
/* PCI BAR nos */
@@ -467,6 +469,7 @@ struct otx2_nic {
#define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15)
#define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16)
#define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17)
+#define OTX2_FLAG_INLINE_IPSEC_ENABLED BIT_ULL(18)
u64 flags;
u64 *cq_op_addr;
@@ -534,6 +537,9 @@ struct otx2_nic {
#if IS_ENABLED(CONFIG_MACSEC)
struct cn10k_mcs_cfg *macsec_cfg;
#endif
+
+ /* Inline ipsec */
+ struct cn10k_ipsec ipsec;
};
static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
@@ -578,6 +584,15 @@ static inline bool is_dev_cn10kb(struct pci_dev *pdev)
return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF;
}
+static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)
+{
+ if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF &&
+ (pdev->revision & 0xFF) == 0x54)
+ return true;
+
+ return false;
+}
+
static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
{
struct otx2_hw *hw = &pfvf->hw;
@@ -627,6 +642,9 @@ static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
case BLKTYPE_NPA:
blkaddr = BLKADDR_NPA;
break;
+ case BLKTYPE_CPT:
+ blkaddr = BLKADDR_CPT0;
+ break;
default:
blkaddr = BLKADDR_RVUM;
break;
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
index cbd5050f58e8..a7e17d870420 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
@@ -26,6 +26,7 @@
#include "cn10k.h"
#include "qos.h"
#include <rvu_trace.h>
+#include "cn10k_ipsec.h"
#define DRV_NAME "rvu_nicpf"
#define DRV_STRING "Marvell RVU NIC Physical Function Driver"
@@ -2201,6 +2202,10 @@ static int otx2_set_features(struct net_device *netdev,
return otx2_enable_rxvlan(pf,
features & NETIF_F_HW_VLAN_CTAG_RX);
+ if (changed & NETIF_F_HW_ESP)
+ return cn10k_ipsec_ethtool_init(netdev,
+ features & NETIF_F_HW_ESP);
+
return otx2_handle_ntuple_tc_features(netdev, features);
}
@@ -3065,10 +3070,14 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
/* reset CGX/RPM MAC stats */
otx2_reset_mac_stats(pf);
+ err = cn10k_ipsec_init(netdev);
+ if (err)
+ goto err_mcs_free;
+
err = register_netdev(netdev);
if (err) {
dev_err(dev, "Failed to register netdevice\n");
- goto err_mcs_free;
+ goto err_ipsec_clean;
}
err = otx2_wq_init(pf);
@@ -3109,6 +3118,8 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
otx2_mcam_flow_del(pf);
err_unreg_netdev:
unregister_netdev(netdev);
+err_ipsec_clean:
+ cn10k_ipsec_clean(pf);
err_mcs_free:
cn10k_mcs_free(pf);
err_del_mcam_entries:
@@ -3286,6 +3297,7 @@ static void otx2_remove(struct pci_dev *pdev)
otx2_unregister_dl(pf);
unregister_netdev(netdev);
+ cn10k_ipsec_clean(pf);
cn10k_mcs_free(pf);
otx2_sriov_disable(pf->pdev);
otx2_sriov_vfcfg_cleanup(pf);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
index 99fcc5661674..6fc70c3cafb6 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
@@ -14,6 +14,7 @@
#include "otx2_reg.h"
#include "otx2_ptp.h"
#include "cn10k.h"
+#include "cn10k_ipsec.h"
#define DRV_NAME "rvu_nicvf"
#define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
@@ -682,10 +683,14 @@ static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n);
}
+ err = cn10k_ipsec_init(netdev);
+ if (err)
+ goto err_ptp_destroy;
+
err = register_netdev(netdev);
if (err) {
dev_err(dev, "Failed to register netdevice\n");
- goto err_ptp_destroy;
+ goto err_ipsec_clean;
}
err = otx2_wq_init(vf);
@@ -719,6 +724,8 @@ static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
otx2_shutdown_tc(vf);
err_unreg_netdev:
unregister_netdev(netdev);
+err_ipsec_clean:
+ cn10k_ipsec_clean(vf);
err_ptp_destroy:
otx2_ptp_destroy(vf);
err_detach_rsrc:
@@ -771,6 +778,7 @@ static void otx2vf_remove(struct pci_dev *pdev)
unregister_netdev(netdev);
if (vf->otx2_wq)
destroy_workqueue(vf->otx2_wq);
+ cn10k_ipsec_clean(vf);
otx2_ptp_destroy(vf);
otx2_mcam_flow_del(vf);
otx2_shutdown_tc(vf);
--
2.34.1
Prepare and submit crypto hardware (CPT) instruction for
outbound inline ipsec crypto mode offload. The CPT instruction
have authentication offset, IV offset and encapsulation offset
in input packet. Also provide SA context pointer which have
details about algo, keys, salt etc. Crypto hardware encrypt,
authenticate and provide the ESP packet to networking hardware.
Signed-off-by: Bharat Bhushan <[email protected]>
---
v1->v2:
- Use dma_wmb() instead of architecture specific barrier
- Fix couple of other compilation warnings
.../marvell/octeontx2/nic/cn10k_ipsec.c | 224 ++++++++++++++++++
.../marvell/octeontx2/nic/cn10k_ipsec.h | 40 ++++
.../marvell/octeontx2/nic/otx2_common.c | 23 ++
.../marvell/octeontx2/nic/otx2_common.h | 3 +
.../ethernet/marvell/octeontx2/nic/otx2_pf.c | 2 +
.../marvell/octeontx2/nic/otx2_txrx.c | 33 ++-
.../marvell/octeontx2/nic/otx2_txrx.h | 3 +
7 files changed, 325 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
index 4262458342c1..91c83a2ba6b1 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
@@ -7,8 +7,11 @@
#include <net/xfrm.h>
#include <linux/netdevice.h>
#include <linux/bitfield.h>
+#include <crypto/aead.h>
+#include <crypto/gcm.h>
#include "otx2_common.h"
+#include "otx2_struct.h"
#include "cn10k_ipsec.h"
static bool is_dev_support_inline_ipsec(struct pci_dev *pdev)
@@ -822,3 +825,224 @@ void cn10k_ipsec_clean(struct otx2_nic *pf)
cn10k_outb_cpt_clean(pf);
}
EXPORT_SYMBOL(cn10k_ipsec_clean);
+
+static u16 cn10k_ipsec_get_ip_data_len(struct xfrm_state *x,
+ struct sk_buff *skb)
+{
+ struct ipv6hdr *ipv6h;
+ struct iphdr *iph;
+ u8 *src;
+
+ src = (u8 *)skb->data + ETH_HLEN;
+
+ if (x->props.family == AF_INET) {
+ iph = (struct iphdr *)src;
+ return ntohs(iph->tot_len);
+ }
+
+ ipv6h = (struct ipv6hdr *)src;
+ return ntohs(ipv6h->payload_len) + sizeof(struct ipv6hdr);
+}
+
+/* Prepare CPT and NIX SQE scatter/gather subdescriptor structure.
+ * SG of NIX and CPT are same in size.
+ * Layout of a NIX SQE and CPT SG entry:
+ * -----------------------------
+ * | CPT Scatter Gather |
+ * | (SQE SIZE) |
+ * | |
+ * -----------------------------
+ * | NIX SQE |
+ * | (SQE SIZE) |
+ * | |
+ * -----------------------------
+ */
+bool otx2_sqe_add_sg_ipsec(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
+ struct sk_buff *skb, int num_segs, int *offset)
+{
+ struct cpt_sg_s *cpt_sg = NULL;
+ struct nix_sqe_sg_s *sg = NULL;
+ u64 dma_addr, *iova = NULL;
+ u64 *cpt_iova = NULL;
+ u16 *sg_lens = NULL;
+ int seg, len;
+
+ sq->sg[sq->head].num_segs = 0;
+ cpt_sg = (struct cpt_sg_s *)(sq->sqe_base - sq->sqe_size);
+
+ for (seg = 0; seg < num_segs; seg++) {
+ if ((seg % MAX_SEGS_PER_SG) == 0) {
+ sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
+ sg->ld_type = NIX_SEND_LDTYPE_LDD;
+ sg->subdc = NIX_SUBDC_SG;
+ sg->segs = 0;
+ sg_lens = (void *)sg;
+ iova = (void *)sg + sizeof(*sg);
+ /* Next subdc always starts at a 16byte boundary.
+ * So if sg->segs is whether 2 or 3, offset += 16bytes.
+ */
+ if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
+ *offset += sizeof(*sg) + (3 * sizeof(u64));
+ else
+ *offset += sizeof(*sg) + sizeof(u64);
+
+ cpt_sg += (seg / MAX_SEGS_PER_SG) * 4;
+ cpt_iova = (void *)cpt_sg + sizeof(*cpt_sg);
+ }
+ dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
+ if (dma_mapping_error(pfvf->dev, dma_addr))
+ return false;
+
+ sg_lens[seg % MAX_SEGS_PER_SG] = len;
+ sg->segs++;
+ *iova++ = dma_addr;
+ *cpt_iova++ = dma_addr;
+
+ /* Save DMA mapping info for later unmapping */
+ sq->sg[sq->head].dma_addr[seg] = dma_addr;
+ sq->sg[sq->head].size[seg] = len;
+ sq->sg[sq->head].num_segs++;
+
+ *cpt_sg = *(struct cpt_sg_s *)sg;
+ cpt_sg->rsvd_63_50 = 0;
+ }
+
+ sq->sg[sq->head].skb = (u64)skb;
+ return true;
+}
+
+static u16 cn10k_ipsec_get_param1(u8 iv_offset)
+{
+ u16 param1_val;
+
+ /* Set Crypto mode, disable L3/L4 checksum */
+ param1_val = CN10K_IPSEC_INST_PARAM1_CRYPTO_MODE |
+ CN10K_IPSEC_INST_PARAM1_DIS_L4_CSUM |
+ CN10K_IPSEC_INST_PARAM1_DIS_L3_CSUM;
+ param1_val |= (u16)iv_offset << CN10K_IPSEC_INST_PARAM1_IV_OFFSET_SHIFT;
+ return param1_val;
+}
+
+bool cn10k_ipsec_transmit(struct otx2_nic *pf, struct netdev_queue *txq,
+ struct otx2_snd_queue *sq, struct sk_buff *skb,
+ int num_segs, int size)
+{
+ struct cpt_ctx_info_s *sa_info;
+ struct cpt_inst_s inst;
+ struct cpt_res_s *res;
+ struct xfrm_state *x;
+ dma_addr_t dptr_iova;
+ struct sec_path *sp;
+ u8 encap_offset;
+ u8 auth_offset;
+ u8 gthr_size;
+ u8 iv_offset;
+ u16 dlen;
+
+ /* Check for Inline IPSEC enabled */
+ if (!(pf->flags & OTX2_FLAG_INLINE_IPSEC_ENABLED)) {
+ netdev_err(pf->netdev, "Ipsec not enabled, drop packet\n");
+ goto drop;
+ }
+
+ sp = skb_sec_path(skb);
+ if (unlikely(!sp->len)) {
+ netdev_err(pf->netdev, "%s: no xfrm state len = %d\n",
+ __func__, sp->len);
+ goto drop;
+ }
+
+ x = xfrm_input_state(skb);
+ if (unlikely(!x)) {
+ netdev_err(pf->netdev, "no xfrm_input_state()\n");
+ goto drop;
+ }
+
+ if (x->props.mode != XFRM_MODE_TRANSPORT &&
+ x->props.mode != XFRM_MODE_TUNNEL) {
+ netdev_err(pf->netdev, "un supported offload mode %d\n",
+ x->props.mode);
+ goto drop;
+ }
+
+ dlen = cn10k_ipsec_get_ip_data_len(x, skb);
+ if (dlen == 0) {
+ netdev_err(pf->netdev, "Invalid IP header, ip-length zero\n");
+ goto drop;
+ }
+
+ /* Check for valid SA context */
+ sa_info = (struct cpt_ctx_info_s *)x->xso.offload_handle;
+ if (!sa_info || !sa_info->sa_iova) {
+ netdev_err(pf->netdev, "Invalid SA conext\n");
+ goto drop;
+ }
+
+ memset(&inst, 0, sizeof(struct cpt_inst_s));
+
+ /* Get authentication offset */
+ if (x->props.family == AF_INET)
+ auth_offset = sizeof(struct iphdr);
+ else
+ auth_offset = sizeof(struct ipv6hdr);
+
+ /* IV offset is after ESP header */
+ iv_offset = auth_offset + sizeof(struct ip_esp_hdr);
+ /* Encap will start after IV */
+ encap_offset = iv_offset + GCM_RFC4106_IV_SIZE;
+
+ /* CPT Instruction word-1 */
+ res = (struct cpt_res_s *)(sq->cpt_resp->base + (64 * sq->head));
+ res->compcode = 0;
+ inst.res_addr = sq->cpt_resp->iova + (64 * sq->head);
+
+ /* CPT Instruction word-2 */
+ inst.rvu_pf_func = pf->pcifunc;
+
+ /* CPT Instruction word-3:
+ * Set QORD to force CPT_RES_S write completion
+ */
+ inst.qord = 1;
+
+ /* CPT Instruction word-4 */
+ inst.dlen = dlen + ETH_HLEN;
+ inst.opcode_major = CN10K_IPSEC_MAJOR_OP_OUTB_IPSEC;
+ inst.param1 = cn10k_ipsec_get_param1(iv_offset);
+
+ inst.param2 = encap_offset <<
+ CN10K_IPSEC_INST_PARAM2_ENC_DATA_OFFSET_SHIFT;
+ inst.param2 |= (u16)auth_offset <<
+ CN10K_IPSEC_INST_PARAM2_AUTH_DATA_OFFSET_SHIFT;
+
+ /* CPT Instruction word-5 */
+ gthr_size = num_segs / MAX_SEGS_PER_SG;
+ gthr_size = (num_segs % MAX_SEGS_PER_SG) ? gthr_size + 1 : gthr_size;
+
+ gthr_size &= 0xF;
+ dptr_iova = (sq->sqe_ring->iova + (sq->head * (sq->sqe_size * 2)));
+ inst.dptr = dptr_iova | ((u64)gthr_size << 60);
+
+ /* CPT Instruction word-6 */
+ inst.rptr = inst.dptr;
+
+ /* CPT Instruction word-7 */
+ inst.cptr = sa_info->sa_iova;
+ inst.ctx_val = 1;
+ inst.egrp = CN10K_DEF_CPT_IPSEC_EGRP;
+
+ /* CPT Instruction word-0 */
+ inst.nixtxl = (size / 16) - 1;
+ inst.dat_offset = ETH_HLEN;
+ inst.nixtx_offset = sq->sqe_size;
+
+ netdev_tx_sent_queue(txq, skb->len);
+
+ /* Finally Flush the CPT instruction */
+ sq->head++;
+ sq->head &= (sq->sqe_cnt - 1);
+ cn10k_cpt_inst_flush(pf, &inst, sizeof(struct cpt_inst_s));
+ return true;
+drop:
+ dev_kfree_skb_any(skb);
+ return false;
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
index d4fab47b7845..262486c91a70 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
@@ -56,6 +56,7 @@
/* IPSEC Instruction opcodes */
#define CN10K_IPSEC_MAJOR_OP_WRITE_SA 0x01UL
#define CN10K_IPSEC_MINOR_OP_WRITE_SA 0x09UL
+#define CN10K_IPSEC_MAJOR_OP_OUTB_IPSEC 0x28UL
enum cn10k_cpt_comp_e {
CN10K_CPT_COMP_E_NOTDONE = 0x00,
@@ -133,6 +134,16 @@ struct cn10k_tx_sa_s {
u64 hw_ctx[6]; /* W31 - W36 */
};
+/* CPT instruction parameter-1 */
+#define CN10K_IPSEC_INST_PARAM1_DIS_L4_CSUM 0x1
+#define CN10K_IPSEC_INST_PARAM1_DIS_L3_CSUM 0x2
+#define CN10K_IPSEC_INST_PARAM1_CRYPTO_MODE 0x20
+#define CN10K_IPSEC_INST_PARAM1_IV_OFFSET_SHIFT 8
+
+/* CPT instruction parameter-2 */
+#define CN10K_IPSEC_INST_PARAM2_ENC_DATA_OFFSET_SHIFT 0
+#define CN10K_IPSEC_INST_PARAM2_AUTH_DATA_OFFSET_SHIFT 8
+
/* CPT Instruction Structure */
struct cpt_inst_s {
u64 nixtxl : 3; /* W0 */
@@ -177,6 +188,15 @@ struct cpt_ctx_info_s {
dma_addr_t sa_iova;
};
+/* CPT SG structure */
+struct cpt_sg_s {
+ u64 seg1_size : 16;
+ u64 seg2_size : 16;
+ u64 seg3_size : 16;
+ u64 segs : 2;
+ u64 rsvd_63_50 : 14;
+};
+
/* CPT LF_INPROG Register */
#define CPT_LF_INPROG_INFLIGHT GENMASK_ULL(8, 0)
#define CPT_LF_INPROG_GRB_CNT GENMASK_ULL(39, 32)
@@ -199,6 +219,11 @@ struct cpt_ctx_info_s {
int cn10k_ipsec_init(struct net_device *netdev);
void cn10k_ipsec_clean(struct otx2_nic *pf);
int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable);
+bool otx2_sqe_add_sg_ipsec(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
+ struct sk_buff *skb, int num_segs, int *offset);
+bool cn10k_ipsec_transmit(struct otx2_nic *pf, struct netdev_queue *txq,
+ struct otx2_snd_queue *sq, struct sk_buff *skb,
+ int num_segs, int size);
#else
static __maybe_unused inline int cn10k_ipsec_init(struct net_device *netdev)
{
@@ -214,5 +239,20 @@ int cn10k_ipsec_ethtool_init(struct net_device *netdev, bool enable)
{
return 0;
}
+
+static __maybe_unused
+bool otx2_sqe_add_sg_ipsec(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
+ struct sk_buff *skb, int num_segs, int *offset)
+{
+ return true;
+}
+
+static __maybe_unused
+bool cn10k_ipsec_transmit(struct otx2_nic *pf, struct netdev_queue *txq,
+ struct otx2_snd_queue *sq, struct sk_buff *skb,
+ int num_segs, int size)
+{
+ return true;
+}
#endif
#endif // CN10K_IPSEC_H
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
index e9d2e039a322..eaa318012162 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
@@ -936,6 +936,29 @@ int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
if (err)
return err;
+ /* Allocate memory for NIX SQE (which includes NIX SG) and CPT SG.
+ * SG of NIX and CPT are same in size. Allocate memory for CPT SG
+ * same as NIX SQE for base address alignment.
+ * Layout of a NIX SQE and CPT SG entry:
+ * -----------------------------
+ * | CPT Scatter Gather |
+ * | (SQE SIZE) |
+ * | |
+ * -----------------------------
+ * | NIX SQE |
+ * | (SQE SIZE) |
+ * | |
+ * -----------------------------
+ */
+ err = qmem_alloc(pfvf->dev, &sq->sqe_ring, qset->sqe_cnt,
+ sq->sqe_size * 2);
+ if (err)
+ return err;
+
+ err = qmem_alloc(pfvf->dev, &sq->cpt_resp, qset->sqe_cnt, 64);
+ if (err)
+ return err;
+
if (qidx < pfvf->hw.tx_queues) {
err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
TSO_HEADER_SIZE);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
index 859bbc78e653..9471ee572625 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
@@ -54,6 +54,9 @@
#define NIX_PF_PFC_PRIO_MAX 8
#endif
+/* Number of segments per SG structure */
+#define MAX_SEGS_PER_SG 3
+
enum arua_mapped_qtypes {
AURA_NIX_RQ,
AURA_NIX_SQ,
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
index a7e17d870420..bc34074454b3 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
@@ -1444,6 +1444,8 @@ static void otx2_free_sq_res(struct otx2_nic *pf)
if (!sq->sqe)
continue;
qmem_free(pf->dev, sq->sqe);
+ qmem_free(pf->dev, sq->sqe_ring);
+ qmem_free(pf->dev, sq->cpt_resp);
qmem_free(pf->dev, sq->tso_hdrs);
kfree(sq->sg);
kfree(sq->sqb_ptrs);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
index f368eac28fdd..b0e1524ea4bd 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
@@ -11,6 +11,7 @@
#include <linux/bpf.h>
#include <linux/bpf_trace.h>
#include <net/ip6_checksum.h>
+#include <net/xfrm.h>
#include "otx2_reg.h"
#include "otx2_common.h"
@@ -32,6 +33,16 @@ static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
struct otx2_cq_queue *cq,
bool *need_xdp_flush);
+static void otx2_sq_set_sqe_base(struct otx2_snd_queue *sq,
+ struct sk_buff *skb)
+{
+ if (unlikely(xfrm_offload(skb)))
+ sq->sqe_base = sq->sqe_ring->base + sq->sqe_size +
+ (sq->head * (sq->sqe_size * 2));
+ else
+ sq->sqe_base = sq->sqe->base;
+}
+
static int otx2_nix_cq_op_status(struct otx2_nic *pfvf,
struct otx2_cq_queue *cq)
{
@@ -580,7 +591,6 @@ void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
sq->head &= (sq->sqe_cnt - 1);
}
-#define MAX_SEGS_PER_SG 3
/* Add SQE scatter/gather subdescriptor structure */
static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
struct sk_buff *skb, int num_segs, int *offset)
@@ -1116,6 +1126,11 @@ bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
struct otx2_nic *pfvf = netdev_priv(netdev);
int offset, num_segs, free_desc;
struct nix_sqe_hdr_s *sqe_hdr;
+ int ipsec = 0;
+ bool ret;
+
+ if (unlikely(xfrm_offload(skb)))
+ ipsec = 1;
/* Check if there is enough room between producer
* and consumer index.
@@ -1132,6 +1147,7 @@ bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
/* If SKB doesn't fit in a single SQE, linearize it.
* TODO: Consider adding JUMP descriptor instead.
*/
+
if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) {
if (__skb_linearize(skb)) {
dev_kfree_skb_any(skb);
@@ -1148,6 +1164,9 @@ bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
return true;
}
+ /* Set sqe base address */
+ otx2_sq_set_sqe_base(sq, skb);
+
/* Set SQE's SEND_HDR.
* Do not clear the first 64bit as it contains constant info.
*/
@@ -1160,7 +1179,12 @@ bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
otx2_sqe_add_ext(pfvf, sq, skb, &offset);
/* Add SG subdesc with data frags */
- if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) {
+ if (unlikely(ipsec))
+ ret = otx2_sqe_add_sg_ipsec(pfvf, sq, skb, num_segs, &offset);
+ else
+ ret = otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset);
+
+ if (!ret) {
otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]);
return false;
}
@@ -1169,11 +1193,14 @@ bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
sqe_hdr->sizem1 = (offset / 16) - 1;
+ if (unlikely(ipsec))
+ return cn10k_ipsec_transmit(pfvf, txq, sq, skb, num_segs,
+ offset);
+
netdev_tx_sent_queue(txq, skb->len);
/* Flush SQE to HW */
pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
-
return true;
}
EXPORT_SYMBOL(otx2_sq_append_skb);
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
index 3f1d2655ff77..248fd78ef0e9 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
@@ -101,6 +101,9 @@ struct otx2_snd_queue {
struct queue_stats stats;
u16 sqb_count;
u64 *sqb_ptrs;
+ /* SQE ring and CPT response queue for Inline IPSEC */
+ struct qmem *sqe_ring;
+ struct qmem *cpt_resp;
} ____cacheline_aligned_in_smp;
enum cq_type {
--
2.34.1
On Mon, May 13, 2024 at 4:25 PM Bharat Bhushan <[email protected]> wrote:
>
> This patch series adds outbound inline ipsec support on Marvell
> cn10k series of platform. One crypto hardware logical function
> (cpt-lf) per netdev is required for inline ipsec outbound
> functionality. Software prepare and submit crypto hardware
> (CPT) instruction for outbound inline ipsec crypto mode offload.
> The CPT instruction have details for encryption and authentication
> Crypto hardware encrypt, authenticate and provide the ESP packet
> to network hardware logic to transmit ipsec packet.
>
> First patch makes dma memory writable for in-place encryption,
> Second patch moves code to common file, Third patch disable
> backpressure on crypto (CPT) and network (NIX) hardware.
> Patch four onwards enables inline outbound ipsec.
>
> v1->v2:
> - Fix compilation error to build driver a module
> - Use dma_wmb() instead of architecture specific barrier
> - Fix couple of other compilation warnings
Comments on V1 is not addressed.
Also, please respect the 24h grace period when posting on netdev:
https://elixir.bootlin.com/linux/latest/source/Documentation/process/maintainer-netdev.rst#L399
>
> Bharat Bhushan (8):
> octeontx2-pf: map skb data as device writeable
> octeontx2-pf: Move skb fragment map/unmap to common code
> octeontx2-af: Disable backpressure between CPT and NIX
> cn10k-ipsec: Initialize crypto hardware for outb inline ipsec
> cn10k-ipsec: Add SA add/delete support for outb inline ipsec
> cn10k-ipsec: Process inline ipsec transmit offload
> cn10k-ipsec: Allow inline ipsec offload for skb with SA
> cn10k-ipsec: Enable outbound inline ipsec offload
>
> .../net/ethernet/marvell/octeontx2/af/mbox.h | 4 +
> .../ethernet/marvell/octeontx2/af/rvu_nix.c | 74 +-
> .../ethernet/marvell/octeontx2/nic/Makefile | 1 +
> .../marvell/octeontx2/nic/cn10k_ipsec.c | 1068 +++++++++++++++++
> .../marvell/octeontx2/nic/cn10k_ipsec.h | 258 ++++
> .../marvell/octeontx2/nic/otx2_common.c | 80 ++
> .../marvell/octeontx2/nic/otx2_common.h | 25 +
> .../marvell/octeontx2/nic/otx2_dcbnl.c | 3 +
> .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 19 +-
> .../marvell/octeontx2/nic/otx2_txrx.c | 65 +-
> .../marvell/octeontx2/nic/otx2_txrx.h | 3 +
> .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 10 +-
> 12 files changed, 1563 insertions(+), 47 deletions(-)
> create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
> create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
>
> --
> 2.34.1
>
>
--
Regards,
Kalesh A P
On Mon, May 13, 2024 at 04:24:41PM +0530, Bharat Bhushan wrote:
> NIX can assert backpressure to CPT on the NIX<=>CPT link.
> Keep the backpressure disabled for now. NIX block anyways
> handles backpressure asserted by MAC due to PFC or flow
> control pkts.
>
> Signed-off-by: Bharat Bhushan <[email protected]>
..
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
..
> @@ -592,8 +596,16 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
> bp = &nix_hw->bp;
> chan_base = pfvf->rx_chan_base + req->chan_base;
> for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
> - cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
> - rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
> + /* CPT channel for a given link channel is always
> + * assumed to be BIT(11) set in link channel.
> + */
> + if (cpt_link)
> + chan_v = chan | BIT(11);
> + else
> + chan_v = chan;
Hi Bharat,
The chan_v logic above seems to appear twice in this patch.
I'd suggest adding a helper.
> +
> + cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v));
> + rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
> cfg & ~BIT_ULL(16));
>
> if (type == NIX_INTF_TYPE_LBK) {
..
> diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> index 7ec99c8d610c..e9d2e039a322 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> @@ -1705,6 +1705,31 @@ int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
> }
> EXPORT_SYMBOL(otx2_nix_config_bp);
>
> +int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable)
> +{
> + struct nix_bp_cfg_req *req;
> +
> + if (enable)
> + req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf->mbox);
> + else
> + req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf->mbox);
> +
> + if (!req)
> + return -ENOMEM;
> +
> + req->chan_base = 0;
> +#ifdef CONFIG_DCB
> + req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
> + req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
> +#else
> + req->chan_cnt = 1;
> + req->bpid_per_chan = 0;
> +#endif
IMHO, inline #ifdefs reduce readability and reduce maintainability.
Would it be possible to either:
1. Include the pfc_en field in struct otx2_nic and make
sure it is set to 0 if CONFIG_DCB is unset; or
2. Provide a wrapper that returns 0 if CONFIG_DCB is unset,
otherwise pfvf->pfc_en.
I suspect 1 will have little downside and be easiest to implement.
> +
> + return otx2_sync_mbox_msg(&pfvf->mbox);
> +}
> +EXPORT_SYMBOL(otx2_nix_cpt_config_bp);
> +
> /* Mbox message handlers */
> void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
> struct cgx_stats_rsp *rsp)
..
Please see inline
> -----Original Message-----
> From: Simon Horman <[email protected]>
> Sent: Monday, May 13, 2024 9:45 PM
> To: Bharat Bhushan <[email protected]>
> Cc: [email protected]; [email protected]; Sunil Kovvuri
> Goutham <[email protected]>; Geethasowjanya Akula
> <[email protected]>; Subbaraya Sundeep Bhatta <[email protected]>;
> Hariprasad Kelam <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; Jerin Jacob
> <[email protected]>; Linu Cherian <[email protected]>;
> [email protected]
> Subject: [EXTERNAL] Re: [net-next,v2 3/8] octeontx2-af: Disable backpressure
> between CPT and NIX
>
>
> ----------------------------------------------------------------------
> On Mon, May 13, 2024 at 04:24:41PM +0530, Bharat Bhushan wrote:
> > NIX can assert backpressure to CPT on the NIX<=>CPT link.
> > Keep the backpressure disabled for now. NIX block anyways
> > handles backpressure asserted by MAC due to PFC or flow
> > control pkts.
> >
> > Signed-off-by: Bharat Bhushan <[email protected]>
>
> ...
>
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
>
> ...
>
> > @@ -592,8 +596,16 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu
> *rvu,
> > bp = &nix_hw->bp;
> > chan_base = pfvf->rx_chan_base + req->chan_base;
> > for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
> > - cfg = rvu_read64(rvu, blkaddr,
> NIX_AF_RX_CHANX_CFG(chan));
> > - rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
> > + /* CPT channel for a given link channel is always
> > + * assumed to be BIT(11) set in link channel.
> > + */
> > + if (cpt_link)
> > + chan_v = chan | BIT(11);
> > + else
> > + chan_v = chan;
>
> Hi Bharat,
>
> The chan_v logic above seems to appear twice in this patch.
> I'd suggest adding a helper.
Will fix in next version.
>
> > +
> > + cfg = rvu_read64(rvu, blkaddr,
> NIX_AF_RX_CHANX_CFG(chan_v));
> > + rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
> > cfg & ~BIT_ULL(16));
> >
> > if (type == NIX_INTF_TYPE_LBK) {
>
> ...
>
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > index 7ec99c8d610c..e9d2e039a322 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > @@ -1705,6 +1705,31 @@ int otx2_nix_config_bp(struct otx2_nic *pfvf,
> bool enable)
> > }
> > EXPORT_SYMBOL(otx2_nix_config_bp);
> >
> > +int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable)
> > +{
> > + struct nix_bp_cfg_req *req;
> > +
> > + if (enable)
> > + req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf-
> >mbox);
> > + else
> > + req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf-
> >mbox);
> > +
> > + if (!req)
> > + return -ENOMEM;
> > +
> > + req->chan_base = 0;
> > +#ifdef CONFIG_DCB
> > + req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
> > + req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
> > +#else
> > + req->chan_cnt = 1;
> > + req->bpid_per_chan = 0;
> > +#endif
>
> IMHO, inline #ifdefs reduce readability and reduce maintainability.
>
> Would it be possible to either:
>
> 1. Include the pfc_en field in struct otx2_nic and make
> sure it is set to 0 if CONFIG_DCB is unset; or
> 2. Provide a wrapper that returns 0 if CONFIG_DCB is unset,
> otherwise pfvf->pfc_en.
>
> I suspect 1 will have little downside and be easiest to implement.
pfc_en is already a field of otx2_nic but under CONFIG_DCB. Will fix by adding a wrapper function like:
static bool is_pfc_enabled(struct otx2_nic *pfvf)
{
#ifdef CONFIG_DCB
return pfvf->pfc_en ? true : false;
#endif
return false;
}
Using same like..
..
if (is_pfc_enabled(pfvf)) {
req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
req->bpid_per_chan = 1;
} else {
req->chan_cnt = 1;
req->bpid_per_chan = 0;
}
..
Thanks
-Bharat
>
> > +
> > + return otx2_sync_mbox_msg(&pfvf->mbox);
> > +}
> > +EXPORT_SYMBOL(otx2_nix_cpt_config_bp);
> > +
> > /* Mbox message handlers */
> > void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
> > struct cgx_stats_rsp *rsp)
>
> ...
On Tue, May 14, 2024 at 06:39:45AM +0000, Bharat Bhushan wrote:
> Please see inline
>
> > -----Original Message-----
> > From: Simon Horman <[email protected]>
> > Sent: Monday, May 13, 2024 9:45 PM
> > To: Bharat Bhushan <[email protected]>
> > Cc: [email protected]; [email protected]; Sunil Kovvuri
> > Goutham <[email protected]>; Geethasowjanya Akula
> > <[email protected]>; Subbaraya Sundeep Bhatta <[email protected]>;
> > Hariprasad Kelam <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected]; Jerin Jacob
> > <[email protected]>; Linu Cherian <[email protected]>;
> > [email protected]
> > Subject: [EXTERNAL] Re: [net-next,v2 3/8] octeontx2-af: Disable backpressure
> > between CPT and NIX
> >
> >
> > ----------------------------------------------------------------------
> > On Mon, May 13, 2024 at 04:24:41PM +0530, Bharat Bhushan wrote:
> > > NIX can assert backpressure to CPT on the NIX<=>CPT link.
> > > Keep the backpressure disabled for now. NIX block anyways
> > > handles backpressure asserted by MAC due to PFC or flow
> > > control pkts.
> > >
> > > Signed-off-by: Bharat Bhushan <[email protected]>
> >
> > ...
> >
> > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> >
> > ...
> >
> > > @@ -592,8 +596,16 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu
> > *rvu,
> > > bp = &nix_hw->bp;
> > > chan_base = pfvf->rx_chan_base + req->chan_base;
> > > for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
> > > - cfg = rvu_read64(rvu, blkaddr,
> > NIX_AF_RX_CHANX_CFG(chan));
> > > - rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
> > > + /* CPT channel for a given link channel is always
> > > + * assumed to be BIT(11) set in link channel.
> > > + */
> > > + if (cpt_link)
> > > + chan_v = chan | BIT(11);
> > > + else
> > > + chan_v = chan;
> >
> > Hi Bharat,
> >
> > The chan_v logic above seems to appear twice in this patch.
> > I'd suggest adding a helper.
>
> Will fix in next version.
>
> >
> > > +
> > > + cfg = rvu_read64(rvu, blkaddr,
> > NIX_AF_RX_CHANX_CFG(chan_v));
> > > + rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
> > > cfg & ~BIT_ULL(16));
> > >
> > > if (type == NIX_INTF_TYPE_LBK) {
> >
> > ...
> >
> > > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > index 7ec99c8d610c..e9d2e039a322 100644
> > > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > @@ -1705,6 +1705,31 @@ int otx2_nix_config_bp(struct otx2_nic *pfvf,
> > bool enable)
> > > }
> > > EXPORT_SYMBOL(otx2_nix_config_bp);
> > >
> > > +int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable)
> > > +{
> > > + struct nix_bp_cfg_req *req;
> > > +
> > > + if (enable)
> > > + req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf-
> > >mbox);
> > > + else
> > > + req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf-
> > >mbox);
> > > +
> > > + if (!req)
> > > + return -ENOMEM;
> > > +
> > > + req->chan_base = 0;
> > > +#ifdef CONFIG_DCB
> > > + req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
> > > + req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
> > > +#else
> > > + req->chan_cnt = 1;
> > > + req->bpid_per_chan = 0;
> > > +#endif
> >
> > IMHO, inline #ifdefs reduce readability and reduce maintainability.
> >
> > Would it be possible to either:
> >
> > 1. Include the pfc_en field in struct otx2_nic and make
> > sure it is set to 0 if CONFIG_DCB is unset; or
> > 2. Provide a wrapper that returns 0 if CONFIG_DCB is unset,
> > otherwise pfvf->pfc_en.
> >
> > I suspect 1 will have little downside and be easiest to implement.
>
> pfc_en is already a field of otx2_nic but under CONFIG_DCB. Will fix by adding a wrapper function like:
Thanks. Just to clarify, my first suggestion was to move
pfc_en outside of CONFIG_DCB in otx2_nic.
>
> static bool is_pfc_enabled(struct otx2_nic *pfvf)
> {
> #ifdef CONFIG_DCB
> return pfvf->pfc_en ? true : false;
FWIIW, I think this could also be:
return !!pfvf->pfc_en;
> #endif
> return false;
> }
Also, I do wonder if the following can work:
return IS_ENABLED(CONFIG_DCB) && pfvf->pfc_en;
>
> Using same like..
> ...
> if (is_pfc_enabled(pfvf)) {
If so, perhaps this can work:
if (IS_ENABLED(CONFIG_DCB) && pfvf->pfc_en) {
...
> req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
> req->bpid_per_chan = 1;
> } else {
> req->chan_cnt = 1;
> req->bpid_per_chan = 0;
> }
> ...
Please see inline
> -----Original Message-----
> From: Simon Horman <[email protected]>
> Sent: Tuesday, May 14, 2024 4:11 PM
> To: Bharat Bhushan <[email protected]>
> Cc: [email protected]; [email protected]; Sunil Kovvuri
> Goutham <[email protected]>; Geethasowjanya Akula
> <[email protected]>; Subbaraya Sundeep Bhatta <[email protected]>;
> Hariprasad Kelam <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; Jerin Jacob
> <[email protected]>; Linu Cherian <[email protected]>;
> [email protected]
> Subject: Re: [EXTERNAL] Re: [net-next,v2 3/8] octeontx2-af: Disable
> backpressure between CPT and NIX
>
> On Tue, May 14, 2024 at 06:39:45AM +0000, Bharat Bhushan wrote:
> > Please see inline
> >
> > > -----Original Message-----
> > > From: Simon Horman <[email protected]>
> > > Sent: Monday, May 13, 2024 9:45 PM
> > > To: Bharat Bhushan <[email protected]>
> > > Cc: [email protected]; [email protected]; Sunil
> > > Kovvuri Goutham <[email protected]>; Geethasowjanya Akula
> > > <[email protected]>; Subbaraya Sundeep Bhatta
> > > <[email protected]>; Hariprasad Kelam <[email protected]>;
> > > [email protected]; [email protected]; [email protected];
> > > [email protected]; Jerin Jacob <[email protected]>; Linu Cherian
> > > <[email protected]>; [email protected]
> > > Subject: [EXTERNAL] Re: [net-next,v2 3/8] octeontx2-af: Disable
> > > backpressure between CPT and NIX
> > >
> > >
> > > --------------------------------------------------------------------
> > > -- On Mon, May 13, 2024 at 04:24:41PM +0530, Bharat Bhushan wrote:
> > > > NIX can assert backpressure to CPT on the NIX<=>CPT link.
> > > > Keep the backpressure disabled for now. NIX block anyways handles
> > > > backpressure asserted by MAC due to PFC or flow control pkts.
> > > >
> > > > Signed-off-by: Bharat Bhushan <[email protected]>
> > >
> > > ...
> > >
> > > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
> > >
> > > ...
> > >
> > > > @@ -592,8 +596,16 @@ int rvu_mbox_handler_nix_bp_disable(struct
> > > > rvu
> > > *rvu,
> > > > bp = &nix_hw->bp;
> > > > chan_base = pfvf->rx_chan_base + req->chan_base;
> > > > for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
> > > > - cfg = rvu_read64(rvu, blkaddr,
> > > NIX_AF_RX_CHANX_CFG(chan));
> > > > - rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
> > > > + /* CPT channel for a given link channel is always
> > > > + * assumed to be BIT(11) set in link channel.
> > > > + */
> > > > + if (cpt_link)
> > > > + chan_v = chan | BIT(11);
> > > > + else
> > > > + chan_v = chan;
> > >
> > > Hi Bharat,
> > >
> > > The chan_v logic above seems to appear twice in this patch.
> > > I'd suggest adding a helper.
> >
> > Will fix in next version.
> >
> > >
> > > > +
> > > > + cfg = rvu_read64(rvu, blkaddr,
> > > NIX_AF_RX_CHANX_CFG(chan_v));
> > > > + rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v),
> > > > cfg & ~BIT_ULL(16));
> > > >
> > > > if (type == NIX_INTF_TYPE_LBK) {
> > >
> > > ...
> > >
> > > > diff --git
> > > > a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > > index 7ec99c8d610c..e9d2e039a322 100644
> > > > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
> > > > @@ -1705,6 +1705,31 @@ int otx2_nix_config_bp(struct otx2_nic
> > > > *pfvf,
> > > bool enable)
> > > > }
> > > > EXPORT_SYMBOL(otx2_nix_config_bp);
> > > >
> > > > +int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable) {
> > > > + struct nix_bp_cfg_req *req;
> > > > +
> > > > + if (enable)
> > > > + req = otx2_mbox_alloc_msg_nix_cpt_bp_enable(&pfvf-
> > > >mbox);
> > > > + else
> > > > + req = otx2_mbox_alloc_msg_nix_cpt_bp_disable(&pfvf-
> > > >mbox);
> > > > +
> > > > + if (!req)
> > > > + return -ENOMEM;
> > > > +
> > > > + req->chan_base = 0;
> > > > +#ifdef CONFIG_DCB
> > > > + req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
> > > > + req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; #else
> > > > + req->chan_cnt = 1;
> > > > + req->bpid_per_chan = 0;
> > > > +#endif
> > >
> > > IMHO, inline #ifdefs reduce readability and reduce maintainability.
> > >
> > > Would it be possible to either:
> > >
> > > 1. Include the pfc_en field in struct otx2_nic and make
> > > sure it is set to 0 if CONFIG_DCB is unset; or 2. Provide a
> > > wrapper that returns 0 if CONFIG_DCB is unset,
> > > otherwise pfvf->pfc_en.
> > >
> > > I suspect 1 will have little downside and be easiest to implement.
> >
> > pfc_en is already a field of otx2_nic but under CONFIG_DCB. Will fix by
> adding a wrapper function like:
>
> Thanks. Just to clarify, my first suggestion was to move pfc_en outside of
> CONFIG_DCB in otx2_nic.
>
> >
> > static bool is_pfc_enabled(struct otx2_nic *pfvf) { #ifdef CONFIG_DCB
> > return pfvf->pfc_en ? true : false;
>
> FWIIW, I think this could also be:
>
> return !!pfvf->pfc_en;
>
> > #endif
> > return false;
> > }
>
> Also, I do wonder if the following can work:
>
> return IS_ENABLED(CONFIG_DCB) && pfvf->pfc_en;
This is required at more than one place, so will keep wrapper function with this condition check.
Thanks
-Bharat
>
> >
> > Using same like..
> > ...
> > if (is_pfc_enabled(pfvf)) {
>
> If so, perhaps this can work:
>
> if (IS_ENABLED(CONFIG_DCB) && pfvf->pfc_en) {
> ...
>
> > req->chan_cnt = IEEE_8021QAZ_MAX_TCS;
> > req->bpid_per_chan = 1;
> > } else {
> > req->chan_cnt = 1;
> > req->bpid_per_chan = 0;
> > }
> > ...
On Tue, May 14, 2024 at 11:26:54AM +0000, Bharat Bhushan wrote:
> Please see inline
>
> > -----Original Message-----
> > From: Simon Horman <[email protected]>
..
> > > > I suspect 1 will have little downside and be easiest to implement.
> > >
> > > pfc_en is already a field of otx2_nic but under CONFIG_DCB. Will fix by
> > adding a wrapper function like:
> >
> > Thanks. Just to clarify, my first suggestion was to move pfc_en outside of
> > CONFIG_DCB in otx2_nic.
> >
> > >
> > > static bool is_pfc_enabled(struct otx2_nic *pfvf) { #ifdef CONFIG_DCB
> > > return pfvf->pfc_en ? true : false;
> >
> > FWIIW, I think this could also be:
> >
> > return !!pfvf->pfc_en;
> >
> > > #endif
> > > return false;
> > > }
> >
> > Also, I do wonder if the following can work:
> >
> > return IS_ENABLED(CONFIG_DCB) && pfvf->pfc_en;
>
> This is required at more than one place, so will keep wrapper function with this condition check.
Thanks, sounds good.
..