2024-05-13 11:45:18

by Ravi Gunasekaran

Subject: [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0

AM62P's DT source files are reused for J722S inorder to
avoid duplication of nodes. But J722S has additional
peripherals that are not present in AM62P.

Introduce a -main.dtsi to define such additional main
domain peripherals and define the SERDES0 node.

Signed-off-by: Ravi Gunasekaran <[email protected]>
---
Changes since v1:
----------------
* Newly introduced k3-j722s-main.dtsi to add main domain
peripherals that are additionally present in J722S

* Used generic node names - renamed "clock-cmnrefclk" to "clk-0",
"wiz@f000000" to "phy@f000000"

v1: https://lore.kernel.org/all/[email protected]/

arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 64 +++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
new file mode 100644
index 000000000000..1fd88cc8545f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S main domain peripherals
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clk-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+};
+
+&cbass_main {
+ serdes_wiz0: phy@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 279 1>;
+ assigned-clock-parents = <&k3_clks 279 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 279 1>,
+ <&k3_clks 279 1>,
+ <&k3_clks 279 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+};
+
+&main_conf {
+ serdes0_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
+ };
+};
--
2.17.1

2024-05-13 11:49:41

by Ravi Gunasekaran

Subject: Re: [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0

Roger,

On 5/13/24 5:14 PM, Ravi Gunasekaran wrote:
> AM62P's DT source files are reused for J722S inorder to
> avoid duplication of nodes. But J722S has additional
> peripherals that are not present in AM62P.
>
> Introduce a -main.dtsi to define such additional main
> domain peripherals and define the SERDES0 node.
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> Changes since v1:
> ----------------
> * Newly introduced k3-j722s-main.dtsi to add main domain
> peripherals that are additionally present in J722S
>
> * Used generic node names - renamed "clock-cmnrefclk" to "clk-0",
> "wiz@f000000" to "phy@f000000"
>

[...]

> +
> +&cbass_main {
> + serdes_wiz0: phy@f000000 {
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 279 1>;
> + assigned-clock-parents = <&k3_clks 279 5>;
> +
> + serdes0: serdes@f000000 {

[1] expects the node name to be "serdes". So I could not rename this node to "phy"
as discussed in the v1 series.

[1] - https://elixir.bootlin.com/linux/latest/source/drivers/phy/ti/phy-j721e-wiz.c#L1474

> + compatible = "ti,j721e-serdes-10g";


[...]

--
Regards,
Ravi