StarFive's StarLink Cache Controller flush/invalidates cache using non-
conventional RISC-V Zicbom extension instructions. This driver provides the
cache handling on StarFive RISC-V SoC.
Changes in v4:
- Move cache controller initialization to arch_initcall()
- Link to v3: https://lore.kernel.org/all/[email protected]/
Changes in v3:
- Fix code syntax
- Link to v2: https://lore.kernel.org/all/[email protected]/
Changes in v2:
- Change patch title from 'Add StarFive's StarLink-500 Cache Controller'
- Remove StarFive alternative from errata framework
- Fixes warning from https://lore.kernel.org/oe-kbuild-all/[email protected]/
- Flush completion through atomic timeout function
- Link to v1: https://lore.kernel.org/lkml/[email protected]/
Joshua Yeong (2):
cache: Add StarFive StarLink cache management for StarFive JH8100
dt-bindings: cache: Add docs for StarFive Starlink cache controller
Joshua Yeong (2):
cache: Add StarFive StarLink cache management
dt-bindings: cache: Add docs for StarFive Starlink cache controller
.../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++
drivers/cache/Kconfig | 9 ++
drivers/cache/Makefile | 5 +-
drivers/cache/starfive_starlink_cache.c | 130 ++++++++++++++++++
4 files changed, 208 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
create mode 100644 drivers/cache/starfive_starlink_cache.c
--
2.25.1
Add DT binding documentation used by StarFive's
Starlink cache controller.
Signed-off-by: Joshua Yeong <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
---
.../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
diff --git a/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
new file mode 100644
index 000000000000..6d61098e388b
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive StarLink Cache Controller
+
+maintainers:
+ - Joshua Yeong <[email protected]>
+
+description:
+ StarFive's StarLink Cache Controller manages the L3 cache shared between
+ clusters of CPU cores. The cache driver enables RISC-V non-standard cache
+ management as an alternative to instructions in the RISC-V Zicbom extension.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+# We need a select here so we don't match all nodes with 'cache'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh8100-starlink-cache
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jh8100-starlink-cache
+ - const: cache
+
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - cache-block-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cache-controller@15000000 {
+ compatible = "starfive,jh8100-starlink-cache", "cache";
+ reg = <0x0 0x15000000 0x0 0x278>;
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <8192>;
+ cache-size = <0x400000>;
+ cache-unified;
+ };
+ };
--
2.25.1
On Wed, May 15, 2024 at 01:02:51PM +0800, Joshua Yeong wrote:
> StarFive's StarLink Cache Controller flush/invalidates cache using non-
> conventional RISC-V Zicbom extension instructions. This driver provides the
> cache handling on StarFive RISC-V SoC.
>
> Changes in v4:
> - Move cache controller initialization to arch_initcall()
> - Link to v3: https://lore.kernel.org/all/[email protected]/
Why are you resending this? A resend with no context doesn't help me
understand what you want done.
There's been no action taken yet with the v4 that you had sent because
there was not enough time between its arrival and when I had to send a
PR with 6.10 material. Right now it is the merge window, so there's
nothing that can be done here til that ends.
Cheers,
Conor.
From: Conor Dooley <[email protected]>
On Wed, 15 May 2024 13:02:51 +0800, Joshua Yeong wrote:
> StarFive's StarLink Cache Controller flush/invalidates cache using non-
> conventional RISC-V Zicbom extension instructions. This driver provides the
> cache handling on StarFive RISC-V SoC.
>
> Changes in v4:
> - Move cache controller initialization to arch_initcall()
> - Link to v3: https://lore.kernel.org/all/[email protected]/
>
> [...]
I've picked these two up and applied to riscv-cache-for-next, with their
order corrected. Emil, shout if there was something left from your
feedback that was unimplemented. The wording etc seems to have been
"fixed" in this version.
[1/2] cache: Add StarFive StarLink cache management
https://git.kernel.org/conor/c/cabff60ca77d
[2/2] dt-bindings: cache: Add docs for StarFive Starlink cache controller
https://git.kernel.org/conor/c/c6005d4dd216
Thanks,
Conor.