The Amlogic A1 SoC family utilizes static operating points and a
PWM-controlled core voltage regulator that is specific to the board. As
the main CPU clock input, the SoC uses CLKID_CPU_CLK from the CPU clock
controller, which can be inherited from the system PLL (syspll) or a
fixed CPU clock.
Currently, the stable operating points at all frequencies are set to
800mV. This value is obtained from the vendor setup of several A1
boards.
The current patch series includes:
* CPU clock controller declaration
* syspll setup in the PLL controller
* operating points
* CPU special power parameters: voltage-tolerance, clock-latency,
capacity-dmips-mhz, dynamic-power-coefficient
Please be informed that the AD402 vddcpu PWM regulator does not exist in
this patch series because currently PWM A1 support is under development.
However, it should look like:
```
vddcpu: regulator-vddcpu {
compatible = "pwm-regulator";
pinctrl-0 = <&pwm_f_pins4>;
pinctrl-names = "default";
regulator-name = "VDDCPU";
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
pwm-supply = <&dc_12v_in>;
pwms = <&pwm_ef 1 1500 0>; // 667kHz
voltage-table = <1050000 0>,
<1040000 3>,
<1030000 6>,
<1020000 8>,
<1010000 11>,
<1000000 14>,
<990000 17>,
<980000 20>,
<970000 23>,
<960000 26>,
<950000 29>,
<940000 31>,
<930000 34>,
<920000 37>,
<910000 40>,
<900000 43>,
<890000 45>,
<880000 48>,
<870000 51>,
<860000 54>,
<850000 56>,
<840000 59>,
<830000 62>,
<820000 65>,
<810000 68>,
<800000 70>,
<790000 73>,
<780000 76>,
<770000 79>,
<760000 81>,
<750000 84>,
<740000 87>,
<730000 89>,
<720000 92>,
<710000 95>,
<700000 98>,
<690000 100>;
regulator-boot-on;
regulator-always-on;
};
```
This patch series depends on [1].
Changes v3 since v2 at [3]:
- move sys_pll_div16 clock from a1-pll clkc to a1-peripherals clkc
as Jerome suggested, so dt connection is changed too
Changes v2 since v1 at [2]:
- remove holes from the beginning of cpu clock controller regmap
- move sys_pll_div16 to the end of the clocks list
Links:
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
[3] https://lore.kernel.org/all/[email protected]/
Signed-off-by: Dmitry Rokosov <[email protected]>
Dmitry Rokosov (4):
arm64: dts: amlogic: a1: add new syspll_in input for clkc_pll
controller
arm64: dts: amlogic: a1: declare cpu clock controller
arm64: dts: amlogic: a1: add new input clock 'sys_pll' to clkc_periphs
arm64: dts: amlogic: a1: setup CPU power management
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 70 +++++++++++++++++++++--
1 file changed, 66 insertions(+), 4 deletions(-)
--
2.43.0
The Amlogic A1 SoC family relies on the CPU clock controller to generate
CPU clocks, serving a crucial function. It has 4 inputs: main
oscillator, fixed clocks and system pll.
Signed-off-by: Dmitry Rokosov <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index feed2bd7ae48..afb5d7361177 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/amlogic,a1-cpu-clkc.h>
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
#include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
@@ -94,6 +95,19 @@ soc {
#size-cells = <2>;
ranges;
+ clkc_cpu: clock-controller@fd000000 {
+ compatible = "amlogic,a1-cpu-clkc";
+ reg = <0 0xfd000080 0 0x8>;
+ #clock-cells = <1>;
+
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_SYS_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3",
+ "sys_pll", "xtal";
+ };
+
spifc: spi@fd000400 {
compatible = "amlogic,a1-spifc";
reg = <0x0 0xfd000400 0x0 0x290>;
--
2.43.0
The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.
Signed-off-by: Dmitry Rokosov <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index afb5d7361177..f73bb7d1f381 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -747,10 +747,12 @@ clkc_periphs: clock-controller@800 {
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
- <&xtal>;
+ <&xtal>,
+ <&clkc_pll CLKID_SYS_PLL>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
- "hifi_pll", "xtal";
+ "hifi_pll", "xtal",
+ "sys_pll";
};
i2c0: i2c@1400 {
--
2.43.0
The Amlogic A1 SoC family utilizes static operating points and a
PWM-controlled core voltage regulator, which is specific to the board.
As the main CPU clock input, the SoC uses CLKID_CPU_CLK from the CPU
clock controller, which can be inherited from the system PLL (syspll) or
a fixed CPU clock.
Currently, the stable operating points at all frequencies are set to
800mV. This value is obtained from the vendor setup of several A1
boards.
Signed-off-by: Dmitry Rokosov <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 44 +++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index f73bb7d1f381..5746c6a5b07b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -33,6 +33,13 @@ cpu0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
+ clocks = <&clkc_cpu CLKID_CPU_CLK>;
+ clock-names = "core_clk";
+ operating-points-v2 = <&cpu_opp_table0>;
+ voltage-tolerance = <0>;
+ clock-latency = <50000>;
+ capacity-dmips-mhz = <400>;
+ dynamic-power-coefficient = <80>;
#cooling-cells = <2>;
};
@@ -42,6 +49,13 @@ cpu1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
+ clocks = <&clkc_cpu CLKID_CPU_CLK>;
+ clock-names = "core_clk";
+ operating-points-v2 = <&cpu_opp_table0>;
+ voltage-tolerance = <0>;
+ clock-latency = <50000>;
+ capacity-dmips-mhz = <400>;
+ dynamic-power-coefficient = <80>;
#cooling-cells = <2>;
};
@@ -52,6 +66,36 @@ l2: l2-cache0 {
};
};
+ cpu_opp_table0: cpu_opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <128000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <256000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <512000000>;
+ opp-microvolt = <800000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-microvolt = <800000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <800000>;
+ };
+ };
+
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
clocks = <&clkc_periphs CLKID_OTP>;
--
2.43.0