IOMMU implementations now sometimes bounce memory through SWIOTLB to
achieve cacheline alignment [1], or prevent DMA attacks by untrusted
devices [2]. These uses of SWIOTLB differ conceptually from historical
use which was a solution to the problem of device addressing
limitations that prevent DMA to some portion of system memory
(typically beyond 4 GiB). IOMMUs also solve the problem of device
addressing limitations and therefore eliminate the need for SWIOTLB for
that purpose. However as mentioned, IOMMUs can use SWIOTLB for other
purposes.
The swiotlb=force kernel command line parameter does not impact IOMMU
related use of SWIOTLB, and that is intentional. IOMMUs cannot be forced
to use SWIOTLB for all buffers. Update the documentation for the swiotlb
parameter to clarify that SWIOTLB use can only be forced in scenarios
where an IOMMU is not involved.
[1] https://lore.kernel.org/all/[email protected]
[2] https://lore.kernel.org/all/[email protected]/
Signed-off-by: T.J. Mercier <[email protected]>
Reviewed-by: Petr Tesarik <[email protected]>
---
Documentation/admin-guide/kernel-parameters.txt | 1 +
Documentation/arch/x86/x86_64/boot-options.rst | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 213d0719e2b7..84c582ac246c 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -6486,6 +6486,7 @@
to a power of 2.
force -- force using of bounce buffers even if they
wouldn't be automatically used by the kernel
+ where a hardware IOMMU is not involved
noforce -- Never use bounce buffers (for debugging)
switches= [HW,M68k,EARLY]
diff --git a/Documentation/arch/x86/x86_64/boot-options.rst b/Documentation/arch/x86/x86_64/boot-options.rst
index 137432d34109..a37139d1752f 100644
--- a/Documentation/arch/x86/x86_64/boot-options.rst
+++ b/Documentation/arch/x86/x86_64/boot-options.rst
@@ -292,6 +292,9 @@ implementation:
Prereserve that many 2K slots for the software IO bounce buffering.
force
Force all IO through the software TLB.
+ Hardware IOMMU implementations can use SWIOTLB bounce buffering in
+ some circumstances, but they cannot be forced to always use them, so
+ this option only has an effect when no hardware IOMMU is involved.
noforce
Do not initialize the software TLB.
--
2.45.0.rc1.225.g2a3ae87e7f-goog
Commit 20347fca71a3 ("swiotlb: split up the global swiotlb lock") added
the ability to specify the number of SWIOTLB areas, but boot-options.rst
was not updated as part of that commit. Also adjust the swiotlb option
syntax to clarify that force and noforce are mutually exclusive.
Reported-by: Michael Kelley <[email protected]>
Fixes: 20347fca71a3 ("swiotlb: split up the global swiotlb lock")
Signed-off-by: T.J. Mercier <[email protected]>
---
Documentation/arch/x86/x86_64/boot-options.rst | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/x86/x86_64/boot-options.rst b/Documentation/arch/x86/x86_64/boot-options.rst
index a37139d1752f..d54e636f91f7 100644
--- a/Documentation/arch/x86/x86_64/boot-options.rst
+++ b/Documentation/arch/x86/x86_64/boot-options.rst
@@ -287,9 +287,11 @@ iommu options only relevant to the AMD GART hardware IOMMU:
iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
implementation:
- swiotlb=<slots>[,force,noforce]
+ swiotlb=[<slots>][,<areas>][, [force] | [noforce] ]
<slots>
Prereserve that many 2K slots for the software IO bounce buffering.
+ <areas>
+ Number of SWIOTLB areas with their own lock. Must be a power of 2.
force
Force all IO through the software TLB.
Hardware IOMMU implementations can use SWIOTLB bounce buffering in
--
2.45.0.rc1.225.g2a3ae87e7f-goog