From: Qingfang Deng <[email protected]>
rd and rs don't have to be the same.
Signed-off-by: Qingfang Deng <[email protected]>
---
arch/riscv/include/asm/arch_hweight.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h
index 85b2c443823e..613769b9cdc9 100644
--- a/arch/riscv/include/asm/arch_hweight.h
+++ b/arch/riscv/include/asm/arch_hweight.h
@@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
asm (".option push\n"
".option arch,+zbb\n"
- CPOPW "%0, %0\n"
+ CPOPW "%0, %1\n"
".option pop\n"
- : "+r" (w) : :);
+ : "=r" (w) : "r" (w) :);
return w;
@@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
asm (".option push\n"
".option arch,+zbb\n"
- "cpop %0, %0\n"
+ "cpop %0, %1\n"
".option pop\n"
- : "+r" (w) : :);
+ : "=r" (w) : "r" (w) :);
return w;
--
2.34.1
> -----Original Message-----
> From: Qingfang Deng <[email protected]>
> Sent: Thursday, May 23, 2024 5:43 PM
> To: Paul Walmsley <[email protected]>; Palmer Dabbelt
> <[email protected]>; Albert Ou <[email protected]>; linux-
> [email protected]; [email protected]
> Cc: Wang, Xiao W <[email protected]>; Qingfang Deng
> <[email protected]>
> Subject: [PATCH] riscv: hweight: relax assembly constraints
>
> From: Qingfang Deng <[email protected]>
>
> rd and rs don't have to be the same.
>
> Signed-off-by: Qingfang Deng <[email protected]>
> ---
> arch/riscv/include/asm/arch_hweight.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/include/asm/arch_hweight.h
> b/arch/riscv/include/asm/arch_hweight.h
> index 85b2c443823e..613769b9cdc9 100644
> --- a/arch/riscv/include/asm/arch_hweight.h
> +++ b/arch/riscv/include/asm/arch_hweight.h
> @@ -26,9 +26,9 @@ static __always_inline unsigned int
> __arch_hweight32(unsigned int w)
>
> asm (".option push\n"
> ".option arch,+zbb\n"
> - CPOPW "%0, %0\n"
> + CPOPW "%0, %1\n"
> ".option pop\n"
> - : "+r" (w) : :);
> + : "=r" (w) : "r" (w) :);
The above code piece takes variable "w" as both input and output, so intuitively, the previous
patch made rs and rd the same.
Though rs and rd can be different, do you see performance difference with this change?
Or any analysis from assembly dump?
BRs,
Xiao
>
> return w;
>
> @@ -57,9 +57,9 @@ static __always_inline unsigned long
> __arch_hweight64(__u64 w)
>
> asm (".option push\n"
> ".option arch,+zbb\n"
> - "cpop %0, %0\n"
> + "cpop %0, %1\n"
> ".option pop\n"
> - : "+r" (w) : :);
> + : "=r" (w) : "r" (w) :);
>
> return w;
>
> --
> 2.34.1
Hi,
On Fri, May 24, 2024 at 9:02 AM Wang, Xiao W <[email protected]> wrote:
>
>
>
> > -----Original Message-----
> > From: Qingfang Deng <[email protected]>
> > Sent: Thursday, May 23, 2024 5:43 PM
> > To: Paul Walmsley <[email protected]>; Palmer Dabbelt
> > <[email protected]>; Albert Ou <[email protected]>; linux-
> > [email protected]; [email protected]
> > Cc: Wang, Xiao W <[email protected]>; Qingfang Deng
> > <[email protected]>
> > Subject: [PATCH] riscv: hweight: relax assembly constraints
> >
> > From: Qingfang Deng <[email protected]>
> >
> > rd and rs don't have to be the same.
> >
> > Signed-off-by: Qingfang Deng <[email protected]>
> > ---
> > arch/riscv/include/asm/arch_hweight.h | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/arch_hweight.h
> > b/arch/riscv/include/asm/arch_hweight.h
> > index 85b2c443823e..613769b9cdc9 100644
> > --- a/arch/riscv/include/asm/arch_hweight.h
> > +++ b/arch/riscv/include/asm/arch_hweight.h
> > @@ -26,9 +26,9 @@ static __always_inline unsigned int
> > __arch_hweight32(unsigned int w)
> >
> > asm (".option push\n"
> > ".option arch,+zbb\n"
> > - CPOPW "%0, %0\n"
> > + CPOPW "%0, %1\n"
> > ".option pop\n"
> > - : "+r" (w) : :);
> > + : "=r" (w) : "r" (w) :);
>
> The above code piece takes variable "w" as both input and output, so intuitively, the previous
> patch made rs and rd the same.
> Though rs and rd can be different, do you see performance difference with this change?
> Or any analysis from assembly dump?
By making rs and rd different, we can save some `mv` instructions.
>
> BRs,
> Xiao
>
> >
> > return w;
> >
> > @@ -57,9 +57,9 @@ static __always_inline unsigned long
> > __arch_hweight64(__u64 w)
> >
> > asm (".option push\n"
> > ".option arch,+zbb\n"
> > - "cpop %0, %0\n"
> > + "cpop %0, %1\n"
> > ".option pop\n"
> > - : "+r" (w) : :);
> > + : "=r" (w) : "r" (w) :);
> >
> > return w;
> >
> > --
> > 2.34.1
>
> -----Original Message-----
> From: Qingfang Deng <[email protected]>
> Sent: Friday, May 24, 2024 2:05 PM
> To: Wang, Xiao W <[email protected]>
> Cc: Paul Walmsley <[email protected]>; Palmer Dabbelt
> <[email protected]>; Albert Ou <[email protected]>; linux-
> [email protected]; [email protected]; Qingfang Deng
> <[email protected]>
> Subject: Re: [PATCH] riscv: hweight: relax assembly constraints
>
> Hi,
>
> On Fri, May 24, 2024 at 9:02 AM Wang, Xiao W <[email protected]>
> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Qingfang Deng <[email protected]>
> > > Sent: Thursday, May 23, 2024 5:43 PM
> > > To: Paul Walmsley <[email protected]>; Palmer Dabbelt
> > > <[email protected]>; Albert Ou <[email protected]>; linux-
> > > [email protected]; [email protected]
> > > Cc: Wang, Xiao W <[email protected]>; Qingfang Deng
> > > <[email protected]>
> > > Subject: [PATCH] riscv: hweight: relax assembly constraints
> > >
> > > From: Qingfang Deng <[email protected]>
> > >
> > > rd and rs don't have to be the same.
> > >
> > > Signed-off-by: Qingfang Deng <[email protected]>
> > > ---
> > > arch/riscv/include/asm/arch_hweight.h | 8 ++++----
> > > 1 file changed, 4 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/arch_hweight.h
> > > b/arch/riscv/include/asm/arch_hweight.h
> > > index 85b2c443823e..613769b9cdc9 100644
> > > --- a/arch/riscv/include/asm/arch_hweight.h
> > > +++ b/arch/riscv/include/asm/arch_hweight.h
> > > @@ -26,9 +26,9 @@ static __always_inline unsigned int
> > > __arch_hweight32(unsigned int w)
> > >
> > > asm (".option push\n"
> > > ".option arch,+zbb\n"
> > > - CPOPW "%0, %0\n"
> > > + CPOPW "%0, %1\n"
> > > ".option pop\n"
> > > - : "+r" (w) : :);
> > > + : "=r" (w) : "r" (w) :);
> >
> > The above code piece takes variable "w" as both input and output, so
> intuitively, the previous
> > patch made rs and rd the same.
> > Though rs and rd can be different, do you see performance difference with
> this change?
> > Or any analysis from assembly dump?
>
> By making rs and rd different, we can save some `mv` instructions.
OK, I guess in some cases, the original data needs be saved for later usage.
Then, we can relax the assembly constraint here and gives flexibility to compiler
For optimization.
It's better to start the patch tile with " riscv: lib:", maybe you can make the title as:
riscv: lib: relax assembly constraints in hweight
BRs,
Xiao
>
> >
> > BRs,
> > Xiao
> >
> > >
> > > return w;
> > >
> > > @@ -57,9 +57,9 @@ static __always_inline unsigned long
> > > __arch_hweight64(__u64 w)
> > >
> > > asm (".option push\n"
> > > ".option arch,+zbb\n"
> > > - "cpop %0, %0\n"
> > > + "cpop %0, %1\n"
> > > ".option pop\n"
> > > - : "+r" (w) : :);
> > > + : "=r" (w) : "r" (w) :);
> > >
> > > return w;
> > >
> > > --
> > > 2.34.1
> >