2024-05-29 18:55:03

by Rajnesh Kanwal

[permalink] [raw]

Subject: [PATCH RFC 3/6] riscv: perf: Add Control Transfer Records extension parsing

---

Adding CTR extension in ISA extension map to lookup for extension
availability.

Signed-off-by: Rajnesh Kanwal <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 4 ++++
arch/riscv/kernel/cpufeature.c | 2 ++
2 files changed, 6 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b8cc459ee8a4..aff5ef398671 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -86,6 +86,8 @@
#define RISCV_ISA_EXT_SSCCFG 77
#define RISCV_ISA_EXT_SMCDELEG 78
#define RISCV_ISA_EXT_SMCNTRPMF 79
+#define RISCV_ISA_EXT_SMCTR 80
+#define RISCV_ISA_EXT_SSCTR 81

#define RISCV_ISA_EXT_XLINUXENVCFG 127

@@ -95,9 +97,11 @@
#ifdef CONFIG_RISCV_M_MODE
#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SMCSRIND
+#define RISCV_ISA_EXT_SxCTR RISCV_ISA_EXT_SMCTR
#else
#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SSCSRIND
+#define RISCV_ISA_EXT_SxCTR RISCV_ISA_EXT_SSCTR
#endif

#endif /* _ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d1fb6a8c5492..4334d822b2f2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -298,6 +298,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
__RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG),
+ __RISCV_ISA_EXT_DATA(smctr, RISCV_ISA_EXT_SMCTR),
__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
__RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF),
__RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND),
@@ -305,6 +306,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND),
__RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+ __RISCV_ISA_EXT_DATA(ssctr, RISCV_ISA_EXT_SSCTR),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
--
2.34.1

2024-06-05 18:14:06

by Conor Dooley

[permalink] [raw]

Subject: Re: [PATCH RFC 3/6] riscv: perf: Add Control Transfer Records extension parsing

---

On Wed, May 29, 2024 at 07:53:34PM +0100, Rajnesh Kanwal wrote:
> Adding CTR extension in ISA extension map to lookup for extension
> availability.
>
> Signed-off-by: Rajnesh Kanwal <[email protected]>

Same comment here about $subject.

You're also missing dt-bindings for the extension.

Thanks,
Conor.

> ---
> arch/riscv/include/asm/hwcap.h | 4 ++++
> arch/riscv/kernel/cpufeature.c | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b8cc459ee8a4..aff5ef398671 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -86,6 +86,8 @@
> #define RISCV_ISA_EXT_SSCCFG 77
> #define RISCV_ISA_EXT_SMCDELEG 78
> #define RISCV_ISA_EXT_SMCNTRPMF 79
> +#define RISCV_ISA_EXT_SMCTR 80
> +#define RISCV_ISA_EXT_SSCTR 81
>
> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>
> @@ -95,9 +97,11 @@
> #ifdef CONFIG_RISCV_M_MODE
> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
> #define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SMCSRIND
> +#define RISCV_ISA_EXT_SxCTR RISCV_ISA_EXT_SMCTR
> #else
> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
> #define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SSCSRIND
> +#define RISCV_ISA_EXT_SxCTR RISCV_ISA_EXT_SSCTR
> #endif
>
> #endif /* _ASM_RISCV_HWCAP_H */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index d1fb6a8c5492..4334d822b2f2 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -298,6 +298,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG),
> + __RISCV_ISA_EXT_DATA(smctr, RISCV_ISA_EXT_SMCTR),
> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF),
> __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND),
> @@ -305,6 +306,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND),
> __RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> + __RISCV_ISA_EXT_DATA(ssctr, RISCV_ISA_EXT_SSCTR),
> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> --
> 2.34.1
>

---

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