by Bjorn Helgaas

[permalink] [raw]

Subject: Re: [PATCH v6 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries

On Sat, Jun 01, 2024 at 08:34:04PM +0530, Sunil V L wrote:
> ACPI MADT entries for interrupt controllers don't have a way to describe
> the hierarchy. However, the hierarchy is known to the architecture and
> on RISC-V platforms, the MADT sub table types are ordered in the
> incremental order from the root controller which is RINTC. So, add
> architecture function for RISC-V to reorder the interrupt controller
> probing as per the hierarchy as below.

Is this ordering requirement documented anywhere? I don't see it in
the RISC-V ECRs to the ACPI r6.5 spec.

I guess the implication is that you need to process MADT structures in
order of ascending acpi_madt_type:

ACPI_MADT_TYPE_RINTC = 24,
ACPI_MADT_TYPE_IMSIC = 25,
ACPI_MADT_TYPE_APLIC = 26,
ACPI_MADT_TYPE_PLIC = 27,

regardless of the order they appear in the MADT? I.e., process all
the RINTC structures (in order of appearance in MADT), followed by all
the IMSIC structures, then all the APLIC structures, etc?

> Signed-off-by: Sunil V L <[email protected]>
> ---
> drivers/acpi/riscv/Makefile | 2 +-
> drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 33 insertions(+), 1 deletion(-)
> create mode 100644 drivers/acpi/riscv/irq.c
>
> diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
> index 877de00d1b50..a96fdf1e2cb8 100644
> --- a/drivers/acpi/riscv/Makefile
> +++ b/drivers/acpi/riscv/Makefile
> @@ -1,4 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> -obj-y += rhct.o init.o
> +obj-y += rhct.o init.o irq.o
> obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
> obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o
> diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
> new file mode 100644
> index 000000000000..f56e103a501f
> --- /dev/null
> +++ b/drivers/acpi/riscv/irq.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023-2024, Ventana Micro Systems Inc
> + * Author: Sunil V L <[email protected]>
> + *

Spurious blank line.

> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/sort.h>
> +
> +static int irqchip_cmp_func(const void *in0, const void *in1)
> +{
> + struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
> + struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
> +
> + return (elem0->type > elem1->type) - (elem0->type < elem1->type);
> +}
> +
> +/*
> + * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
> + * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
> + * order, this arch function will reorder the probe functions as per the
> + * required order for the architecture.

But this comment seems to contradict the commit log. This comment
says you should process MADT structures in the order they appear in
the MADT. But if that were the case, you wouldn't need to sort
anything.

Maybe "defined in the order they should be probed" means "in order of
increasing Interrupt Controller structure type value"?

> + */
> +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
> +{
> + struct acpi_probe_entry *ape = ap_head;
> +
> + if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
> + return;
> + sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
> +}
> --
> 2.40.1
>

2024-06-06 22:33:11

by Bjorn Helgaas

[permalink] [raw]

Subject: Re: [PATCH v6 11/17] ACPI: RISC-V: Initialize GSI mapping structures

On Sat, Jun 01, 2024 at 08:34:05PM +0530, Sunil V L wrote:
> RISC-V has PLIC and APLIC in MADT as well as namespace devices.
> Initialize the list of those structures using MADT and namespace devices
> to create mapping between the ACPI handle and the GSI ranges. This will
> be used later to add dependencies.

From a long ways away, this looks like "map a GSI to an interrupt
controller described either via MADT or namespace" plus a little bit
of RISC-V stuff.

That first part, mapping GSI to interrupt controller, is generic and
other arches need to do the same thing. It would be nice if every
arch didn't have to roll their own list of (handle, gsi_base, nr_irqs)
tuples. And it might clarify the whole concept of GSI, which is
conceptually very simple but gets muddied by all the magic stuff
around it.

This is probably just wishful thinking and not actionable feedback.

> Signed-off-by: Sunil V L <[email protected]>
> ---
> arch/riscv/include/asm/irq.h | 22 ++++++
> drivers/acpi/riscv/init.c | 2 +
> drivers/acpi/riscv/init.h | 4 +
> drivers/acpi/riscv/irq.c | 142 +++++++++++++++++++++++++++++++++++
> 4 files changed, 170 insertions(+)
> create mode 100644 drivers/acpi/riscv/init.h
>
> diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
> index 8e10a94430a2..44a0b128c602 100644
> --- a/arch/riscv/include/asm/irq.h
> +++ b/arch/riscv/include/asm/irq.h
> @@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
>
> struct fwnode_handle *riscv_get_intc_hwnode(void);
>
> +#ifdef CONFIG_ACPI
> +
> +enum riscv_irqchip_type {
> + ACPI_RISCV_IRQCHIP_INTC = 0x00,
> + ACPI_RISCV_IRQCHIP_IMSIC = 0x01,
> + ACPI_RISCV_IRQCHIP_PLIC = 0x02,
> + ACPI_RISCV_IRQCHIP_APLIC = 0x03,
> +};
> +
> +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
> + u32 *id, u32 *nr_irqs, u32 *nr_idcs);
> +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi);
> +
> +#else
> +static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
> + u32 *id, u32 *nr_irqs, u32 *nr_idcs)
> +{
> + return 0;
> +}
> +
> +#endif /* CONFIG_ACPI */
> +
> #endif /* _ASM_RISCV_IRQ_H */
> diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c
> index 5f7571143245..22db97f7a772 100644
> --- a/drivers/acpi/riscv/init.c
> +++ b/drivers/acpi/riscv/init.c
> @@ -6,7 +6,9 @@
> */
>
> #include <linux/acpi.h>
> +#include "init.h"
>
> void __init acpi_riscv_init(void)
> {
> + riscv_acpi_init_gsi_mapping();
> }
> diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h
> new file mode 100644
> index 000000000000..0b9a07e4031f
> --- /dev/null
> +++ b/drivers/acpi/riscv/init.h
> @@ -0,0 +1,4 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#include <linux/init.h>
> +
> +void __init riscv_acpi_init_gsi_mapping(void);
> diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
> index f56e103a501f..0473428e8d1e 100644
> --- a/drivers/acpi/riscv/irq.c
> +++ b/drivers/acpi/riscv/irq.c
> @@ -7,6 +7,21 @@
>
> #include <linux/acpi.h>
> #include <linux/sort.h>
> +#include <linux/irq.h>
> +
> +#include "init.h"
> +
> +struct riscv_ext_intc_list {
> + acpi_handle handle;
> + u32 gsi_base;
> + u32 nr_irqs;
> + u32 nr_idcs;
> + u32 id;
> + u32 type;
> + struct list_head list;
> +};
> +
> +LIST_HEAD(ext_intc_list);
>
> static int irqchip_cmp_func(const void *in0, const void *in1)
> {
> @@ -30,3 +45,130 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
> return;
> sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
> }
> +
> +static void riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle)
> +{
> + struct riscv_ext_intc_list *ext_intc_element;
> + struct list_head *i, *tmp;
> +
> + list_for_each_safe(i, tmp, &ext_intc_list) {
> + ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
> + if (gsi_base == ext_intc_element->gsi_base) {
> + ext_intc_element->handle = handle;
> + return;
> + }
> + }
> +
> + acpi_handle_err(handle, "failed to find the GSI mapping entry\n");
> +}
> +
> +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
> + u32 *id, u32 *nr_irqs, u32 *nr_idcs)
> +{
> + struct riscv_ext_intc_list *ext_intc_element;
> + struct list_head *i, *tmp;
> +
> + list_for_each_safe(i, tmp, &ext_intc_list) {
> + ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
> + if (ext_intc_element->handle == ACPI_HANDLE_FWNODE(fwnode)) {
> + *gsi_base = ext_intc_element->gsi_base;
> + *id = ext_intc_element->id;
> + *nr_irqs = ext_intc_element->nr_irqs;
> + if (nr_idcs)
> + *nr_idcs = ext_intc_element->nr_idcs;
> +
> + return 0;
> + }
> + }
> +
> + return -ENODEV;
> +}
> +
> +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi)
> +{
> + struct riscv_ext_intc_list *ext_intc_element;
> + struct acpi_device *adev;
> + struct list_head *i, *tmp;
> +
> + list_for_each_safe(i, tmp, &ext_intc_list) {
> + ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
> + if (gsi >= ext_intc_element->gsi_base &&
> + gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) {
> + adev = acpi_fetch_acpi_dev(ext_intc_element->handle);
> + if (!adev)
> + return NULL;
> +
> + return acpi_fwnode_handle(adev);
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs,
> + u32 id, u32 type)
> +{
> + struct riscv_ext_intc_list *ext_intc_element;
> +
> + ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL);
> + if (!ext_intc_element)
> + return -ENOMEM;
> +
> + ext_intc_element->gsi_base = gsi_base;
> + ext_intc_element->nr_irqs = nr_irqs;
> + ext_intc_element->nr_idcs = nr_idcs;
> + ext_intc_element->id = id;
> + list_add_tail(&ext_intc_element->list, &ext_intc_list);
> + return 0;
> +}
> +
> +static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u32 level,
> + void *context, void **return_value)
> +{
> + acpi_status status;
> + u64 gbase;
> +
> + if (!acpi_has_method(handle, "_GSB")) {
> + acpi_handle_err(handle, "_GSB method not found\n");
> + return AE_OK;
> + }
> +
> + status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase);
> + if (ACPI_FAILURE(status)) {
> + acpi_handle_err(handle, "failed to evaluate _GSB method\n");
> + return AE_OK;
> + }
> +
> + riscv_acpi_update_gsi_handle((u32)gbase, handle);
> + return AE_OK;
> +}
> +
> +static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header;
> +
> + return riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources, aplic->num_idcs,
> + aplic->id, ACPI_RISCV_IRQCHIP_APLIC);
> +}
> +
> +static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header;
> +
> + return riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0,
> + plic->id, ACPI_RISCV_IRQCHIP_PLIC);
> +}
> +
> +void __init riscv_acpi_init_gsi_mapping(void)
> +{
> + /* There can be either PLIC or APLIC */
> + if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt, 0) > 0) {
> + acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL);
> + return;
> + }
> +
> + if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_madt, 0) > 0)
> + acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL);
> +}
> --
> 2.40.1
>