STM32MP13 is STM32 SOC with 2 GMACs instances
GMAC IP version is SNPS 4.20.
GMAC IP configure with 1 RX and 1 TX queue.
DMA HW capability register supported
RX Checksum Offload Engine supported
TX Checksum insertion supported
Wake-Up On Lan supported
TSO supported
Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
Remark from Serge Semin (upate commits msg)
V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
manage PHY regulator (in glue or PHY side)
- Integrate RFC from Marek
- Remark from Rob Herring in YAML documentation
V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg)
- Remark from Rasmus (add sign-off, add base-commit)
- Remark from Sai Krishna Gajula
Christophe Roullier (6):
dt-bindings: net: add STM32MP13 compatible in documentation for stm32
net: ethernet: stmmac: add management of stm32mp13 for stm32
ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
Marek Vasut (5):
net: stmmac: dwmac-stm32: Separate out external clock rate validation
net: stmmac: dwmac-stm32: Separate out external clock selector
net: stmmac: dwmac-stm32: Extract PMCR configuration
net: stmmac: dwmac-stm32: Clean up the debug prints
net: stmmac: dwmac-stm32: Fix Mhz to MHz
.../devicetree/bindings/net/stm32-dwmac.yaml | 41 ++++-
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 ++++++++
arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++
arch/arm/boot/dts/st/stm32mp133.dtsi | 31 ++++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++
arch/arm/configs/multi_v7_defconfig | 1 +
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 172 ++++++++++++++----
7 files changed, 330 insertions(+), 47 deletions(-)
base-commit: cd0057ad75116bacf16fea82e48c1db642971136
--
2.25.1
From: Marek Vasut <[email protected]>
Pull the external clock selector into a separate function, to avoid
conflating it with external clock rate validation and clock mux
register configuration. This should make the code easier to read and
understand.
The dwmac->enable_eth_ck variable in the end indicates whether the MAC
clock are supplied by external oscillator (true) or internal RCC clock
IP (false). The dwmac->enable_eth_ck value is set based on multiple DT
properties, some of them deprecated, some of them specific to bus mode.
The following DT properties and variables are taken into account. In
each case, if the property is present or true, MAC clock is supplied
by external oscillator.
- "st,ext-phyclk", assigned to variable dwmac->ext_phyclk
- Used in any mode (MII/RMII/GMII/RGMII)
- The only non-deprecated DT property of the three
- "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg
- Valid only in GMII/RGMII mode
- Deprecated property, backward compatibility only
- "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg
- Valid only in RMII mode
- Deprecated property, backward compatibility only
The stm32mp1_select_ethck_external() function handles the aforementioned
DT properties and sets dwmac->enable_eth_ck accordingly.
The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external()
first and then only use dwmac->enable_eth_ck to determine hardware clock mux
settings.
No functional change intended.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Christophe Roullier <[email protected]>
---
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 ++++++++++++++-----
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 2fd2620ebed69..767994061ea82 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -157,6 +157,37 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume)
return stm32_dwmac_clk_enable(dwmac, resume);
}
+static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat)
+{
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+
+ switch (plat_dat->mac_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ dwmac->enable_eth_ck = dwmac->ext_phyclk;
+ return 0;
+ case PHY_INTERFACE_MODE_GMII:
+ dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||
+ dwmac->ext_phyclk;
+ return 0;
+ case PHY_INTERFACE_MODE_RMII:
+ dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg ||
+ dwmac->ext_phyclk;
+ return 0;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||
+ dwmac->ext_phyclk;
+ return 0;
+ default:
+ dwmac->enable_eth_ck = false;
+ dev_err(dwmac->dev, "Mode %s not supported",
+ phy_modes(plat_dat->mac_interface));
+ return -EINVAL;
+ }
+}
+
static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
@@ -194,28 +225,25 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
u32 reg = dwmac->mode_reg;
int val, ret;
- dwmac->enable_eth_ck = false;
+ ret = stm32mp1_select_ethck_external(plat_dat);
+ if (ret)
+ return ret;
+
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
- if (dwmac->ext_phyclk)
- dwmac->enable_eth_ck = true;
val = SYSCFG_PMCR_ETH_SEL_MII;
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_GMII:
val = SYSCFG_PMCR_ETH_SEL_GMII;
- if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
- dwmac->enable_eth_ck = true;
+ if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_CLK_SEL;
- }
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
break;
case PHY_INTERFACE_MODE_RMII:
val = SYSCFG_PMCR_ETH_SEL_RMII;
- if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) {
- dwmac->enable_eth_ck = true;
+ if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
- }
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
break;
case PHY_INTERFACE_MODE_RGMII:
@@ -223,10 +251,8 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
val = SYSCFG_PMCR_ETH_SEL_RGMII;
- if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
- dwmac->enable_eth_ck = true;
+ if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_CLK_SEL;
- }
pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
break;
default:
--
2.25.1
From: Marek Vasut <[email protected]>
Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of
pr_debug() and hand-written PHY mode decoding. This way, each debug
print has associated device with it and duplicated mode decoding is
removed.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Christophe Roullier <[email protected]>
---
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index aa413edd1ef71..75981ac2cbb56 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -228,19 +228,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
val = SYSCFG_PMCR_ETH_SEL_MII;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_GMII:
val = SYSCFG_PMCR_ETH_SEL_GMII;
if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_CLK_SEL;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
break;
case PHY_INTERFACE_MODE_RMII:
val = SYSCFG_PMCR_ETH_SEL_RMII;
if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
@@ -249,15 +246,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
val = SYSCFG_PMCR_ETH_SEL_RGMII;
if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_CLK_SEL;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
break;
default:
- pr_debug("SYSCFG init : Do not manage %d interface\n",
- plat_dat->mac_interface);
+ dev_err(dwmac->dev, "Mode %s not supported",
+ phy_modes(plat_dat->mac_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+
/* Need to update PMCCLRR (clear register) */
regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
dwmac->ops->syscfg_eth_mask);
@@ -291,19 +289,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
val = SYSCFG_MCU_ETH_SEL_MII;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_RMII:
val = SYSCFG_MCU_ETH_SEL_RMII;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
break;
default:
- pr_debug("SYSCFG init : Do not manage %d interface\n",
- plat_dat->mac_interface);
+ dev_err(dwmac->dev, "Mode %s not supported",
+ phy_modes(plat_dat->mac_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+
return regmap_update_bits(dwmac->regmap, reg,
dwmac->ops->syscfg_eth_mask, val << 23);
}
--
2.25.1
Need to enable MCP23S08 I/O expanders to manage Ethernet PHY
reset in STM32MP135F-DK board.
Put this config in built-in like STMMAC to avoid huge of Ethernet
messages during boot (deferred)
Signed-off-by: Christophe Roullier <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 86bf057ac3663..9758f3d41ad70 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -469,6 +469,7 @@ CONFIG_SPI_XILINX=y
CONFIG_SPI_SPIDEV=y
CONFIG_SPMI=y
CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_MCP23S08=y
CONFIG_PINCTRL_MICROCHIP_SGPIO=y
CONFIG_PINCTRL_OCELOT=y
CONFIG_PINCTRL_PALMAS=y
--
2.25.1
On Tue, 04 Jun 2024 16:34:51 +0200, Christophe Roullier wrote:
> STM32MP13 is STM32 SOC with 2 GMACs instances
> GMAC IP version is SNPS 4.20.
> GMAC IP configure with 1 RX and 1 TX queue.
> DMA HW capability register supported
> RX Checksum Offload Engine supported
> TX Checksum insertion supported
> Wake-Up On Lan supported
> TSO supported
> Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
>
> V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
> Remark from Serge Semin (upate commits msg)
> V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
> manage PHY regulator (in glue or PHY side)
> - Integrate RFC from Marek
> - Remark from Rob Herring in YAML documentation
> V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg)
> - Remark from Rasmus (add sign-off, add base-commit)
> - Remark from Sai Krishna Gajula
>
> Christophe Roullier (6):
> dt-bindings: net: add STM32MP13 compatible in documentation for stm32
> net: ethernet: stmmac: add management of stm32mp13 for stm32
> ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
> ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
> ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
> ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
>
> Marek Vasut (5):
> net: stmmac: dwmac-stm32: Separate out external clock rate validation
> net: stmmac: dwmac-stm32: Separate out external clock selector
> net: stmmac: dwmac-stm32: Extract PMCR configuration
> net: stmmac: dwmac-stm32: Clean up the debug prints
> net: stmmac: dwmac-stm32: Fix Mhz to MHz
>
> .../devicetree/bindings/net/stm32-dwmac.yaml | 41 ++++-
> arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 ++++++++
> arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++
> arch/arm/boot/dts/st/stm32mp133.dtsi | 31 ++++
> arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++
> arch/arm/configs/multi_v7_defconfig | 1 +
> .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 172 ++++++++++++++----
> 7 files changed, 330 insertions(+), 47 deletions(-)
>
>
> base-commit: cd0057ad75116bacf16fea82e48c1db642971136
> --
> 2.25.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y st/stm32mp135f-dk.dtb' for [email protected]:
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: adc@48003000: 'ethernet@5800e000' does not match any of the regexes: '^adc@[0-9]+$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
On 6/4/24 17:29, Rob Herring (Arm) wrote:
> On Tue, 04 Jun 2024 16:34:51 +0200, Christophe Roullier wrote:
>> STM32MP13 is STM32 SOC with 2 GMACs instances
>> GMAC IP version is SNPS 4.20.
>> GMAC IP configure with 1 RX and 1 TX queue.
>> DMA HW capability register supported
>> RX Checksum Offload Engine supported
>> TX Checksum insertion supported
>> Wake-Up On Lan supported
>> TSO supported
>> Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
>>
>> V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
>> Remark from Serge Semin (upate commits msg)
>> V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
>> manage PHY regulator (in glue or PHY side)
>> - Integrate RFC from Marek
>> - Remark from Rob Herring in YAML documentation
>> V4: - Remark from Marek (remove max-speed, extra space in DT, update commit msg)
>> - Remark from Rasmus (add sign-off, add base-commit)
>> - Remark from Sai Krishna Gajula
>>
>> Christophe Roullier (6):
>> dt-bindings: net: add STM32MP13 compatible in documentation for stm32
>> net: ethernet: stmmac: add management of stm32mp13 for stm32
>> ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
>> ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
>> ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
>> ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
>>
>> Marek Vasut (5):
>> net: stmmac: dwmac-stm32: Separate out external clock rate validation
>> net: stmmac: dwmac-stm32: Separate out external clock selector
>> net: stmmac: dwmac-stm32: Extract PMCR configuration
>> net: stmmac: dwmac-stm32: Clean up the debug prints
>> net: stmmac: dwmac-stm32: Fix Mhz to MHz
>>
>> .../devicetree/bindings/net/stm32-dwmac.yaml | 41 ++++-
>> arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 ++++++++
>> arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++
>> arch/arm/boot/dts/st/stm32mp133.dtsi | 31 ++++
>> arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++
>> arch/arm/configs/multi_v7_defconfig | 1 +
>> .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 172 ++++++++++++++----
>> 7 files changed, 330 insertions(+), 47 deletions(-)
>>
>>
>> base-commit: cd0057ad75116bacf16fea82e48c1db642971136
>> --
>> 2.25.1
>>
>>
>>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
> pip3 install dtschema --upgrade
>
>
> New warnings running 'make CHECK_DTBS=y st/stm32mp135f-dk.dtb' for [email protected]:
>
> arch/arm/boot/dts/st/stm32mp135f-dk.dtb: adc@48003000: 'ethernet@5800e000' does not match any of the regexes: '^adc@[0-9]+$', 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
>
Hi Rob,
I will provide v5 to fix it.
Thanks
>
>
>
On 6/4/24 4:35 PM, Christophe Roullier wrote:
> Need to enable MCP23S08 I/O expanders to manage Ethernet PHY
> reset in STM32MP135F-DK board.
> Put this config in built-in like STMMAC to avoid huge of Ethernet
> messages during boot (deferred)
You're not avoiding any error/defer/messages here, you simply need to
enable the MCP23S08 GPIO controller driver, so the kernel can use the
GPIO provided by that driver instance to release the ethernet PHY from
reset on STM32MP135F-DK, that's all.