This patch series consist of six parts and covers the following:
1. Re-enable context caching for Qualcomm SoCs to retain prefetcher
settings during reset and runtime suspend.
2. Remove cfg inside qcom_smmu structure and replace it with single
pointer to qcom_smmu_match_data avoiding replication of multiple
members from same.
3. Introduce intital set of driver changes to implement ACTLR register
for custom prefetcher settings in Qualcomm SoCs.
4. Add ACTLR data and implementation operations for SM8550.
5. Add ACTLR data and implementation operations for SC7280.
6. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
Changes in v11 from v10:
- Include a new patch 6/6 to add support for ACTLR PRR bit
through adreno-smmu-priv interface as suggested by Rob and Dmitry.
Link to v10:
https://lore.kernel.org/all/[email protected]/
Changes in v10 from v9:
- Added reviewed-by tags 1/5,2/5,3/5.
Changes incorporated:
- Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
as this bit needs special handling in the gfx driver along with
the associated register settings.
Link to discussion on PRR bit:
https://lore.kernel.org/all/[email protected]/
Link to v9:
https://lore.kernel.org/all/[email protected]/
Changes in v9 from v8:
Changes to incorporate suggestions from Konrad as follows:
- Re-wrap struct members of actlr_variant in patch 4/5,5/5
in a cleaner way.
- Move actlr_config members to the header.
Link to v8:
https://lore.kernel.org/all/[email protected]/
Changes in v8 from v7:
- Added reviewed-by tags on patch 1/5, 2/5.
Changes to incorporate suggestions from Pavan and Konrad:
- Remove non necessary extra lines.
- Use num_smmu and num_actlrcfg to store the array size and use the
same to traverse the table and save on sentinel space along with
indentation levels.
- Refactor blocks containing qcom_smmu_set_actlr to remove block
repetition in patch 3/5.
- Change copyright year from 2023 to 2022-2023 in patch 3/5.
- Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
const pointer to a const resource.
- use C99 designated initializers and put the address first.
Link to v7:
https://lore.kernel.org/all/[email protected]/
Changes in v7 from v6:
Changes to incorporate suggestions from Dmitry as follows:
- Use io_start address instead of compatible string to identify the
correct instance by comparing with smmu start address and check for
which smmu the corresponding actlr table is to be picked.
Link to v6:
https://lore.kernel.org/all/[email protected]/
Changes in v6 from v5:
- Remove extra Suggested-by tags.
- Add return check for arm_mmu500_reset in 1/5 as discussed.
Link to v5:
https://lore.kernel.org/all/[email protected]/
Changes in v5 from v4:
New addition:
- Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
Changes to incorporate suggestions from Dmitry as follows:
- Modify the defines for prefetch in (foo << bar) format
as suggested.(FIELD_PREP could not be used in defines
is not inside any block/function)
Changes to incorporate suggestions from Konrad as follows:
- Shift context caching enablement patch as 1/5 instead of 5/5 to
be picked up as independent patch.
- Fix the codestyle to orient variables in reverse xmas tree format
for patch 1/5.
- Fix variable name in patch 1/5 as suggested.
Link to v4:
https://lore.kernel.org/all/[email protected]/
Changes in v4 from v3:
New addition:
- Remove actlrcfg_size and use NULL end element instead to traverse
the actlr table, as this would be a cleaner approach by removing
redundancy of actlrcfg_size.
- Renaming of actlr set function to arm_smmu_qcom based proprietary
convention.
- break from loop once sid is found and ACTLR value is initialized
in qcom_smmu_set_actlr.
- Modify the GFX prefetch value separating into 2 sensible defines.
- Modify comments for prefetch defines as per SMMU-500 TRM.
Changes to incorporate suggestions from Konrad as follows:
- Use Reverse-Christmas-tree sorting wherever applicable.
- Pass arguments directly to arm_smmu_set_actlr instead of creating
duplicate variables.
- Use array indexing instead of direct pointer addressed by new
addition of eliminating actlrcfg_size.
- Switch the HEX value's case from upper to lower case in SC7280
actlrcfg table.
Changes to incorporate suggestions from Dmitry as follows:
- Separate changes not related to ACTLR support to different commit
with patch 5/5.
- Using pointer to struct for arguments in smr_is_subset().
Changes to incorporate suggestions from Bjorn as follows:
- fix the commit message for patch 2/5 to properly document the
value space to avoid confusion.
Fixed build issues reported by kernel test robot [1] for
arm64-allyesconfig [2].
[1]: https://lore.kernel.org/all/[email protected]/
[2]:
https://download.01.org/0day-ci/archive/20231201/[email protected]/config
Link to v3:
https://lore.kernel.org/all/[email protected]/
Changes in v3 from v2:
New addition:
- Include patch 3/4 for adding ACTLR support and data for SC7280.
- Add driver changes for actlr support in gpu smmu.
- Add target wise actlr data and implementation ops for gpu smmu.
Changes to incorporate suggestions from Robin as follows:
- Match the ACTLR values with individual corresponding SID instead
of assuming that any SMR will be programmed to match a superset of
the data.
- Instead of replicating each elements from qcom_smmu_match_data to
qcom_smmu structre during smmu device creation, replace the
replicated members with qcom_smmu_match_data structure inside
qcom_smmu structre and handle the dereference in places that
requires them.
Changes to incorporate suggestions from Dmitry and Konrad as follows:
- Maintain actlr table inside a single structure instead of
nested structure.
- Rename prefetch defines to more appropriately describe their
behavior.
- Remove SM8550 specific implementation ops and roll back to default
qcom_smmu_500_impl implementation ops.
- Add back the removed comments which are NAK.
- Fix commit description for patch 4/4.
Link to v2:
https://lore.kernel.org/all/[email protected]/
Changes in v2 from v1:
- Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
- Added defines for ACTLR values.
- Linked sm8550 implementation structure to corresponding
compatible string.
- Repackaged actlr value set implementation to separate function.
- Fixed indentation errors.
- Link to v1:
https://lore.kernel.org/all/[email protected]/
Changes in v1 from RFC:
- Incorporated suggestion form Robin on RFC
- Moved the actlr data table into driver, instead of maintaining
it inside soc specific DT and piggybacking on exisiting iommus
property (iommu = <SID, MASK, ACTLR>) to set this value during
smmu probe.
- Link to RFC:
https://lore.kernel.org/all/[email protected]/
Bibek Kumar Patro (6):
iommu/arm-smmu: re-enable context caching in smmu reset operation
iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
iommu/arm-smmu: add ACTLR data and support for SM8550
iommu/arm-smmu: add ACTLR data and support for SC7280
iommu/arm-smmu: add support for PRR bit setup
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 244 +++++++++++++++++-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 18 +-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +-
drivers/iommu/arm/arm-smmu/arm-smmu.h | 7 +
include/linux/adreno-smmu-priv.h | 5 +-
6 files changed, 270 insertions(+), 11 deletions(-)
--
2.34.1
Add an adreno-smmu-priv interface for drm/msm to call
into arm-smmu-qcom and initiate the PRR bit setup or reset
sequence as per request.
This will be used by GPU side to setup the PRR bit and
related configuration registers through adreno-smmu private
interface instead of directly poking the smmu hardware.
Signed-off-by: Bibek Kumar Patro <[email protected]>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21 +++++++++++++++++++++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
include/linux/adreno-smmu-priv.h | 5 ++++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 8dabc26fa10e..2f4ee22f740a 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -28,6 +28,7 @@
#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT)
#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT)
#define PREFETCH_DEEP (3 << PREFETCH_SHIFT)
+#define GFX_ACTLR_PRR (1 << 5)
static const struct actlr_config sc7280_apps_actlr_cfg[] = {
{ 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
@@ -212,6 +213,25 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina
arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
}
+static void qcom_adreno_smmu_set_actlr_bit(const void *cookie, phys_addr_t page_addr, bool set)
+{
+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
+ struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+ u32 reg = 0;
+
+ writel_relaxed(lower_32_bits(page_addr),
+ (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
+
+ writel_relaxed(upper_32_bits(page_addr),
+ (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
+
+ reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
+ reg |= FIELD_PREP(GFX_ACTLR_PRR, set ? 1 : 0);
+ arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
+
+}
+
#define QCOM_ADRENO_SMMU_GPU_SID 0
static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
@@ -384,6 +404,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
priv->set_stall = qcom_adreno_smmu_set_stall;
priv->resume_translation = qcom_adreno_smmu_resume_translation;
+ priv->set_actlr_bit = qcom_adreno_smmu_set_actlr_bit;
actlrvar = qsmmu->data->actlrvar;
if (!actlrvar)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index d9c2ef8c1653..3076bef49e20 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -154,6 +154,8 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_SCTLR_M BIT(0)
#define ARM_SMMU_CB_ACTLR 0x4
+#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008
+#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C
#define ARM_SMMU_CB_RESUME 0x8
#define ARM_SMMU_RESUME_TERMINATE BIT(0)
diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
index c637e0997f6d..448e191eeb52 100644
--- a/include/linux/adreno-smmu-priv.h
+++ b/include/linux/adreno-smmu-priv.h
@@ -49,7 +49,9 @@ struct adreno_smmu_fault_info {
* before set_ttbr0_cfg(). If stalling on fault is enabled,
* the GPU driver must call resume_translation()
* @resume_translation: Resume translation after a fault
- *
+ * @set_actlr_bits: Extendible interface to be used by GPU to modify the
+ * ACTLR bits, currently used to intitate PRR bit setup or
+ * reset sequence for ACTLR registers as requested.
*
* The GPU driver (drm/msm) and adreno-smmu work together for controlling
* the GPU's SMMU instance. This is by necessity, as the GPU is directly
@@ -67,6 +69,7 @@ struct adreno_smmu_priv {
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
void (*set_stall)(const void *cookie, bool enabled);
void (*resume_translation)(const void *cookie, bool terminate);
+ void (*set_actlr_bit)(const void *cookie, phys_addr_t page_addr, bool set);
};
#endif /* __ADRENO_SMMU_PRIV_H */
--
2.34.1
qcom_smmu_match_data is static and constant so refactor qcom_smmu
to store single pointer to qcom_smmu_match_data instead of
replicating multiple child members of the same and handle the further
dereferences in the places that want them.
Suggested-by: Robin Murphy <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Bibek Kumar Patro <[email protected]>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 552199cbd9e2..885af324916b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -73,7 +73,7 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
if (__ratelimit(&rs)) {
dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n");
- cfg = qsmmu->cfg;
+ cfg = qsmmu->data->cfg;
if (!cfg)
return;
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 76db4c8d1a9b..573c4c9886f1 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -506,7 +506,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
return ERR_PTR(-ENOMEM);
qsmmu->smmu.impl = impl;
- qsmmu->cfg = data->cfg;
+ qsmmu->data = data;
return &qsmmu->smmu;
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 9bb3ae7d62da..addc07623c0b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -8,7 +8,7 @@
struct qcom_smmu {
struct arm_smmu_device smmu;
- const struct qcom_smmu_config *cfg;
+ const struct qcom_smmu_match_data *data;
bool bypass_quirk;
u8 bypass_cbndx;
u32 stall_enabled;
--
2.34.1
Currently in Qualcomm SoCs the default prefetch is set to 1 which allows
the TLB to fetch just the next page table. MMU-500 features ACTLR
register which is implementation defined and is used for Qualcomm SoCs
to have a custom prefetch setting enabling TLB to prefetch the next set
of page tables accordingly allowing for faster translations.
ACTLR value is unique for each SMR (Stream matching register) and stored
in a pre-populated table. This value is set to the register during
context bank initialisation.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Bibek Kumar Patro <[email protected]>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 61 ++++++++++++++++++++++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 16 +++++-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +-
drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 ++
4 files changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 573c4c9886f1..77c9abffe07d 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -215,10 +215,42 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
return true;
}
+static void qcom_smmu_set_actlr(struct device *dev, struct arm_smmu_device *smmu, int cbndx,
+ const struct actlr_config *actlrcfg, const size_t num_actlrcfg)
+{
+ struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ struct arm_smmu_smr *smr;
+ u16 mask;
+ int idx;
+ u16 id;
+ int i;
+ int j;
+
+ for (i = 0; i < num_actlrcfg; i++) {
+ id = actlrcfg[i].sid;
+ mask = actlrcfg[i].mask;
+
+ for_each_cfg_sme(cfg, fwspec, j, idx) {
+ smr = &smmu->smrs[idx];
+ if (smr_is_subset(smr, id, mask)) {
+ arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR,
+ actlrcfg[i].actlr);
+ break;
+ }
+ }
+ }
+}
+
static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+ struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+ const struct actlr_variant *actlrvar;
+ int cbndx = smmu_domain->cfg.cbndx;
struct adreno_smmu_priv *priv;
+ int i;
smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
@@ -248,6 +280,18 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
priv->set_stall = qcom_adreno_smmu_set_stall;
priv->resume_translation = qcom_adreno_smmu_resume_translation;
+ actlrvar = qsmmu->data->actlrvar;
+ if (!actlrvar)
+ return 0;
+
+ for (i = 0; i < qsmmu->data->num_smmu ; i++) {
+ if (actlrvar[i].io_start == smmu->ioaddr) {
+ qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar[i].actlrcfg,
+ actlrvar[i].num_actlrcfg);
+ break;
+ }
+ }
+
return 0;
}
@@ -277,7 +321,24 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+ struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+ const struct actlr_variant *actlrvar;
+ int cbndx = smmu_domain->cfg.cbndx;
+ int i;
+
smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
+ actlrvar = qsmmu->data->actlrvar;
+ if (!actlrvar)
+ return 0;
+
+ for (i = 0; i < qsmmu->data->num_smmu ; i++) {
+ if (actlrvar[i].io_start == smmu->ioaddr) {
+ qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar[i].actlrcfg,
+ actlrvar[i].num_actlrcfg);
+ break;
+ }
+ }
return 0;
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index addc07623c0b..c51817ff4674 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _ARM_SMMU_QCOM_H
@@ -24,8 +24,22 @@ struct qcom_smmu_config {
const u32 *reg_offset;
};
+struct actlr_config {
+ u16 sid;
+ u16 mask;
+ u32 actlr;
+};
+
+struct actlr_variant {
+ const resource_size_t io_start;
+ const struct actlr_config * const actlrcfg;
+ const size_t num_actlrcfg;
+};
+
struct qcom_smmu_match_data {
+ const struct actlr_variant * const actlrvar;
const struct qcom_smmu_config *cfg;
+ const size_t num_smmu;
const struct arm_smmu_impl *impl;
const struct arm_smmu_impl *adreno_impl;
};
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 87c81f75cf84..f43d417bf7f6 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -1003,9 +1003,10 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
* expect simply identical entries for this case, but there's
* no harm in accommodating the generalisation.
*/
- if ((mask & smrs[i].mask) == mask &&
- !((id ^ smrs[i].id) & ~smrs[i].mask))
+
+ if (smr_is_subset(&smrs[i], id, mask))
return i;
+
/*
* If the new entry has any other overlap with an existing one,
* though, then there always exists at least one stream ID
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 4765c6945c34..d9c2ef8c1653 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -503,6 +503,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);
}
+static inline bool smr_is_subset(struct arm_smmu_smr *smrs, u16 id, u16 mask)
+{
+ return (mask & smrs->mask) == mask && !((id ^ smrs->id) & ~smrs->mask);
+}
+
#define ARM_SMMU_GR0 0
#define ARM_SMMU_GR1 1
#define ARM_SMMU_CB(s, n) ((s)->numpage + (n))
--
2.34.1
Default MMU-500 reset operation disables context caching in
prefetch buffer. It is however expected for context banks using
the ACTLR register to retain their prefetch value during reset
and runtime suspend.
Replace default MMU-500 reset operation with Qualcomm specific reset
operation which envelope the default reset operation and re-enables
context caching in prefetch buffer for Qualcomm SoCs.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bibek Kumar Patro <[email protected]>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 36 ++++++++++++++++++++--
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 25f034677f56..76db4c8d1a9b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -14,6 +14,16 @@
#define QCOM_DUMMY_VAL -1
+/*
+ * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
+ * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
+ * buffer). The remaining bits are implementation defined and vary across
+ * SoCs.
+ */
+
+#define CPRE (1 << 1)
+#define CMTLB (1 << 0)
+
static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
return container_of(smmu, struct qcom_smmu, smmu);
@@ -379,11 +389,31 @@ static int qcom_smmu_def_domain_type(struct device *dev)
return match ? IOMMU_DOMAIN_IDENTITY : 0;
}
+static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
+{
+ int ret;
+ u32 val;
+ int i;
+
+ ret = arm_mmu500_reset(smmu);
+ if (ret)
+ return ret;
+
+ /* arm_mmu500_reset() disables CPRE which is re-enabled here */
+ for (i = 0; i < smmu->num_context_banks; ++i) {
+ val = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+ val |= CPRE;
+ arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, val);
+ }
+
+ return 0;
+}
+
static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
{
int ret;
- arm_mmu500_reset(smmu);
+ qcom_smmu500_reset(smmu);
/*
* To address performance degradation in non-real time clients,
@@ -410,7 +440,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = {
.init_context = qcom_smmu_init_context,
.cfg_probe = qcom_smmu_cfg_probe,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = arm_mmu500_reset,
+ .reset = qcom_smmu500_reset,
.write_s2cr = qcom_smmu_write_s2cr,
.tlb_sync = qcom_smmu_tlb_sync,
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
@@ -443,7 +473,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
.init_context = qcom_adreno_smmu_init_context,
.def_domain_type = qcom_smmu_def_domain_type,
- .reset = arm_mmu500_reset,
+ .reset = qcom_smmu500_reset,
.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
.write_sctlr = qcom_adreno_smmu_write_sctlr,
.tlb_sync = qcom_smmu_tlb_sync,
--
2.34.1
On Wed, Jun 5, 2024 at 5:18 AM Bibek Kumar Patro
<[email protected]> wrote:
>
> Add an adreno-smmu-priv interface for drm/msm to call
> into arm-smmu-qcom and initiate the PRR bit setup or reset
> sequence as per request.
>
> This will be used by GPU side to setup the PRR bit and
> related configuration registers through adreno-smmu private
> interface instead of directly poking the smmu hardware.
>
> Signed-off-by: Bibek Kumar Patro <[email protected]>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21 +++++++++++++++++++++
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
> include/linux/adreno-smmu-priv.h | 5 ++++-
> 3 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 8dabc26fa10e..2f4ee22f740a 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -28,6 +28,7 @@
> #define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT)
> #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT)
> #define PREFETCH_DEEP (3 << PREFETCH_SHIFT)
> +#define GFX_ACTLR_PRR (1 << 5)
>
> static const struct actlr_config sc7280_apps_actlr_cfg[] = {
> { 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
> @@ -212,6 +213,25 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina
> arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
> }
>
> +static void qcom_adreno_smmu_set_actlr_bit(const void *cookie, phys_addr_t page_addr, bool set)
> +{
_set_actlr_bit() is a bit more of an implementation detail. Maybe
_set_prr() would be a better name?
Also, the version of this patch that I typed up (but haven't sent to
list yet) took a `struct page *` instead of a phys_addr_t.. passing
NULL would disable PRR, so I didn't need the third arg
> + struct arm_smmu_domain *smmu_domain = (void *)cookie;
> + struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
> + struct arm_smmu_device *smmu = smmu_domain->smmu;
> + u32 reg = 0;
> +
> + writel_relaxed(lower_32_bits(page_addr),
> + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
> +
> + writel_relaxed(upper_32_bits(page_addr),
> + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
I know downstream writes it as upper+lower, but I'd guess we could
just writeq, couldn't we?
> +
> + reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
> + reg |= FIELD_PREP(GFX_ACTLR_PRR, set ? 1 : 0);
this won't clear the ENABLE_PRR bit if we try to disable it after
enabling (unless this bit is read-as-zero
Also, can we give a name to PRR? I'm guessing it is something like
physical-range-remap?
BR,
-R
> + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
> +
> +}
> +
> #define QCOM_ADRENO_SMMU_GPU_SID 0
>
> static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
> @@ -384,6 +404,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
> priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
> priv->set_stall = qcom_adreno_smmu_set_stall;
> priv->resume_translation = qcom_adreno_smmu_resume_translation;
> + priv->set_actlr_bit = qcom_adreno_smmu_set_actlr_bit;
>
> actlrvar = qsmmu->data->actlrvar;
> if (!actlrvar)
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index d9c2ef8c1653..3076bef49e20 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_SCTLR_M BIT(0)
>
> #define ARM_SMMU_CB_ACTLR 0x4
> +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008
> +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C
>
> #define ARM_SMMU_CB_RESUME 0x8
> #define ARM_SMMU_RESUME_TERMINATE BIT(0)
> diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
> index c637e0997f6d..448e191eeb52 100644
> --- a/include/linux/adreno-smmu-priv.h
> +++ b/include/linux/adreno-smmu-priv.h
> @@ -49,7 +49,9 @@ struct adreno_smmu_fault_info {
> * before set_ttbr0_cfg(). If stalling on fault is enabled,
> * the GPU driver must call resume_translation()
> * @resume_translation: Resume translation after a fault
> - *
> + * @set_actlr_bits: Extendible interface to be used by GPU to modify the
> + * ACTLR bits, currently used to intitate PRR bit setup or
> + * reset sequence for ACTLR registers as requested.
> *
> * The GPU driver (drm/msm) and adreno-smmu work together for controlling
> * the GPU's SMMU instance. This is by necessity, as the GPU is directly
> @@ -67,6 +69,7 @@ struct adreno_smmu_priv {
> void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
> void (*set_stall)(const void *cookie, bool enabled);
> void (*resume_translation)(const void *cookie, bool terminate);
> + void (*set_actlr_bit)(const void *cookie, phys_addr_t page_addr, bool set);
> };
>
> #endif /* __ADRENO_SMMU_PRIV_H */
> --
> 2.34.1
>
On 6/12/2024 12:32 AM, Rob Clark wrote:
> On Wed, Jun 5, 2024 at 5:18 AM Bibek Kumar Patro
> <[email protected]> wrote:
>>
>> Add an adreno-smmu-priv interface for drm/msm to call
>> into arm-smmu-qcom and initiate the PRR bit setup or reset
>> sequence as per request.
>>
>> This will be used by GPU side to setup the PRR bit and
>> related configuration registers through adreno-smmu private
>> interface instead of directly poking the smmu hardware.
>>
>> Signed-off-by: Bibek Kumar Patro <[email protected]>
>> ---
>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21 +++++++++++++++++++++
>> drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
>> include/linux/adreno-smmu-priv.h | 5 ++++-
>> 3 files changed, 27 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> index 8dabc26fa10e..2f4ee22f740a 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> @@ -28,6 +28,7 @@
>> #define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT)
>> #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT)
>> #define PREFETCH_DEEP (3 << PREFETCH_SHIFT)
>> +#define GFX_ACTLR_PRR (1 << 5)
>>
>> static const struct actlr_config sc7280_apps_actlr_cfg[] = {
>> { 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
>> @@ -212,6 +213,25 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina
>> arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
>> }
>>
>> +static void qcom_adreno_smmu_set_actlr_bit(const void *cookie, phys_addr_t page_addr, bool set)
>> +{
>
> _set_actlr_bit() is a bit more of an implementation detail. Maybe
> _set_prr() would be a better name?
>
Yes set_prr sounds more explanatory. Infact Initially planned to name it
as set_actlr_prr() but later changed it to set_actlr_bit() so to keep
this interface extendible.
Incase if gfx driver in future wants to control some other ACTLR bit as
well along with PRR bit, then we can extend this same interface to
handle other bits.
So any additional adreno-smmu-priv interface would note be needed, and
set_actlr_bit can itself be used for gfx handling of all required ACTLR
bits.
I think we can name it set_actlr_prr() for now, and later can change the
name incase we extend it. What's your thought on this?
> Also, the version of this patch that I typed up (but haven't sent to
> list yet) took a `struct page *` instead of a phys_addr_t.. passing
> NULL would disable PRR, so I didn't need the third arg
>
>> + struct arm_smmu_domain *smmu_domain = (void *)cookie;
>> + struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
>> + struct arm_smmu_device *smmu = smmu_domain->smmu;
>> + u32 reg = 0;
>> +
>> + writel_relaxed(lower_32_bits(page_addr),
>> + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
>> +
>> + writel_relaxed(upper_32_bits(page_addr),
>> + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
>
> I know downstream writes it as upper+lower, but I'd guess we could
> just writeq, couldn't we?
>
Actually ARM_SMMU_GFX_PRR_CFG_LADDR, ARM_SMMU_GFX_PRR_CFG_UADDR both are
separate 32 bit registers. So I think writeq for 64bit write might not
work, as these are not 64 bit registers nor these two are separated by
64 aligned address.
>> +
>> + reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
>> + reg |= FIELD_PREP(GFX_ACTLR_PRR, set ? 1 : 0);
>
> this won't clear the ENABLE_PRR bit if we try to disable it after
> enabling (unless this bit is read-as-zero
>
Ah okay right, got it. Thanks for pointing this out.
Will take care of this in next version.
will use set/reset in side if() instead with different
bitwise ops for set and reset.
> Also, can we give a name to PRR? I'm guessing it is something like
> physical-range-remap?
Yes sure. I checked on this, PRR here actually stands for
partially-resident-region.
So would be better If we add expansion for PRR in a comment ?
Because if we expand PRR in variables/defines then wouldn't
the names become too long?
Thanks & regards,
Bibek
>
> BR,
> -R
>
>> + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
>> +
>> +}
>> +
>> #define QCOM_ADRENO_SMMU_GPU_SID 0
>>
>> static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
>> @@ -384,6 +404,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>> priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
>> priv->set_stall = qcom_adreno_smmu_set_stall;
>> priv->resume_translation = qcom_adreno_smmu_resume_translation;
>> + priv->set_actlr_bit = qcom_adreno_smmu_set_actlr_bit;
>>
>> actlrvar = qsmmu->data->actlrvar;
>> if (!actlrvar)
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> index d9c2ef8c1653..3076bef49e20 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type {
>> #define ARM_SMMU_SCTLR_M BIT(0)
>>
>> #define ARM_SMMU_CB_ACTLR 0x4
>> +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008
>> +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C
>>
>> #define ARM_SMMU_CB_RESUME 0x8
>> #define ARM_SMMU_RESUME_TERMINATE BIT(0)
>> diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
>> index c637e0997f6d..448e191eeb52 100644
>> --- a/include/linux/adreno-smmu-priv.h
>> +++ b/include/linux/adreno-smmu-priv.h
>> @@ -49,7 +49,9 @@ struct adreno_smmu_fault_info {
>> * before set_ttbr0_cfg(). If stalling on fault is enabled,
>> * the GPU driver must call resume_translation()
>> * @resume_translation: Resume translation after a fault
>> - *
>> + * @set_actlr_bits: Extendible interface to be used by GPU to modify the
>> + * ACTLR bits, currently used to intitate PRR bit setup or
>> + * reset sequence for ACTLR registers as requested.
>> *
>> * The GPU driver (drm/msm) and adreno-smmu work together for controlling
>> * the GPU's SMMU instance. This is by necessity, as the GPU is directly
>> @@ -67,6 +69,7 @@ struct adreno_smmu_priv {
>> void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
>> void (*set_stall)(const void *cookie, bool enabled);
>> void (*resume_translation)(const void *cookie, bool terminate);
>> + void (*set_actlr_bit)(const void *cookie, phys_addr_t page_addr, bool set);
>> };
>>
>> #endif /* __ADRENO_SMMU_PRIV_H */
>> --
>> 2.34.1
>>