Similar to
commit 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage")
this drops CLK_NR_CLKS usage from the clock driver and instead uses the
rockchip_clk_find_max_clk_id helper which was introduced for that purpose.
Signed-off-by: Alex Bee <[email protected]>
---
drivers/clk/rockchip/clk-rk3128.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index d076b7971f33..40e0e4556d59 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -569,18 +569,22 @@ static const char *const rk3128_critical_clocks[] __initconst = {
"sclk_timer5",
};
-static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
+static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np,
+ unsigned long soc_nr_clks)
{
struct rockchip_clk_provider *ctx;
+ unsigned long common_nr_clks;
void __iomem *reg_base;
+ common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches,
+ ARRAY_SIZE(common_clk_branches)) + 1;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return ERR_PTR(-ENOMEM);
}
- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks));
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
@@ -609,8 +613,12 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
static void __init rk3126_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long soc_nr_clks;
- ctx = rk3128_common_clk_init(np);
+ soc_nr_clks = rockchip_clk_find_max_clk_id(rk3126_clk_branches,
+ ARRAY_SIZE(rk3126_clk_branches)) + 1;
+
+ ctx = rk3128_common_clk_init(np, soc_nr_clks);
if (IS_ERR(ctx))
return;
@@ -627,8 +635,12 @@ CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
static void __init rk3128_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long soc_nr_clks;
+
+ soc_nr_clks = rockchip_clk_find_max_clk_id(rk3128_clk_branches,
+ ARRAY_SIZE(rk3128_clk_branches)) + 1;
- ctx = rk3128_common_clk_init(np);
+ ctx = rk3128_common_clk_init(np, soc_nr_clks);
if (IS_ERR(ctx))
return;
--
2.45.2
CLK_NR_CLKS should not be part of the binding. Let's drop it, since
the kernel code no longer uses it either.
Signed-off-by: Alex Bee <[email protected]>
---
include/dt-bindings/clock/rk3128-cru.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 1be455ba4985..420984fc2285 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -145,7 +145,6 @@
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
-#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
--
2.45.2
Add a clock id for SFC's AHB clock.
Signed-off-by: Alex Bee <[email protected]>
---
include/dt-bindings/clock/rk3128-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 420984fc2285..d731c3ffbe1e 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -144,6 +144,7 @@
#define HCLK_TSP 475
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
+#define HCLK_SFC 479
/* soft-reset indices */
--
2.45.2
The SFC IP exists only in RK3128 version of the SoC, thus the clock gets
added to rk3128_clk_branches.
Signed-off-by: Alex Bee <[email protected]>
---
drivers/clk/rockchip/clk-rk3128.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 40e0e4556d59..7c3d92af12df 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -553,6 +553,7 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
};
--
2.45.2
Add the Serial Flash Controller and it's pincontrols.
Signed-off-by: Alex Bee <[email protected]>
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index a7ab0904564f..22e2a35dedb1 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -399,6 +399,15 @@ usb_host_ohci: usb@101e0000 {
status = "disabled";
};
+ sfc: spi@1020c000 {
+ compatible = "rockchip,sfc";
+ reg = <0x1020c000 0x8000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ status = "disabled";
+ };
+
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -1155,6 +1164,32 @@ sdmmc_bus4: sdmmc-bus4 {
};
};
+ sfc {
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>;
+ };
+
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>,
+ <1 RK_PD2 3 &pcfg_pull_default>,
+ <1 RK_PD3 3 &pcfg_pull_default>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins = <2 RK_PA2 3 &pcfg_pull_default>;
+ };
+
+ sfc_cs1: sfc-cs1 {
+ rockchip,pins = <2 RK_PA3 3 &pcfg_pull_default>;
+ };
+ };
+
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
--
2.45.2
This series adds support for the Serial Flash Controller (SFC) found in
RK3128 SoCs.
As without using some "id holes" we would run out clock ids in the binding
and would have to touch the ABI, I added patches which removes the
CLK_NR_CLKS macro and uses the recently introduced
rockchip_clk_find_max_clk_id helper instead to find the highest clock id.
changes since v1:
- added patches to remove CLK_NR_CLKS (Connor)
Link to v1:
https://lore.kernel.org/all/[email protected]/
Alex Bee (5):
clk: rockchip: rk3128: Drop CLK_NR_CLKS usage
dt-bindings: clock: rk3128: Drop CLK_NR_CLKS
dt-bindings: clock: rk3128: Add HCLK_SFC
clk: rockchip: Add HCLK_SFC for RK3128
ARM: dts: rockchip: Add SFC for RK3128
arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
drivers/clk/rockchip/clk-rk3128.c | 21 +++++++++++++---
include/dt-bindings/clock/rk3128-cru.h | 2 +-
3 files changed, 53 insertions(+), 5 deletions(-)
base-commit: 234cb065ad82915ff8d06ce01e01c3e640b674d2
--
2.45.2
In order to get rid of CLK_NR_CLKS and be able to drop it from the
bindings, use rockchip_clk_find_max_clk_id helper to find the highest
clock id.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- new patch
drivers/clk/rockchip/clk-rk3128.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index d076b7971f33..40e0e4556d59 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -569,18 +569,22 @@ static const char *const rk3128_critical_clocks[] __initconst = {
"sclk_timer5",
};
-static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
+static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np,
+ unsigned long soc_nr_clks)
{
struct rockchip_clk_provider *ctx;
+ unsigned long common_nr_clks;
void __iomem *reg_base;
+ common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches,
+ ARRAY_SIZE(common_clk_branches)) + 1;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return ERR_PTR(-ENOMEM);
}
- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks));
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
@@ -609,8 +613,12 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
static void __init rk3126_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long soc_nr_clks;
- ctx = rk3128_common_clk_init(np);
+ soc_nr_clks = rockchip_clk_find_max_clk_id(rk3126_clk_branches,
+ ARRAY_SIZE(rk3126_clk_branches)) + 1;
+
+ ctx = rk3128_common_clk_init(np, soc_nr_clks);
if (IS_ERR(ctx))
return;
@@ -627,8 +635,12 @@ CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
static void __init rk3128_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long soc_nr_clks;
+
+ soc_nr_clks = rockchip_clk_find_max_clk_id(rk3128_clk_branches,
+ ARRAY_SIZE(rk3128_clk_branches)) + 1;
- ctx = rk3128_common_clk_init(np);
+ ctx = rk3128_common_clk_init(np, soc_nr_clks);
if (IS_ERR(ctx))
return;
--
2.45.2
CLK_NR_CLKS should not be part of the binding. Let's drop it, since
the kernel code no longer uses it either.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- new patch
include/dt-bindings/clock/rk3128-cru.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 1be455ba4985..420984fc2285 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -145,7 +145,6 @@
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
-#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
--
2.45.2
Add a clock id for SFC's AHB clock.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- add new clock id at the end
include/dt-bindings/clock/rk3128-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 420984fc2285..d731c3ffbe1e 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -144,6 +144,7 @@
#define HCLK_TSP 475
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
+#define HCLK_SFC 479
/* soft-reset indices */
--
2.45.2
The SFC IP exists only in RK3128 version of the SoC, thus the clock gets
added to rk3128_clk_branches.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- none
drivers/clk/rockchip/clk-rk3128.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 40e0e4556d59..7c3d92af12df 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -553,6 +553,7 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
};
--
2.45.2
Add the Serial Flash Controller and it's pincontrols.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- none
arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index a7ab0904564f..22e2a35dedb1 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -399,6 +399,15 @@ usb_host_ohci: usb@101e0000 {
status = "disabled";
};
+ sfc: spi@1020c000 {
+ compatible = "rockchip,sfc";
+ reg = <0x1020c000 0x8000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ status = "disabled";
+ };
+
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -1155,6 +1164,32 @@ sdmmc_bus4: sdmmc-bus4 {
};
};
+ sfc {
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>;
+ };
+
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>,
+ <1 RK_PD2 3 &pcfg_pull_default>,
+ <1 RK_PD3 3 &pcfg_pull_default>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins = <2 RK_PA2 3 &pcfg_pull_default>;
+ };
+
+ sfc_cs1: sfc-cs1 {
+ rockchip,pins = <2 RK_PA3 3 &pcfg_pull_default>;
+ };
+ };
+
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
--
2.45.2
Hi,
sorry for the noise - not sure what went wrong here.
Just resend v2:
https://lore.kernel.org/all/[email protected]/
Alex
Am 05.06.24 um 22:51 schrieb Alex Bee:
> Similar to
> commit 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage")
> this drops CLK_NR_CLKS usage from the clock driver and instead uses the
> rockchip_clk_find_max_clk_id helper which was introduced for that purpose.
>
> Signed-off-by: Alex Bee <[email protected]>
> ---
> drivers/clk/rockchip/clk-rk3128.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
> index d076b7971f33..40e0e4556d59 100644
> --- a/drivers/clk/rockchip/clk-rk3128.c
> +++ b/drivers/clk/rockchip/clk-rk3128.c
> @@ -569,18 +569,22 @@ static const char *const rk3128_critical_clocks[] __initconst = {
> "sclk_timer5",
> };
>
> -static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
> +static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np,
> + unsigned long soc_nr_clks)
> {
> struct rockchip_clk_provider *ctx;
> + unsigned long common_nr_clks;
> void __iomem *reg_base;
>
> + common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches,
> + ARRAY_SIZE(common_clk_branches)) + 1;
> reg_base = of_iomap(np, 0);
> if (!reg_base) {
> pr_err("%s: could not map cru region\n", __func__);
> return ERR_PTR(-ENOMEM);
> }
>
> - ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
> + ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks));
> if (IS_ERR(ctx)) {
> pr_err("%s: rockchip clk init failed\n", __func__);
> iounmap(reg_base);
> @@ -609,8 +613,12 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
> static void __init rk3126_clk_init(struct device_node *np)
> {
> struct rockchip_clk_provider *ctx;
> + unsigned long soc_nr_clks;
>
> - ctx = rk3128_common_clk_init(np);
> + soc_nr_clks = rockchip_clk_find_max_clk_id(rk3126_clk_branches,
> + ARRAY_SIZE(rk3126_clk_branches)) + 1;
> +
> + ctx = rk3128_common_clk_init(np, soc_nr_clks);
> if (IS_ERR(ctx))
> return;
>
> @@ -627,8 +635,12 @@ CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
> static void __init rk3128_clk_init(struct device_node *np)
> {
> struct rockchip_clk_provider *ctx;
> + unsigned long soc_nr_clks;
> +
> + soc_nr_clks = rockchip_clk_find_max_clk_id(rk3128_clk_branches,
> + ARRAY_SIZE(rk3128_clk_branches)) + 1;
>
> - ctx = rk3128_common_clk_init(np);
> + ctx = rk3128_common_clk_init(np, soc_nr_clks);
> if (IS_ERR(ctx))
> return;
>
On 05/06/2024 22:52, Alex Bee wrote:
> Add a clock id for SFC's AHB clock.
>
> Signed-off-by: Alex Bee <[email protected]>
> ---
> include/dt-bindings/clock/rk3128-cru.h | 1 +
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 05/06/2024 22:52, Alex Bee wrote:
> This series adds support for the Serial Flash Controller (SFC) found in
> RK3128 SoCs.
>
> As without using some "id holes" we would run out clock ids in the binding
> and would have to touch the ABI, I added patches which removes the
> CLK_NR_CLKS macro and uses the recently introduced
> rockchip_clk_find_max_clk_id helper instead to find the highest clock id.
>
> changes since v1:
> - added patches to remove CLK_NR_CLKS (Connor)
>
Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.
You sent now v2 immediately after. Confused.
Best regards,
Krzysztof
On 05/06/2024 22:52, Alex Bee wrote:
> CLK_NR_CLKS should not be part of the binding. Let's drop it, since
> the kernel code no longer uses it either.
>
> Signed-off-by: Alex Bee <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Am Donnerstag, 6. Juni 2024, 08:41:19 CEST schrieb Krzysztof Kozlowski:
> On 05/06/2024 22:52, Alex Bee wrote:
> > This series adds support for the Serial Flash Controller (SFC) found in
> > RK3128 SoCs.
> >
> > As without using some "id holes" we would run out clock ids in the binding
> > and would have to touch the ABI, I added patches which removes the
> > CLK_NR_CLKS macro and uses the recently introduced
> > rockchip_clk_find_max_clk_id helper instead to find the highest clock id.
> >
> > changes since v1:
> > - added patches to remove CLK_NR_CLKS (Connor)
> >
>
> Do not attach (thread) your patchsets to some other threads (unrelated
> or older versions). This buries them deep in the mailbox and might
> interfere with applying entire sets.
>
> You sent now v2 immediately after. Confused.
it looks like Alex had some mail trouble yesterday.
The thread you Acked patches in actually is v2, just missing the label.
- original v1: https://lore.kernel.org/linux-rockchip/[email protected]
- "unlabeled" v2: https://lore.kernel.org/linux-rockchip/[email protected]/
- this as v2, but as reply to the previous
- real v2: https://lore.kernel.org/linux-rockchip/[email protected]/
The last 3 are identical, just the sending process was somehow fumbled.
Hi Heiko, Hi Krzysztof,
Am 06.06.24 um 09:37 schrieb Heiko Stübner:
> Am Donnerstag, 6. Juni 2024, 08:41:19 CEST schrieb Krzysztof Kozlowski:
>> On 05/06/2024 22:52, Alex Bee wrote:
>>> This series adds support for the Serial Flash Controller (SFC) found in
>>> RK3128 SoCs.
>>>
>>> As without using some "id holes" we would run out clock ids in the binding
>>> and would have to touch the ABI, I added patches which removes the
>>> CLK_NR_CLKS macro and uses the recently introduced
>>> rockchip_clk_find_max_clk_id helper instead to find the highest clock id.
>>>
>>> changes since v1:
>>> - added patches to remove CLK_NR_CLKS (Connor)
>>>
>> Do not attach (thread) your patchsets to some other threads (unrelated
>> or older versions). This buries them deep in the mailbox and might
>> interfere with applying entire sets.
>>
>> You sent now v2 immediately after. Confused.
> it looks like Alex had some mail trouble yesterday.
>
> The thread you Acked patches in actually is v2, just missing the label.
>
> - original v1: https://lore.kernel.org/linux-rockchip/[email protected]
>
> - "unlabeled" v2: https://lore.kernel.org/linux-rockchip/[email protected]/
> - this as v2, but as reply to the previous
> - real v2: https://lore.kernel.org/linux-rockchip/[email protected]/
>
> The last 3 are identical, just the sending process was somehow fumbled.
Yes, that's why I replied to the first message in the messed-up thread
explaining it a bit:
https://lore.kernel.org/all/[email protected]/
Anyway: To make it a bit less confusing, I'll send v3 with Krzysztof's acks
included.
Alex
>
>