This series adds support for the Serial Flash Controller (SFC) found in
RK3128 SoCs. The existing driver can be used as-is.
As without using some "id holes" we would run out clock ids when adding the
additional SFC AHB clock in the binding and would have to touch the ABI, I
added patches which remove the CLK_NR_CLKS macro and use the recently
introduced rockchip_clk_find_max_clk_id helper instead to find the highest
clock id.
changes since v1:
- added patches to remove CLK_NR_CLKS (Conor)
Link to v1:
https://lore.kernel.org/all/[email protected]/
changes since v2:
- collect acks for the dt-bindings patches
- fixed pinmux settings for chipselect pincontrols
Link to (the messed version of) v2:
https://lore.kernel.org/all/[email protected]/
Alex Bee (5):
clk: rockchip: rk3128: Drop CLK_NR_CLKS usage
dt-bindings: clock: rk3128: Drop CLK_NR_CLKS
dt-bindings: clock: rk3128: Add HCLK_SFC
clk: rockchip: Add HCLK_SFC for RK3128
ARM: dts: rockchip: Add SFC for RK3128
arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
drivers/clk/rockchip/clk-rk3128.c | 21 +++++++++++++---
include/dt-bindings/clock/rk3128-cru.h | 3 +--
3 files changed, 53 insertions(+), 6 deletions(-)
base-commit: 234cb065ad82915ff8d06ce01e01c3e640b674d2
--
2.45.2
CLK_NR_CLKS should not be part of the binding. Let's drop it, since
the kernel code no longer uses it either.
Signed-off-by: Alex Bee <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
changes since v1:
- new patch
include/dt-bindings/clock/rk3128-cru.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 1be455ba4985..2616a8791c14 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -145,8 +145,6 @@
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
--
2.45.2
The SFC IP exists only in RK3128 version of the SoC, thus the clock gets
added to rk3128_clk_branches.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- none
drivers/clk/rockchip/clk-rk3128.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 40e0e4556d59..7c3d92af12df 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -553,6 +553,7 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
};
--
2.45.2
Add the Serial Flash Controller and it's pincontrols.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v2:
Fixed pinux settings for the chipselect pincontrols which originated from
contradictory documentation: Datasheet [0] (page 29/31) says it is func4
(when start counting with func1), while TRM [1] (page 185) says func3
(register value 0x2). It turned out TRM is correct as with setting cs
pincontrols to func4 the spi chip is not detected, while func3 is fine.
[0] https://www.armdesigner.com/download/Rockchip_RK3128_datasheet_V1.2.pdf,
[1] https://www.t-firefly.com/download/fireprime/docs/rk3128_trm/chapter-5-general-register-file(grf).pdf
arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index a7ab0904564f..c37aed28bd10 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -399,6 +399,15 @@ usb_host_ohci: usb@101e0000 {
status = "disabled";
};
+ sfc: spi@1020c000 {
+ compatible = "rockchip,sfc";
+ reg = <0x1020c000 0x8000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ status = "disabled";
+ };
+
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -1155,6 +1164,32 @@ sdmmc_bus4: sdmmc-bus4 {
};
};
+ sfc {
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>;
+ };
+
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>,
+ <1 RK_PD2 3 &pcfg_pull_default>,
+ <1 RK_PD3 3 &pcfg_pull_default>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>;
+ };
+
+ sfc_cs1: sfc-cs1 {
+ rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>;
+ };
+ };
+
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
--
2.45.2
In order to get rid of CLK_NR_CLKS and be able to drop it from the
bindings, use rockchip_clk_find_max_clk_id helper to find the highest
clock id.
Signed-off-by: Alex Bee <[email protected]>
---
changes since v1:
- new patch
drivers/clk/rockchip/clk-rk3128.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index d076b7971f33..40e0e4556d59 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -569,18 +569,22 @@ static const char *const rk3128_critical_clocks[] __initconst = {
"sclk_timer5",
};
-static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
+static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np,
+ unsigned long soc_nr_clks)
{
struct rockchip_clk_provider *ctx;
+ unsigned long common_nr_clks;
void __iomem *reg_base;
+ common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches,
+ ARRAY_SIZE(common_clk_branches)) + 1;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return ERR_PTR(-ENOMEM);
}
- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks));
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
@@ -609,8 +613,12 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
static void __init rk3126_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long soc_nr_clks;
- ctx = rk3128_common_clk_init(np);
+ soc_nr_clks = rockchip_clk_find_max_clk_id(rk3126_clk_branches,
+ ARRAY_SIZE(rk3126_clk_branches)) + 1;
+
+ ctx = rk3128_common_clk_init(np, soc_nr_clks);
if (IS_ERR(ctx))
return;
@@ -627,8 +635,12 @@ CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
static void __init rk3128_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long soc_nr_clks;
+
+ soc_nr_clks = rockchip_clk_find_max_clk_id(rk3128_clk_branches,
+ ARRAY_SIZE(rk3128_clk_branches)) + 1;
- ctx = rk3128_common_clk_init(np);
+ ctx = rk3128_common_clk_init(np, soc_nr_clks);
if (IS_ERR(ctx))
return;
--
2.45.2
Add a clock id for SFC's AHB clock.
Signed-off-by: Alex Bee <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
changes since v1:
- add new clock id at the end
include/dt-bindings/clock/rk3128-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 2616a8791c14..b609fcf96508 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -144,6 +144,7 @@
#define HCLK_TSP 475
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
+#define HCLK_SFC 479
/* soft-reset indices */
#define SRST_CORE0_PO 0
--
2.45.2
Am Donnerstag, 6. Juni 2024, 16:33:59 CEST schrieb Alex Bee:
> CLK_NR_CLKS should not be part of the binding. Let's drop it, since
> the kernel code no longer uses it either.
>
> Signed-off-by: Alex Bee <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Just carrying over an Ack, in v2 [0] Connor provided an
Acked-by: Conor Dooley <[email protected]>
[0] https://lore.kernel.org/all/20240607-dealer-vertebrae-9b22db3dc43b@spud/
On Thu, 6 Jun 2024 16:33:57 +0200, Alex Bee wrote:
> This series adds support for the Serial Flash Controller (SFC) found in
> RK3128 SoCs. The existing driver can be used as-is.
>
> As without using some "id holes" we would run out clock ids when adding the
> additional SFC AHB clock in the binding and would have to touch the ABI, I
> added patches which remove the CLK_NR_CLKS macro and use the recently
> introduced rockchip_clk_find_max_clk_id helper instead to find the highest
> clock id.
>
> [...]
Applied, thanks!
[1/5] clk: rockchip: rk3128: Drop CLK_NR_CLKS usage
commit: 3d0316c949e26392a5098e23c139c932991e50ce
[2/5] dt-bindings: clock: rk3128: Drop CLK_NR_CLKS
commit: 9f22b4fbd4c6d27ca4e5f8fa6632e6d7a846af28
[3/5] dt-bindings: clock: rk3128: Add HCLK_SFC
commit: 469d6e0e70eefe1a31a89a7abd379f169b33b1f4
[4/5] clk: rockchip: Add HCLK_SFC for RK3128
commit: f1fc95b41a3b1b2e613acb04c4f8aee7b87394cc
[5/5] ARM: dts: rockchip: Add SFC for RK3128
commit: 01689df79018c4d68f84a2ac0cf65c35c852b979
Best regards,
--
Heiko Stuebner <[email protected]>