From: Apurva Nandan <[email protected]>
The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each
of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems
in MAIN voltage domain.
The Inter-Processor communication between the main A72 cores and these
R5F and DSP remote cores is achieved through shared memory and
Mailboxes. Thus, add the memory carveouts required for communication.
Signed-off-by: Apurva Nandan <[email protected]>
Signed-off-by: Beleswar Padhi <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 103 ++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index a51925deb43b8..b0b5b6c97b92d 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -49,12 +49,71 @@ secure_ddr: optee@9e800000 {
no-map;
};
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
+ mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c7x_0_memory_region: c7x-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c7x_1_memory_region: c7x-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x1c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
vmain_pd: regulator-0 {
@@ -421,3 +480,47 @@ mbox_c7x_1: mbox-c7x-1 {
ti,mbox-tx = <3 0 0>;
};
};
+
+&wkup_r5fss0 {
+ status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
+ memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+ <&wkup_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0 {
+ status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0 {
+ status = "okay";
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&c7x_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
+ memory-region = <&c7x_0_dma_memory_region>,
+ <&c7x_0_memory_region>;
+};
+
+&c7x_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
+ memory-region = <&c7x_1_dma_memory_region>,
+ <&c7x_1_memory_region>;
+};
--
2.34.1
On 6/7/24 4:04 AM, Beleswar Padhi wrote:
> From: Apurva Nandan <[email protected]>
>
> The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each
> of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems
> in MAIN voltage domain.
>
> The Inter-Processor communication between the main A72 cores and these
> R5F and DSP remote cores is achieved through shared memory and
> Mailboxes. Thus, add the memory carveouts required for communication.
>
> Signed-off-by: Apurva Nandan <[email protected]>
> Signed-off-by: Beleswar Padhi <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 103 ++++++++++++++++++++++++
> 1 file changed, 103 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index a51925deb43b8..b0b5b6c97b92d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -49,12 +49,71 @@ secure_ddr: optee@9e800000 {
> no-map;
> };
>
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa0000000 0x00 0x100000>;
> + no-map;
> + };
> +
> wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
> compatible = "shared-dma-pool";
> reg = <0x00 0xa0100000 0x00 0xf00000>;
> no-map;
> };
>
> + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa1000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa1100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa2000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa2100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa3000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + c7x_0_memory_region: c7x-memory@a3100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa3100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa4000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + c7x_1_memory_region: c7x-memory@a4100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa4100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + rtos_ipc_memory_region: ipc-memories@a5000000 {
> + reg = <0x00 0xa5000000 0x00 0x1c00000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> };
>
> vmain_pd: regulator-0 {
> @@ -421,3 +480,47 @@ mbox_c7x_1: mbox-c7x-1 {
> ti,mbox-tx = <3 0 0>;
> };
> };
> +
> +&wkup_r5fss0 {
> + status = "okay";
> +};
> +
> +&wkup_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
These mboxes where added in the previous patch, why not add these
references in that patch? Or you could probably just merge the two
patches together as they are doing the same logical thing: enabling
remote cores for J722s-EVM.
Andrew
> + memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
> + <&wkup_r5fss0_core0_memory_region>;
> +};
> +
> +&mcu_r5fss0 {
> + status = "okay";
> +};
> +
> +&mcu_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
> + memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
> + <&mcu_r5fss0_core0_memory_region>;
> +};
> +
> +&main_r5fss0 {
> + status = "okay";
> +};
> +
> +&main_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
> + memory-region = <&main_r5fss0_core0_dma_memory_region>,
> + <&main_r5fss0_core0_memory_region>;
> +};
> +
> +&c7x_0 {
> + status = "okay";
> + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
> + memory-region = <&c7x_0_dma_memory_region>,
> + <&c7x_0_memory_region>;
> +};
> +
> +&c7x_1 {
> + status = "okay";
> + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
> + memory-region = <&c7x_1_dma_memory_region>,
> + <&c7x_1_memory_region>;
> +};